2000-12-13 Joel Sherrill <joel@OARcorp.com>

	* configure.in: Added new directories.
	* shared/interrupts/Makefile.am: Added AM_CPPFLAGS to define TX39
	when compiling for a TX3904.
	* shared/interrupts/maxvectors.c: Corrected conditional logic.
	* tx39/Makefile.am: Added vectorisrs.
	* tx39/vectorisrs/Makefile.am, tx39/vectorisrs/vectorisrs.c,
	* tx39/vectorisrs/.cvsignore: New files.  This decodes the
	interrupt pending information on the TX3904 and vectors
	an interrupt.

1 files changed, 41 insertions, 0 deletions

diff --git a/c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c b/c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c
new file mode 100644
index 0000000000..15a4753123
--- /dev/null
+++ b/c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c
@@ -0,0 +1,41 @@
+/*
+ *  $Id$
+ */
+
+#include <rtems.h>
+#include <stdlib.h>
+#include <libcpu/tx3904.h>
+
+#define mips_get_cause( _cause ) \
+  do { \
+    asm volatile( "mfc0 %0, $13; nop" : "=g" (_cause) :  ); \
+  } while (0)
+
+#define CALL_ISR(_vector) \
+    (_ISR_Vector_table[_vector])(_vector);
+
+void mips_vector_isr_handlers( void )
+{
+  unsigned int sr;
+  unsigned int cause;
+
+  mips_get_sr( sr );
+  mips_get_cause( cause );
+
+  cause &= (sr & SR_IMASK);
+  cause >>= CAUSE_IPSHIFT;
+
+  if ( cause & 0x80 )       /* IP[5] ==> INT0 */
+    CALL_ISR( TX3904_IRQ_INT0 );
+
+  if ( cause & 0x40 ) {     /* (IP[4] == 1) ==> IP[0-3] are valid */
+    unsigned int v = (cause >> 2) & 0x0f;
+    CALL_ISR( v );
+  }
+   
+  if ( cause & 0x02 )       /* SW[0] */
+    CALL_ISR( TX3904_IRQ_SOFTWARE_1 );
+
+  if ( cause & 0x01 )       /* IP[1] */
+    CALL_ISR( TX3904_IRQ_SOFTWARE_2 );
+}