diff options
| author | Jay Monkman <jtm@smoothsmoothie.com> | 2005-02-25 05:18:49 +0000 |
|---|---|---|
| committer | Jay Monkman <jtm@smoothsmoothie.com> | 2005-02-25 05:18:49 +0000 |
| commit | 74fb4e1f1d66b129bb144a1b90590bcb1c11332c (patch) | |
| tree | e3fb1cd3233360bd91cdc9184bd219358f9c4d3f /c/src/lib/libcpu/mips/shared | |
| parent | 2005-02-24 Jay Monkman <jtm@lopingdog.com> (diff) | |
| download | rtems-74fb4e1f1d66b129bb144a1b90590bcb1c11332c.tar.bz2 | |
2005-02-24 Jay Monkman <jtm@lopingdog.com>
* Makefile.am, configure.ac: New CPU.
* shared/interrupts/installisrentries.c,
shared/interrupts/isr_entries.S: Added CPU32 support.
* au1x00/Makefile.am, au1x00/include/au1x00.h,
au1x00/vectorisrs/maxvectors.c, au1x00/vectorisrs/vectorisrs.c: New CPU.
Diffstat (limited to 'c/src/lib/libcpu/mips/shared')
| -rw-r--r-- | c/src/lib/libcpu/mips/shared/interrupts/installisrentries.c | 11 | ||||
| -rw-r--r-- | c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S | 30 |
2 files changed, 41 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/mips/shared/interrupts/installisrentries.c b/c/src/lib/libcpu/mips/shared/interrupts/installisrentries.c index 5c2fb62abc..1be985a8b4 100644 --- a/c/src/lib/libcpu/mips/shared/interrupts/installisrentries.c +++ b/c/src/lib/libcpu/mips/shared/interrupts/installisrentries.c @@ -18,6 +18,17 @@ void mips_install_isr_entries( void ) memcpy( (void *)DB_VEC, exc_dbg_code, 40 ); memcpy( (void *)E_VEC, exc_norm_code, 40 ); /* exception vevtor */ +#elif __mips == 32 + void exc_tlb_code(void); + void exc_xtlb_code(void); + void exc_cache_code(void); + void exc_norm_code(void); + + memcpy( (void *)T_VEC, exc_tlb_code, 40 ); /* tlbmiss vector */ + memcpy( (void *)X_VEC, exc_xtlb_code, 40 ); /* xtlbmiss vector */ + memcpy( (void *)C_VEC, exc_cache_code, 40 ); /* cache error vector */ + memcpy( (void *)E_VEC, exc_norm_code, 40 ); /* exception vector */ + #elif __mips == 3 void exc_tlb_code(void); void exc_xtlb_code(void); diff --git a/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S b/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S index 43351dd1d4..89fc538e49 100644 --- a/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S +++ b/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S @@ -41,6 +41,36 @@ FRAME(exc_utlb_code,sp,0,ra) ENDFRAME(exc_utlb_code) /* + * MIPS ISA Level 32 + * XXX Again, reliance on SIM. Not good.?????????? + */ +#elif __mips == 32 +FRAME(exc_tlb_code,sp,0,ra) + la k0, _ISR_Handler + j k0 + nop +ENDFRAME(exc_tlb_code) + +FRAME(exc_xtlb_code,sp,0,ra) + la k0, _ISR_Handler + j k0 + nop + +ENDFRAME(exc_xtlb_code) + +FRAME(exc_cache_code,sp,0,ra) + la k0, _ISR_Handler + j k0 + nop +ENDFRAME(exc_cache_code) + +FRAME(exc_norm_code,sp,0,ra) + la k0, _ISR_Handler /* generic external int hndlr */ + j k0 + nop +ENDFRAME(exc_norm_code) + +/* * MIPS ISA Level 3 * XXX Again, reliance on SIM. Not good. */ |