diff options
author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2001-05-07 13:10:53 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2001-05-07 13:10:53 +0000 |
commit | bbc99f1a6f0984a8cf68027328a0bfdf852721b5 (patch) | |
tree | 2ccc7ffadef545f056b889cddbf309923acdad5b /c/src/lib/libcpu/mips/shared/interrupts | |
parent | 2001-05-07 Joel Sherrill <joel@OARcorp.com> (diff) | |
download | rtems-bbc99f1a6f0984a8cf68027328a0bfdf852721b5.tar.bz2 |
2001-05-07 Joel Sherrill <joel@OARcorp.com>
* shared/interrupts/vectorexceptions.c: New file to decode
exception code and vector appropriate NON-interrupt exception.
* shared/interrupts/Makefile.am: Modified to reflect above.
Diffstat (limited to 'c/src/lib/libcpu/mips/shared/interrupts')
-rw-r--r-- | c/src/lib/libcpu/mips/shared/interrupts/Makefile.am | 2 | ||||
-rw-r--r-- | c/src/lib/libcpu/mips/shared/interrupts/vectorexceptions.c | 90 |
2 files changed, 91 insertions, 1 deletions
diff --git a/c/src/lib/libcpu/mips/shared/interrupts/Makefile.am b/c/src/lib/libcpu/mips/shared/interrupts/Makefile.am index c1fb455e2f..866b0247a9 100644 --- a/c/src/lib/libcpu/mips/shared/interrupts/Makefile.am +++ b/c/src/lib/libcpu/mips/shared/interrupts/Makefile.am @@ -6,7 +6,7 @@ AUTOMAKE_OPTIONS = foreign 1.4 PGM = $(ARCH)/interrupts.rel -C_FILES = installisrentries.c maxvectors.c +C_FILES = installisrentries.c maxvectors.c vectorexceptions.c S_FILES = isr_entries.S diff --git a/c/src/lib/libcpu/mips/shared/interrupts/vectorexceptions.c b/c/src/lib/libcpu/mips/shared/interrupts/vectorexceptions.c new file mode 100644 index 0000000000..708f9ffea8 --- /dev/null +++ b/c/src/lib/libcpu/mips/shared/interrupts/vectorexceptions.c @@ -0,0 +1,90 @@ +/* + * ISR Vectoring support for the Synova Mongoose-V. + * + * COPYRIGHT (c) 1989-2001. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include <rtems.h> +#include <stdlib.h> + +#define mips_get_cause( _cause ) \ + do { \ + asm volatile( "mfc0 %0, $13; nop" : "=r" (_cause) : ); \ + } while (0) + +#define CALL_ISR(_vector) \ + do { \ + if ( _ISR_Vector_table[_vector] ) \ + (_ISR_Vector_table[_vector])(_vector); \ + else \ + mips_default_exception_code_handler(_vector); \ + } while (0) + +#include <bspIo.h> /* for printk */ + +char *cause_strings[32] = { + /* 0 */ "Int", + /* 1 */ "TLB Mods", + /* 2 */ "TLB Load", + /* 3 */ "TLB Store", + /* 4 */ "Address Load", + /* 5 */ "Address Store", + /* 6 */ "Instruction Bus Error", + /* 7 */ "Data Bus Error", + /* 9 */ "Syscall", + /* 10 */ "Breakpoint", + /* 11 */ "Reserved Instruction", + /* 12 */ "Coprocessor Unuseable", + /* 13 */ "Overflow", + /* 14 */ "Trap", + /* 15 */ "Instruction Virtual Coherency Error", + /* 16 */ "FP Exception", + /* 17 */ "Reserved 17", + /* 18 */ "Reserved 17", + /* 19 */ "Reserved 17", + /* 20 */ "Reserved 20", + /* 21 */ "Reserved 21", + /* 22 */ "Reserved 22", + /* 23 */ "Watch", + /* 24 */ "Reserved 24", + /* 25 */ "Reserved 25", + /* 26 */ "Reserved 26", + /* 27 */ "Reserved 27", + /* 28 */ "Reserved 28", + /* 29 */ "Reserved 29", + /* 30 */ "Reserved 30", + /* 31 */ "Data Virtual Coherency Error" +}; + +void mips_default_exception_code_handler( int exc, CPU_Interrupt_frame *frame ) +{ + unsigned int sr; + unsigned int cause; + + mips_get_cause( cause ); + + printk( "Unhandled exception cause %d\n", exc ); + printk( "sr: 0x%08x", sr ); + printk( "cause: 0x%08x --> %s", cause, cause_strings[(cause >> 2) &0x1f] ); + /* XXX dump frame once defined */ + rtems_fatal_error_occurred(1); +} + +void mips_vector_exceptions( CPU_Interrupt_frame *frame ) +{ + unsigned int cause; + int exc; + + mips_get_cause( cause ); + exc = (cause >> 2) &0x1f; + + printk( "Exception!\n" ); + mips_default_exception_code_handler( exc, frame ); +} |