2000-12-13 Joel Sherrill <joel@OARcorp.com>

	* shared/.cvsignore, shared/Makefile.am,
	shared/cache/.cvsignore, shared/cache/Makefile.am,
	shared/cache/cache.c, shared/cache/cache_.h,
	shared/interrupts/.cvsignore, shared/interrupts/Makefile.am,
	shared/interrupts/installisrentries.c,
	shared/interrupts/isr_entries.S,
	shared/interrupts/maxvectors.c, tx39/.cvsignore,
	tx39/Makefile.am, tx39/include/.cvsignore,
	tx39/include/Makefile.am, tx39/include/tx3904.h: New file.
	Moved some pieces of interrupt processing from score/cpu to
	libcpu/mips since many interrupt servicing characteristics are
	CPU model dependent.  This patch addresses the number of interrupt
	sources and where the ISR prologues are located.  The only way to
	currently install the ISR prologues requires that the prologues
	be installed into RAM.

1 files changed, 29 insertions, 0 deletions

diff --git a/c/src/lib/libcpu/mips/shared/interrupts/maxvectors.c b/c/src/lib/libcpu/mips/shared/interrupts/maxvectors.c
new file mode 100644
index 0000000000..c1e5df20a4
--- /dev/null
+++ b/c/src/lib/libcpu/mips/shared/interrupts/maxvectors.c
@@ -0,0 +1,29 @@
+/* 
+ *  This file contains the maximum number of vectors.  This can not
+ *  be determined without knowing the RTEMS CPU model. 
+ *
+ *  COPYRIGHT (c) 1989-2000.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+
+/*
+ *  The tx3904 attaches 4 of the eight interrupt bits to an on-CPU interrupt
+ *  controller so that these four bits map to 16 unique interrupts.
+ *  So you have: 2 software interrupts, an NMI, and 16 others.
+ */
+#if defined(tx3904)
+#define MAX_VECTORS 19
+#endif
+
+#ifndef MAX
+#define MAX_VECTORS 8
+#endif
+
+unsigned int mips_interrupt_number_of_vectors = MAX_VECTORS;