diff options
author | Greg Menke <gregory.menke@gsfc.nasa.gov> | 2006-06-08 18:03:55 +0000 |
---|---|---|
committer | Greg Menke <gregory.menke@gsfc.nasa.gov> | 2006-06-08 18:03:55 +0000 |
commit | 7c990076419ff4a80999dcc04985688cd5bea5ce (patch) | |
tree | 5199f71be51bf7f51705f85683cd0f9aa4a5765d /c/src/lib/libcpu/mips/shared/interrupts/interruptmask.c | |
parent | Preps for VPATH builts. (diff) | |
download | rtems-7c990076419ff4a80999dcc04985688cd5bea5ce.tar.bz2 |
B.Robinson MIPS patch
Diffstat (limited to 'c/src/lib/libcpu/mips/shared/interrupts/interruptmask.c')
-rw-r--r-- | c/src/lib/libcpu/mips/shared/interrupts/interruptmask.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/mips/shared/interrupts/interruptmask.c b/c/src/lib/libcpu/mips/shared/interrupts/interruptmask.c new file mode 100644 index 0000000000..27be57b46b --- /dev/null +++ b/c/src/lib/libcpu/mips/shared/interrupts/interruptmask.c @@ -0,0 +1,24 @@ +/* + * $Id: interruptmask.c,v 1.0 2006/04/04 05:18:49 + */ + +#include <rtems.h> + +/* + * This function returns a mask value which is used to select the bits + * in the processor status register that can be set to enable interrupts. + * The mask value should not include the 2 software interrupt enable bits. + */ + +uint32_t mips_interrupt_mask( void ) +{ + uint32_t interrupt_mask; + +#ifdef TX49 + interrupt_mask = 0x00000400; /* Toshiba TX49 processors have a non-standard interrupt mask */ +#else + interrupt_mask = 0x0000fc00; +#endif + + return(interrupt_mask); +} |