diff options
author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-12-13 17:52:53 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-12-13 17:52:53 +0000 |
commit | b4d0d18eeda3ee81816c33140de46bb6bc724d43 (patch) | |
tree | 13ff75e525be655fcfa9119b7f379d71de069635 /c/src/lib/libcpu/mips/shared/interrupts/installisrentries.c | |
parent | changed version to ss-20001211 (diff) | |
download | rtems-b4d0d18eeda3ee81816c33140de46bb6bc724d43.tar.bz2 |
2000-12-13 Joel Sherrill <joel@OARcorp.com>
* shared/.cvsignore, shared/Makefile.am,
shared/cache/.cvsignore, shared/cache/Makefile.am,
shared/cache/cache.c, shared/cache/cache_.h,
shared/interrupts/.cvsignore, shared/interrupts/Makefile.am,
shared/interrupts/installisrentries.c,
shared/interrupts/isr_entries.S,
shared/interrupts/maxvectors.c, tx39/.cvsignore,
tx39/Makefile.am, tx39/include/.cvsignore,
tx39/include/Makefile.am, tx39/include/tx3904.h: New file.
Moved some pieces of interrupt processing from score/cpu to
libcpu/mips since many interrupt servicing characteristics are
CPU model dependent. This patch addresses the number of interrupt
sources and where the ISR prologues are located. The only way to
currently install the ISR prologues requires that the prologues
be installed into RAM.
Diffstat (limited to 'c/src/lib/libcpu/mips/shared/interrupts/installisrentries.c')
-rw-r--r-- | c/src/lib/libcpu/mips/shared/interrupts/installisrentries.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/mips/shared/interrupts/installisrentries.c b/c/src/lib/libcpu/mips/shared/interrupts/installisrentries.c new file mode 100644 index 0000000000..5dd37f82bb --- /dev/null +++ b/c/src/lib/libcpu/mips/shared/interrupts/installisrentries.c @@ -0,0 +1,29 @@ +/* + * $Id$ + */ + +#include <rtems.h> +#include <idtcpu.h> +#include <stdlib.h> + +void mips_install_isr_entries( void ) +{ +#if __mips == 1 + void exc_utlb_code(void); + void exc_norm_code(void); + + memcpy( (void *)UT_VEC, exc_utlb_code, 40 ); /* utlbmiss vector */ + memcpy( (void *)E_VEC, exc_norm_code, 40 ); /* exception vevtor */ +#elif __mips == 3 + void exc_tlb_code(void); + void exc_utlb_code(void); + void exc_cache_code(void); + void exc_norm_code(void); + + memcpy( (void *)T_VEC, exc_tlb_code, 40 ); /* tlbmiss vector */ + memcpy( (void *)X_VEC, exc_xtlb_code, 40 ); /* xtlbmiss vector */ + memcpy( (void *)C_VEC, exc_cache_code, 40 ); /* cache error vector */ + memcpy( (void *)E_VEC, exc_norm_code, 40 ); /* exception vector */ +#endif + rtems_cache_flush_entire_data(); +} |