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author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2002-02-01 15:15:02 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2002-02-01 15:15:02 +0000 |
commit | 2835b3a5683ef8dc6b6e7da02c7754ac5d700344 (patch) | |
tree | 8c585d994dd5d63425a1d66d677cc2bd109f9413 /c/src/lib/libcpu/mips/mongoosev/README | |
parent | 2001-02-01 Greg Menke <gregory.menke@gsfc.nasa.gov> (diff) | |
download | rtems-2835b3a5683ef8dc6b6e7da02c7754ac5d700344.tar.bz2 |
2001-02-01 Greg Menke <gregory.menke@gsfc.nasa.gov>
* Lots of tinkering and tuning as part of improving interrupt latency
and improving the per-task interrupt level control and FP mask handling.
With these modifications interrupt latency was measured at a worst-case
of 100us, average below 60 us on a 12 Mhz R3000 class CPU with 50
RTEMS tasks in the application.
* mongoosev/README: Updated.
* mongoosev/include/mongoose-v.h: Masks modified.
* mongoosev/vectorisrs/vectorisrs.c: Significant overhaul to address
software prioritization of interrupts. If a higher priority interrupt
occurs while we are looking for new interrupts, we will reinitiate the
scan of all interrupts.
* shared/interrupts/vectorexceptions.c: Removed warning and deleted
blank lines.
Diffstat (limited to 'c/src/lib/libcpu/mips/mongoosev/README')
-rw-r--r-- | c/src/lib/libcpu/mips/mongoosev/README | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/mips/mongoosev/README b/c/src/lib/libcpu/mips/mongoosev/README index c7e4e9f8ef..76a8a7529e 100644 --- a/c/src/lib/libcpu/mips/mongoosev/README +++ b/c/src/lib/libcpu/mips/mongoosev/README @@ -4,3 +4,57 @@ The Synova Mongoose-V is a radiation hardened derivative of the LSI 33K with on-CPU peripherals. + +Status +====== + +Per-task floating point enable/disable is supported for both immediate +and deferred FPU context swaps. + +Interrupt Levels are adapted reasonably well to the MIPS interrupt +model. Bit 0 of the int level is a global enable/disable, corresponding +to bit 0 of the processor's SR register. Bits 1 thru 6 are configured +as masks for the Int0 thru Int5 interrupts. The 2 software interrupt +bits are always enabled by default. Each task maintains its own +Interrupt Level setting, reconfiguring the SR register's interrupt bits +whenever scheduled in. The software ints, though not addressable via +the various Interrupt Level functions, are maintained on a per-task +basis, so if software manipulates them directly, things should behave as +expected. At the time of these udpates, the Interrupt Level was only 8 +bits, and completely supporting the global enable, software ints and the +hardware ints would require 9 bits. When more than 8 bits are +available, there is no reason the software interrupts could not be added +to the Interrupt Level. + +While supporting the Int0 thru Int5 bits in this way doesn't seem +wonderfully useful, it does increase the level of compliance with the +RTEMS spec. + +Interrupt Level 0 corresponds to interrupts globally enabled, software +ints enabled and Int0 thru Int5 enabled. If values other than 0 are +supplied, they should be formulated to impose the desired bitmask. +Interrupt priority is not a strong concept on this bsp, it is provided +only by the order in which interrupts are checked. + +If during the vectoring of an interrupt, others arrive, they will all be +processed in accordance with their ordering in SR & the peripheral +register. For example, if while we're vectoring Int4, Int3 and Int5 are +asserted, Int3 will be serviced before Int5. The peripheral interrupts +are individually vectored as a consequence of Int5 being asserted, +however Int5 is not itself vectored. Within the set of peripheral +interrupts, bit 0 is vectored first, 31 is last. + +Interrupts are not nested for MIPS1 or MIPS3 processors, but are +processed serially as possible. On an unloaded 50 task RTEMS program, +runnning on a 12mhz MIPS1 processor, worst-case latencies of 100us were +observed, the average being down at 60us or below. + + +These features are principally a consequence of fixes and tweaks to the +MIPS1 and MIPS3 processor support, and should be equally effective on +both levels of MIPS processors for any of their bsp's. + + + + + |