2008-07-04 Matthew Riek <matthew.riek@ibiscomputer.com.au>

	* Makefile.am, mcf532x/include/mcf532x.h, shared/cache/cache_.h: Add
	cache support for 5329. Enable the cache in copyback and
	write-through so we can assume that in BSP.
	* mcf532x/cache/cachepd.c: New file.

5 files changed, 179 insertions, 1 deletions

diff --git a/c/src/lib/libcpu/m68k/ChangeLog b/c/src/lib/libcpu/m68k/ChangeLog
index 85005c3799..870d7f8a55 100644
--- a/c/src/lib/libcpu/m68k/ChangeLog
+++ b/c/src/lib/libcpu/m68k/ChangeLog
@@ -1,3 +1,10 @@
+2008-07-04	Matthew Riek <matthew.riek@ibiscomputer.com.au>
+
+	* Makefile.am, mcf532x/include/mcf532x.h, shared/cache/cache_.h: Add
+	cache support for 5329. Enable the cache in copyback and
+	write-through so we can assume that in BSP.
+	* mcf532x/cache/cachepd.c: New file.
+
 2008-06-20	Matthew Riek <matthew.riek@ibiscomputer.com.au>
 
 	* Makefile.am, configure.ac, preinstall.am: Adding mcf5329 BSP and CPU
diff --git a/c/src/lib/libcpu/m68k/Makefile.am b/c/src/lib/libcpu/m68k/Makefile.am
index 6e1ac1260f..8796fc9aa1 100644
--- a/c/src/lib/libcpu/m68k/Makefile.am
+++ b/c/src/lib/libcpu/m68k/Makefile.am
@@ -109,6 +109,12 @@ if mcf532x
 ## mcf532x/include
 include_mcf532xdir = $(includedir)/mcf532x
 include_mcf532x_HEADERS = mcf532x/include/mcf532x.h
+
+## mcf532x/cache
+noinst_PROGRAMS += mcf532x/cachepd.rel
+mcf532x_cachepd_rel_SOURCES = mcf532x/cache/cachepd.c
+mcf532x_cachepd_rel_CPPFLAGS = $(AM_CPPFLAGS)
+mcf532x_cachepd_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
 endif
 
 if mcf5272
diff --git a/c/src/lib/libcpu/m68k/mcf532x/cache/cachepd.c b/c/src/lib/libcpu/m68k/mcf532x/cache/cachepd.c
new file mode 100644
index 0000000000..f37117fb7b
--- /dev/null
+++ b/c/src/lib/libcpu/m68k/mcf532x/cache/cachepd.c
@@ -0,0 +1,139 @@
+/*
+ *  Cache Management Support Routines for the MCF532x
+ *
+ *  $Id:
+ */
+
+#include <rtems.h>
+#include <mcf532x/mcf532x.h>
+
+#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr))
+
+/*
+ * Read/write copy of common cache
+ *  Default cache mode is *disabled* (cache only ACRx areas)
+ *  Allow CPUSHL to invalidate a cache line
+ *  Enable store buffer
+ */
+static uint32_t cacr_mode = MCF_CACR_ESB |
+                              MCF_CACR_DCM(3);
+
+/*
+ * Cannot be frozen
+ */
+void _CPU_cache_freeze_data(void)
+{
+}
+
+void _CPU_cache_unfreeze_data(void)
+{
+}
+
+void _CPU_cache_freeze_instruction(void)
+{
+}
+
+void _CPU_cache_unfreeze_instruction(void)
+{
+}
+
+void _CPU_cache_flush_1_data_line(const void *d_addr)
+{
+  register unsigned long adr = (((unsigned long) d_addr >> 4) & 0xff) << 4;
+
+  asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
+  adr += 1;
+  asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
+  adr += 1;
+  asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
+  adr += 1;
+  asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));  
+}
+
+void _CPU_cache_flush_entire_data(void)
+{
+  register unsigned long set, adr;
+  
+  for(set = 0; set < 256; ++set) {
+    adr = (set << 4);
+    asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
+    adr += 1;
+    asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
+    adr += 1;
+    asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
+    adr += 1;
+    asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));  
+  }
+}
+
+void _CPU_cache_enable_instruction(void)
+{
+  rtems_interrupt_level level;
+
+  rtems_interrupt_disable(level);
+  if(!(cacr_mode & MCF_CACR_CENB))
+  {
+    cacr_mode |= MCF_CACR_CENB;
+    m68k_set_cacr(cacr_mode);
+  }
+  rtems_interrupt_enable(level);
+}
+
+void _CPU_cache_disable_instruction(void)
+{
+  rtems_interrupt_level level;
+
+  rtems_interrupt_disable(level);
+  if((cacr_mode & MCF_CACR_CENB))
+  {
+    cacr_mode &= ~MCF_CACR_CENB;
+    m68k_set_cacr(cacr_mode);
+  }
+  rtems_interrupt_enable(level);
+}
+
+void _CPU_cache_invalidate_entire_instruction(void)
+{
+  m68k_set_cacr(cacr_mode | MCF_CACR_CINVA);
+}
+
+void _CPU_cache_invalidate_1_instruction_line(const void *addr)
+{
+  register unsigned long adr = (((unsigned long) addr >> 4) & 0xff) << 4;
+
+  asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
+  adr += 1;
+  asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
+  adr += 1;
+  asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
+  adr += 1;
+  asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
+}
+
+void _CPU_cache_enable_data(void)
+{
+  /*
+   * The 532x has a unified data and instruction cache, so we call through
+   * to enable instruction.
+   */
+  _CPU_cache_enable_instruction();
+}
+
+void _CPU_cache_disable_data(void)
+{
+  /*
+   * The 532x has a unified data and instruction cache, so we call through
+   * to disable instruction.
+   */
+  _CPU_cache_disable_instruction();
+}
+
+void _CPU_cache_invalidate_entire_data(void)
+{
+  _CPU_cache_invalidate_entire_instruction();
+}
+
+void _CPU_cache_invalidate_1_data_line(const void *addr)
+{
+  _CPU_cache_invalidate_1_instruction_line(addr);
+} 
diff --git a/c/src/lib/libcpu/m68k/mcf532x/include/mcf532x.h b/c/src/lib/libcpu/m68k/mcf532x/include/mcf532x.h
index 85ebf04b26..798fb1175b 100644
--- a/c/src/lib/libcpu/m68k/mcf532x/include/mcf532x.h
+++ b/c/src/lib/libcpu/m68k/mcf532x/include/mcf532x.h
@@ -8,6 +8,29 @@
 
 /*********************************************************************
 *
+* Cache
+*
+*********************************************************************/
+
+#define MCF_CACR_CENB                     (1 << 31)
+#define MCF_CACR_ESB                      (1 << 29)
+#define MCF_CACR_DPI                      (1 << 28)
+#define MCF_CACR_HLCK                     (1 << 27)
+#define MCF_CACR_CINVA                    (1 << 24)
+#define MCF_CACR_DNFB                     (1 << 10)
+#define MCF_CACR_DCM(A)                   (((A) & 0x3) << 8)
+#define MCF_CACR_DW                       (1 << 5)
+#define MCF_CACR_EUSP                     (1 << 4)
+
+#define MCF_ACR_ADDR_BASE(A)              (((A) & 0xFF) << 24)
+#define MCF_ACR_ADDR_MASK(A)              (((A) & 0xFF) << 16)
+#define MCF_ACR_E                         (1 << 15)
+#define MCF_ACR_S(A)                      (((A) & 0x3) << 13)
+#define MCF_ACR_CM(A)                     (((A) & 0x3) << 5)
+#define MCF_ACR_W                         (1 << 2)
+
+/*********************************************************************
+*
 * System Control Module (SCM)
 *
 *********************************************************************/
@@ -1243,7 +1266,7 @@
 #define MCF_EDMA_TCD13_CSR                   (*(vuint16*)(0xFC0451BE))
 #define MCF_EDMA_TCD14_CSR                   (*(vuint16*)(0xFC0451DE))
 #define MCF_EDMA_TCD15_CSR                   (*(vuint16*)(0xFC0451FE))
-#define MCF_EDMA_TCD_CSR(x)                  (*(vuint16*)(0xFC04501E+((x)*0x020)))
+#define MCF_EDMA_TCD_CSR(x)                  (*(vuint16*)(0xFC04501E +((x)*0x020)))
 
 /* Bit definitions and macros for MCF_EDMA_CR */
 #define MCF_EDMA_CR_EDBG                     (0x00000002)
diff --git a/c/src/lib/libcpu/m68k/shared/cache/cache_.h b/c/src/lib/libcpu/m68k/shared/cache/cache_.h
index 62a9fd8541..55f20de182 100644
--- a/c/src/lib/libcpu/m68k/shared/cache/cache_.h
+++ b/c/src/lib/libcpu/m68k/shared/cache/cache_.h
@@ -18,6 +18,9 @@
 # if ( defined(__mcf528x__) )
 #  define M68K_DATA_CACHE_ALIGNMENT 16
 # endif
+#elif ( defined(__mcf5300__) )
+# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
+# define M68K_DATA_CACHE_ALIGNMENT 16
 #endif
 
 #if defined(M68K_DATA_CACHE_ALIGNMENT)