diff options
author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-06-13 21:53:38 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-06-13 21:53:38 +0000 |
commit | cf1f72ea339287cf6f780b2e34b8092ce08da6b0 (patch) | |
tree | 3b6eee762364ef5304ebae3bf5da4e9296eafa29 /c/src/lib/libcpu/m68k/shared | |
parent | Added .cvsignore. (diff) | |
download | rtems-cf1f72ea339287cf6f780b2e34b8092ce08da6b0.tar.bz2 |
Moved i386 and m68k cache management code to libcpu. Everything
now is an implementation of the prototypes in rtems/rtems/cache.h.
The libcpu/i386/wrapup directory is no longer needed.
The PowerPC needs this done to it.
Diffstat (limited to 'c/src/lib/libcpu/m68k/shared')
-rw-r--r-- | c/src/lib/libcpu/m68k/shared/Makefile.am | 10 | ||||
-rw-r--r-- | c/src/lib/libcpu/m68k/shared/cache/Makefile.am | 38 | ||||
-rw-r--r-- | c/src/lib/libcpu/m68k/shared/cache/cache.c | 192 | ||||
-rw-r--r-- | c/src/lib/libcpu/m68k/shared/cache/cache_.h | 29 |
4 files changed, 269 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/m68k/shared/Makefile.am b/c/src/lib/libcpu/m68k/shared/Makefile.am new file mode 100644 index 0000000000..3f7ad1d7a6 --- /dev/null +++ b/c/src/lib/libcpu/m68k/shared/Makefile.am @@ -0,0 +1,10 @@ +## +## $Id$ +## + +AUTOMAKE_OPTIONS = foreign 1.4 + +SUBDIRS = cache + +include $(top_srcdir)/../../../../../automake/subdirs.am +include $(top_srcdir)/../../../../../automake/local.am diff --git a/c/src/lib/libcpu/m68k/shared/cache/Makefile.am b/c/src/lib/libcpu/m68k/shared/cache/Makefile.am new file mode 100644 index 0000000000..d94c4388c9 --- /dev/null +++ b/c/src/lib/libcpu/m68k/shared/cache/Makefile.am @@ -0,0 +1,38 @@ +## +## $Id$ +## + +AUTOMAKE_OPTIONS = foreign 1.4 +ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal + +VPATH = @srcdir@:@srcdir@/../../../shared/src + +C_FILES = cache.c cache_aligned_malloc.c cache_manager.c +C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) + +H_FILES = cache_.h +INSTALLED_H_FILES = + +OBJS = $(C_O_FILES) + +include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg +include $(top_srcdir)/../../../../../automake/lib.am + +AM_CPPFLAGS += -I$(srcdir) + +$(PROJECT_INCLUDE)/libcpu: + $(mkinstalldirs) $@ + +$(PROJECT_INCLUDE)/libcpu/%.h: %.h + $(INSTALL_DATA) $< $@ + +$(PROJECT_INCLUDE)/libcpu/cache.h: $(top_srcdir)/../shared/include/cache.h + $(INSTALL_DATA) $< $@ + +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu $(PROJECT_INCLUDE)/libcpu/cache.h + +all-local: $(ARCH) $(PREINSTALL_FILES) $(OBJS) + +EXTRA_DIST = cache.c cache_.h + +include $(top_srcdir)/../../../../../automake/local.am diff --git a/c/src/lib/libcpu/m68k/shared/cache/cache.c b/c/src/lib/libcpu/m68k/shared/cache/cache.c new file mode 100644 index 0000000000..ce98f006c6 --- /dev/null +++ b/c/src/lib/libcpu/m68k/shared/cache/cache.c @@ -0,0 +1,192 @@ +/* + * Cache Management Support Routines for the MC68040 + * + * $Id$ + */ + +#include <rtems.h> +#include "cache_.h" + +/* + * Since the cacr is common to all mc680x0, provide macros + * for masking values in that register. + */ + +/* + * Used to clear bits in the cacr. + */ +#define _CPU_CACR_AND(mask) \ + { \ + register unsigned long _value = mask; \ + register unsigned long _ctl = 0; \ + asm volatile ( "movec %%cacr, %0; /* read the cacr */ \ + andl %2, %0; /* and with _val */ \ + movec %1, %%cacr" /* write the cacr */ \ + : "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" ); \ + } + + +/* + * Used to set bits in the cacr. + */ +#define _CPU_CACR_OR(mask) \ + { \ + register unsigned long _value = mask; \ + register unsigned long _ctl = 0; \ + asm volatile ( "movec %%cacr, %0; /* read the cacr */ \ + orl %2, %0; /* or with _val */ \ + movec %1, %%cacr" /* write the cacr */ \ + : "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" ); \ + } + + +/* + * CACHE MANAGER: The following functions are CPU-specific. + * They provide the basic implementation for the rtems_* cache + * management routines. If a given function has no meaning for the CPU, + * it does nothing by default. + */ +#if ( defined(__mc68020__) || defined(__mc68030__) ) + +#if defined(__mc68030__) + +/* Only the mc68030 has a data cache; it is writethrough only. */ + +void _CPU_flush_1_data_cache_line ( const void * d_addr ) {} +void _CPU_flush_entire_data_cache ( const void * d_addr ) {} + +void _CPU_invalidate_1_data_cache_line ( + const void * d_addr ) +{ + void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); + asm volatile ( "movec %0, %%caar" :: "a" (p_address) ); /* write caar */ + _CPU_CACR_OR(0x00000400); +} + +void _CPU_invalidate_entire_data_cache ( void ) +{ + _CPU_CACR_OR( 0x00000800 ); +} + +void _CPU_freeze_data_cache ( void ) +{ + _CPU_CACR_OR( 0x00000200 ); +} + +void _CPU_unfreeze_data_cache ( void ) +{ + _CPU_CACR_AND( 0xFFFFFDFF ); +} + +void _CPU_enable_data_cache ( void ) +{ + _CPU_CACR_OR( 0x00000100 ); +} +void _CPU_disable_data_cache ( void ) +{ + _CPU_CACR_AND( 0xFFFFFEFF ); +} +#endif + + +/* Both the 68020 and 68030 have instruction caches */ + +void _CPU_invalidate_1_inst_cache_line ( + const void * d_addr ) +{ + void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); + asm volatile ( "movec %0, %%caar" :: "a" (p_address) ); /* write caar */ + _CPU_CACR_OR( 0x00000004 ); +} + +void _CPU_invalidate_entire_inst_cache ( void ) +{ + _CPU_CACR_OR( 0x00000008 ); +} + +void _CPU_freeze_inst_cache ( void ) +{ + _CPU_CACR_OR( 0x00000002); +} + +void _CPU_unfreeze_inst_cache ( void ) +{ + _CPU_CACR_AND( 0xFFFFFFFD ); +} + +void _CPU_enable_inst_cache ( void ) +{ + _CPU_CACR_OR( 0x00000001 ); +} + +void _CPU_disable_inst_cache ( void ) +{ + _CPU_CACR_AND( 0xFFFFFFFE ); +} + + +#elif ( defined(__mc68040__) || defined (__mc68060__) ) + +/* Cannot be frozen */ +void _CPU_freeze_data_cache ( void ) {} +void _CPU_unfreeze_data_cache ( void ) {} +void _CPU_freeze_inst_cache ( void ) {} +void _CPU_unfreeze_inst_cache ( void ) {} + +void _CPU_flush_1_data_cache_line ( + const void * d_addr ) +{ + void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); + asm volatile ( "cpushl %%dc,(%0)" :: "a" (p_address) ); +} + +void _CPU_invalidate_1_data_cache_line ( + const void * d_addr ) +{ + void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); + asm volatile ( "cinvl %%dc,(%0)" :: "a" (p_address) ); +} + +void _CPU_flush_entire_data_cache ( void ) +{ + asm volatile ( "cpusha %%dc" :: ); +} + +void _CPU_invalidate_entire_data_cache ( void ) +{ + asm volatile ( "cinva %%dc" :: ); +} + +void _CPU_enable_data_cache ( void ) +{ + _CPU_CACR_OR( 0x80000000 ); +} + +void _CPU_disable_data_cache ( void ) +{ + _CPU_CACR_AND( 0x7FFFFFFF ); +} + +void _CPU_invalidate_1_inst_cache_line ( + const void * i_addr ) +{ + void * p_address = (void *) _CPU_virtual_to_physical( i_addr ); + asm volatile ( "cinvl %%ic,(%0)" :: "a" (p_address) ); +} + +void _CPU_invalidate_entire_inst_cache ( void ) +{ + asm volatile ( "cinva %%ic" :: ); +} + +void _CPU_enable_inst_cache ( void ) +{ + _CPU_CACR_OR( 0x00008000 ); +} + +void _CPU_disable_inst_cache ( void ) +{ + _CPU_CACR_AND( 0xFFFF7FFF ); +} +#endif +/* end of file */ diff --git a/c/src/lib/libcpu/m68k/shared/cache/cache_.h b/c/src/lib/libcpu/m68k/shared/cache/cache_.h new file mode 100644 index 0000000000..13406b3c49 --- /dev/null +++ b/c/src/lib/libcpu/m68k/shared/cache/cache_.h @@ -0,0 +1,29 @@ +/* + * M68K Cache Manager Support + */ + +#ifndef __M68K_CACHE_h +#define __M68K_CACHE_h + +#if defined(__mc68020__) +#define M68K_INST_CACHE_ALIGNMENT 16 +#elif defined(__mc68030__) +#define M68K_INST_CACHE_ALIGNMENT 16 +#define M68K_DATA_CACHE_ALIGNMENT 16 +#elif ( defined(__mc68040__) || defined (__mc68060__) ) +#define M68K_INST_CACHE_ALIGNMENT 16 +#define M68K_DATA_CACHE_ALIGNMENT 16 +#endif + +#if defined(M68K_DATA_CACHE_ALIGNMENT) +#define _CPU_DATA_CACHE_ALIGNMENT M68K_DATA_CACHE_ALIGNMENT +#endif + +#if defined(M68K_INST_CACHE_ALIGNMENT) +#define _CPU_INST_CACHE_ALIGNMENT M68K_INST_CACHE_ALIGNMENT +#endif + +#include <libcpu/cache.h> + +#endif +/* end of include file */ |