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author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-07-11 19:31:04 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-07-11 19:31:04 +0000 |
commit | bc85fd5a6df8753543ba55c98a588e255471752b (patch) | |
tree | b51e3eb5c77cca042081bb7ba88e5515560451d2 /c/src/lib/libcpu/i960/i960rp/cpu_install_raw_isr.c | |
parent | Patch rtems-rc-20000711-2-cvs.diff from Ralf Corsepius <corsepiu@faw.uni-ulm.de> (diff) | |
download | rtems-bc85fd5a6df8753543ba55c98a588e255471752b.tar.bz2 |
Reworked score/cpu/i960 so it can be safely compiled multilib. All
routines and structures that require CPU model specific information
are now in libcpu. This required significant rework of the
score/cpu header files and the creation of multiple header files
and subdirectories in libcpu/i960.
Diffstat (limited to 'c/src/lib/libcpu/i960/i960rp/cpu_install_raw_isr.c')
-rw-r--r-- | c/src/lib/libcpu/i960/i960rp/cpu_install_raw_isr.c | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/i960/i960rp/cpu_install_raw_isr.c b/c/src/lib/libcpu/i960/i960rp/cpu_install_raw_isr.c new file mode 100644 index 0000000000..9ee56993a5 --- /dev/null +++ b/c/src/lib/libcpu/i960/i960rp/cpu_install_raw_isr.c @@ -0,0 +1,37 @@ +/* + * Install raw interrupt vector for i960RP + * + * $Id$ + */ + +#include <rtems.h> +#include <libcpu/i960RP.h> + +#define i960_vector_caching_enabled( _prcb ) \ + ((*((unsigned int *) ICON_ADDR)) & 0x2000) + +extern i960_PRCB *Prcb; + +void _CPU_ISR_install_raw_handler( + unsigned32 vector, + proc_ptr new_handler, + proc_ptr *old_handler +) +{ + i960_PRCB *prcb = &Prcb; + proc_ptr *cached_intr_tbl = NULL; + + /* The i80960RP does not support vectors 0-7. The first 9 entries + * in the Interrupt Table are used to manage pending interrupts. + * Thus vector 8, the first valid vector number, is actually in + * slot 9 in the table. + */ + + *old_handler = prcb->intr_tbl[ vector + 1 ]; + + prcb->intr_tbl[ vector + 1 ] = new_handler; + + if ( i960_vector_caching_enabled( prcb ) ) + if ( (vector & 0xf) == 0x2 ) /* cacheable? */ + cached_intr_tbl[ vector >> 4 ] = new_handler; +} |