Patch from John Cotton <john.cotton@nrc.ca> to correct cache

routine naming to follow RTEMS package/object.method rule.
This patch also eliminated calls to the obsolete routine
m68k_enable_caching.

3 files changed, 22 insertions, 29 deletions

diff --git a/c/src/lib/libcpu/i386/cache.c b/c/src/lib/libcpu/i386/cache.c
index 976f00e5e1..57dfee283d 100644
--- a/c/src/lib/libcpu/i386/cache.c
+++ b/c/src/lib/libcpu/i386/cache.c
@@ -15,7 +15,7 @@ void _CPU_disable_cache() {
   regCr0.cr0.page_level_cache_disable = 1;
   regCr0.cr0.no_write_through = 1;
   i386_set_cr0( regCr0.i );
-  rtems_flush_entire_data_cache();
+  rtems_cache_flush_entire_data();
 }
 
 /*
@@ -29,7 +29,7 @@ void _CPU_enable_cache() {
   regCr0.cr0.page_level_cache_disable = 0;
   regCr0.cr0.no_write_through = 0;
   i386_set_cr0( regCr0.i );
-  /*rtems_flush_entire_data_cache();*/
+  /*rtems_cache_flush_entire_data();*/
 }
 
 /*
@@ -38,56 +38,49 @@ void _CPU_enable_cache() {
  * management routines. If a given function has no meaning for the CPU,
  * it does nothing by default.
  *
- * FIXME: Definitions for I386_CACHE_ALIGNMENT are missing above for
- *        each CPU. The routines below should be implemented per CPU,
+ * FIXME: The routines below should be implemented per CPU,
  *        to accomodate the capabilities of each.
  */
 
-/* FIXME: I don't belong here. */
-#define I386_CACHE_ALIGNMENT 16
-
 #if defined(I386_CACHE_ALIGNMENT)
-#define _CPU_DATA_CACHE_ALIGNMENT I386_CACHE_ALIGNMENT
-#define _CPU_INST_CACHE_ALIGNEMNT I386_CACHE_ALIGNMENT
-
-void _CPU_flush_1_data_cache_line(const void *d_addr) {}
-void _CPU_invalidate_1_data_cache_line(const void *d_addr) {}
-void _CPU_freeze_data_cache(void) {}
-void _CPU_unfreeze_data_cache(void) {}
-void _CPU_invalidate_1_inst_cache_line ( const void *d_addr ) {}
-void _CPU_freeze_inst_cache(void) {}
-void _CPU_unfreeze_inst_cache(void) {}
-
-void _CPU_flush_entire_data_cache(void)
+void _CPU_cache_flush_1_data_line(const void *d_addr) {}
+void _CPU_cache_invalidate_1_data_line(const void *d_addr) {}
+void _CPU_cache_freeze_data(void) {}
+void _CPU_cache_unfreeze_data(void) {}
+void _CPU_cache_invalidate_1_instruction_line ( const void *d_addr ) {}
+void _CPU_cache_freeze_instruction(void) {}
+void _CPU_cache_unfreeze_instruction(void) {}
+
+void _CPU_cache_flush_entire_data(void)
 {
   asm volatile ("wbinvd");
 }
-void _CPU_invalidate_entire_data_cache(void)
+void _CPU_cache_invalidate_entire_data(void)
 {
   asm volatile ("invd");
 }
 
-void _CPU_enable_data_cache(void)
+void _CPU_cache_enable_data(void)
 {
         _CPU_enable_cache();
 }
 
-void _CPU_disable_data_cache(void)
+void _CPU_cache_disable_data(void)
 {
         _CPU_disable_cache();
 }
 
-void _CPU_invalidate_entire_inst_cache(void)
+void _CPU_cache_invalidate_entire_instruction(void)
 {
   asm volatile ("invd");
 }
 
-void _CPU_enable_inst_cache(void)
+void _CPU_cache_enable_instruction(void)
 {
   _CPU_enable_cache();
 }
 
-void _CPU_disable_inst_cache( void )
+void _CPU_cache_disable_instruction( void )
 {
   _CPU_disable_cache();
 }
diff --git a/c/src/lib/libcpu/i386/cache_.h b/c/src/lib/libcpu/i386/cache_.h
index c660c720d3..2450e5e4be 100644
--- a/c/src/lib/libcpu/i386/cache_.h
+++ b/c/src/lib/libcpu/i386/cache_.h
@@ -6,8 +6,8 @@
 #define __i386_CACHE_h
 
 #define I386_CACHE_ALIGNMENT 16
-#define _CPU_DATA_CACHE_ALIGNMENT I386_CACHE_ALIGNMENT
-#define _CPU_INST_CACHE_ALIGNEMNT I386_CACHE_ALIGNMENT
+#define CPU_DATA_CACHE_ALIGNMENT I386_CACHE_ALIGNMENT
+#define CPU_INSTRUCTION_CACHE_ALIGNEMNT I386_CACHE_ALIGNMENT
 
 #include <libcpu/cache.h>
 
diff --git a/c/src/lib/libcpu/i386/page.c b/c/src/lib/libcpu/i386/page.c
index e5cceeed23..c44ab3a393 100644
--- a/c/src/lib/libcpu/i386/page.c
+++ b/c/src/lib/libcpu/i386/page.c
@@ -45,7 +45,7 @@ extern rtems_unsigned32 rtemsFreeMemStart;
 void _CPU_disable_paging() {
   cr0 regCr0;
 
-  rtems_flush_entire_data_cache();
+  rtems_cache_flush_entire_data();
   regCr0.i = i386_get_cr0();
   regCr0.cr0.paging = 0;
   i386_set_cr0( regCr0.i );
@@ -60,7 +60,7 @@ void _CPU_enable_paging() {
   regCr0.i = i386_get_cr0();
   regCr0.cr0.paging = 1;
   i386_set_cr0( regCr0.i );
-  rtems_flush_entire_data_cache();
+  rtems_cache_flush_entire_data();
 }