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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2009-05-27 11:57:33 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2009-05-27 11:57:33 +0000 |
| commit | 6ff3add12326dd7878946d726c4260e1ec9f3a3b (patch) | |
| tree | dd64bb88b82ba65d4d3691a4ab01d8e178e69de7 /c/src/lib/libcpu/bfin | |
| parent | 2009-05-25 Joel Sherrill <joel.sherrill@OARcorp.com> (diff) | |
| download | rtems-6ff3add12326dd7878946d726c4260e1ec9f3a3b.tar.bz2 | |
2009-05-25 Allan Hessenflow <allanh@kallisti.com>
PR 1418/bsps
* mmu/mmu.c: enable mmu after initializing it.
* mmu/mmu.h: add missing mmu flags entries.
* include/mmuRegs.h: correct a couple field name typos.
Diffstat (limited to 'c/src/lib/libcpu/bfin')
| -rw-r--r-- | c/src/lib/libcpu/bfin/ChangeLog | 6 | ||||
| -rw-r--r-- | c/src/lib/libcpu/bfin/include/mmuRegs.h | 4 | ||||
| -rw-r--r-- | c/src/lib/libcpu/bfin/mmu/mmu.c | 4 | ||||
| -rw-r--r-- | c/src/lib/libcpu/bfin/mmu/mmu.h | 10 |
4 files changed, 21 insertions, 3 deletions
diff --git a/c/src/lib/libcpu/bfin/ChangeLog b/c/src/lib/libcpu/bfin/ChangeLog index ab56a227c2..010ee44dc7 100644 --- a/c/src/lib/libcpu/bfin/ChangeLog +++ b/c/src/lib/libcpu/bfin/ChangeLog @@ -1,3 +1,9 @@ +2009-05-25 Allan Hessenflow <allanh@kallisti.com> + + * mmu/mmu.c: enable mmu after initializing it. + * mmu/mmu.h: add missing mmu flags entries. + * include/mmuRegs.h: correct a couple field name typos. + 2008-09-25 Allan Hessenflow <allanh@kallisti.com> * clock/clock.c, include/bf533.h, include/bf537.h, include/sicRegs.h: diff --git a/c/src/lib/libcpu/bfin/include/mmuRegs.h b/c/src/lib/libcpu/bfin/include/mmuRegs.h index bee11ce0e9..c15ddf9159 100644 --- a/c/src/lib/libcpu/bfin/include/mmuRegs.h +++ b/c/src/lib/libcpu/bfin/include/mmuRegs.h @@ -50,8 +50,8 @@ #define ICPLB_DATA_CPLB_L1_CHBL 0x00001000 #define ICPLB_DATA_CPLB_LRUPRIO 0x00000100 #define ICPLB_DATA_CPLB_USER_RD 0x00000004 -#define ICPLB_DATA_CPLB_CPLB_LOCK 0x00000002 -#define ICPLB_DATA_CPLB_CPLB_VALID 0x00000001 +#define ICPLB_DATA_CPLB_LOCK 0x00000002 +#define ICPLB_DATA_CPLB_VALID 0x00000001 #endif /* _mmuRegs_h_ */ diff --git a/c/src/lib/libcpu/bfin/mmu/mmu.c b/c/src/lib/libcpu/bfin/mmu/mmu.c index 6c3943b55e..b1a3c038f2 100644 --- a/c/src/lib/libcpu/bfin/mmu/mmu.c +++ b/c/src/lib/libcpu/bfin/mmu/mmu.c @@ -13,9 +13,9 @@ #include <rtems.h> +#include <libcpu/memoryRegs.h> #include "mmu.h" - /* NOTE: see notes in mmu.h */ void bfin_mmu_init(bfin_mmu_config_t *config) { @@ -32,6 +32,7 @@ void bfin_mmu_init(bfin_mmu_config_t *config) { *(uint32_t volatile *) data = config->instruction[i].flags; data += ICPLB_DATA_PITCH; } + *(uint32_t volatile *) IMEM_CONTROL |= IMEM_CONTROL_ENICPLB; addr = (intptr_t) DCPLB_ADDR0; data = (intptr_t) DCPLB_DATA0; for (i = 0; i < sizeof(config->data) / sizeof(config->data[0]); i++) { @@ -40,5 +41,6 @@ void bfin_mmu_init(bfin_mmu_config_t *config) { *(uint32_t volatile *) data = config->data[i].flags; data += DCPLB_DATA_PITCH; } + *(uint32_t volatile *) DMEM_CONTROL |= DMEM_CONTROL_ENDCPLB; } diff --git a/c/src/lib/libcpu/bfin/mmu/mmu.h b/c/src/lib/libcpu/bfin/mmu/mmu.h index 8a57750ba5..5ccf57aaa7 100644 --- a/c/src/lib/libcpu/bfin/mmu/mmu.h +++ b/c/src/lib/libcpu/bfin/mmu/mmu.h @@ -25,12 +25,22 @@ #include <libcpu/mmuRegs.h> +#define INSTR_NOCACHE (ICPLB_DATA_CPLB_USER_RD | \ + ICPLB_DATA_CPLB_VALID) + #define INSTR_CACHEABLE (ICPLB_DATA_CPLB_L1_CHBL | \ ICPLB_DATA_CPLB_USER_RD | \ ICPLB_DATA_CPLB_VALID) +#define DATA_NOCACHE (DCPLB_DATA_CPLB_DIRTY | \ + DCPLB_DATA_CPLB_SUPV_WR | \ + DCPLB_DATA_CPLB_USER_WR | \ + DCPLB_DATA_CPLB_USER_RD | \ + DCPLB_DATA_CPLB_VALID) + #define DATA_WRITEBACK (DCPLB_DATA_CPLB_L1_AOW | \ DCPLB_DATA_CPLB_L1_CHBL | \ + DCPLB_DATA_CPLB_DIRTY | \ DCPLB_DATA_CPLB_SUPV_WR | \ DCPLB_DATA_CPLB_USER_WR | \ DCPLB_DATA_CPLB_USER_RD | \ |