2008-08-15 Allan Hessenflow <allanh@kallisti.com>

	* ChangeLog, Makefile.am, README, configure.ac, preinstall.am,
	cache/cache.c, cache/cache_.h, clock/clock.c, clock/rtc.c,
	clock/tod.h, include/bf533.h, include/bf537.h, include/cecRegs.h,
	include/coreTimerRegs.h, include/dmaRegs.h, include/ebiuRegs.h,
	include/ethernetRegs.h, include/gpioRegs.h, include/memoryRegs.h,
	include/mmuRegs.h, include/ppiRegs.h, include/rtcRegs.h,
	include/sicRegs.h, include/spiRegs.h, include/sportRegs.h,
	include/timerRegs.h, include/twiRegs.h, include/uartRegs.h,
	include/wdogRegs.h, interrupt/interrupt.c, interrupt/interrupt.h,
	mmu/mmu.c, mmu/mmu.h, network/ethernet.c, network/ethernet.h,
	serial/spi.c, serial/spi.h, serial/sport.c, serial/sport.h,
	serial/twi.c, serial/twi.h, serial/uart.c, serial/uart.h,
	timer/timer.c: New files.

1 files changed, 65 insertions, 0 deletions

diff --git a/c/src/lib/libcpu/bfin/mmu/mmu.h b/c/src/lib/libcpu/bfin/mmu/mmu.h
new file mode 100644
index 0000000000..8a57750ba5
--- /dev/null
+++ b/c/src/lib/libcpu/bfin/mmu/mmu.h
@@ -0,0 +1,65 @@
+/*  Blackfin MMU Support
+ *
+ *  Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
+ *             written by Allan Hessenflow <allanh@kallisti.com>
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ */
+
+
+/* NOTE: this currently only implements a static table.  It should be made
+   to handle more regions than fit in the CPLBs, with an exception handler
+   to do replacements as needed.  This would of course require great care
+   to insure any storage required by the exception handler, including any
+   stack space, the exception handler itself, and the region descriptors
+   it needs to update the CPLBs, are in regions that will never be
+   replaced. */
+
+#ifndef _mmu_h_
+#define _mmu_h_
+
+#include <libcpu/mmuRegs.h>
+
+
+#define INSTR_CACHEABLE (ICPLB_DATA_CPLB_L1_CHBL | \
+                         ICPLB_DATA_CPLB_USER_RD | \
+                         ICPLB_DATA_CPLB_VALID)
+
+#define DATA_WRITEBACK (DCPLB_DATA_CPLB_L1_AOW | \
+                        DCPLB_DATA_CPLB_L1_CHBL | \
+                        DCPLB_DATA_CPLB_SUPV_WR | \
+                        DCPLB_DATA_CPLB_USER_WR | \
+                        DCPLB_DATA_CPLB_USER_RD | \
+                        DCPLB_DATA_CPLB_VALID)
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+typedef struct {
+  struct {
+    void *address;
+    uint32_t flags;
+  } instruction[ICPLB_COUNT];
+  struct {
+    void *address;
+    uint32_t flags;
+  } data[DCPLB_COUNT];
+} bfin_mmu_config_t;
+
+
+void bfin_mmu_init(bfin_mmu_config_t *config);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _mmu_h_ */
+