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author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2008-08-15 20:18:41 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2008-08-15 20:18:41 +0000 |
commit | 30abd24b7e7bc1f66b22527792931cf4468b06b8 (patch) | |
tree | fba359b7e4b04fdd1f008f54fcca7b69d810bab6 /c/src/lib/libcpu/bfin/include/uartRegs.h | |
parent | 2008-08-15 Joel Sherrill <joel.sherrill@OARcorp.com> (diff) | |
download | rtems-30abd24b7e7bc1f66b22527792931cf4468b06b8.tar.bz2 |
2008-08-15 Allan Hessenflow <allanh@kallisti.com>
* ChangeLog, Makefile.am, README, configure.ac, preinstall.am,
cache/cache.c, cache/cache_.h, clock/clock.c, clock/rtc.c,
clock/tod.h, include/bf533.h, include/bf537.h, include/cecRegs.h,
include/coreTimerRegs.h, include/dmaRegs.h, include/ebiuRegs.h,
include/ethernetRegs.h, include/gpioRegs.h, include/memoryRegs.h,
include/mmuRegs.h, include/ppiRegs.h, include/rtcRegs.h,
include/sicRegs.h, include/spiRegs.h, include/sportRegs.h,
include/timerRegs.h, include/twiRegs.h, include/uartRegs.h,
include/wdogRegs.h, interrupt/interrupt.c, interrupt/interrupt.h,
mmu/mmu.c, mmu/mmu.h, network/ethernet.c, network/ethernet.h,
serial/spi.c, serial/spi.h, serial/sport.c, serial/sport.h,
serial/twi.c, serial/twi.h, serial/uart.c, serial/uart.h,
timer/timer.c: New files.
Diffstat (limited to 'c/src/lib/libcpu/bfin/include/uartRegs.h')
-rw-r--r-- | c/src/lib/libcpu/bfin/include/uartRegs.h | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/bfin/include/uartRegs.h b/c/src/lib/libcpu/bfin/include/uartRegs.h new file mode 100644 index 0000000000..d921b17723 --- /dev/null +++ b/c/src/lib/libcpu/bfin/include/uartRegs.h @@ -0,0 +1,73 @@ +/* Blackfin UART Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow <allanh@kallisti.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _uartRegs_h_ +#define _uartRegs_h_ + +/* register addresses */ + +#define UART_RBR_OFFSET 0x0000 +#define UART_THR_OFFSET 0x0000 +#define UART_DLL_OFFSET 0x0000 +#define UART_IER_OFFSET 0x0004 +#define UART_DLH_OFFSET 0x0004 +#define UART_IIR_OFFSET 0x0008 +#define UART_LCR_OFFSET 0x000c +#define UART_MCR_OFFSET 0x0010 +#define UART_LSR_OFFSET 0x0014 +#define UART_SCR_OFFSET 0x001c +#define UART_GCTL_OFFSET 0x0024 + + +/* register fields */ + +#define UART_LCR_DLAB 0x80 +#define UART_LCR_SB 0x40 +#define UART_LCR_STP 0x20 +#define UART_LCR_EPS 0x10 +#define UART_LCR_PEN 0x08 +#define UART_LCR_STB 0x04 +#define UART_LCR_WLS_MASK 0x03 +#define UART_LCR_WLS_5 0x00 +#define UART_LCR_WLS_6 0x01 +#define UART_LCR_WLS_7 0x02 +#define UART_LCR_WLS_8 0x03 + +#define UART_MCR_LOOP 0x10 + +#define UART_LSR_TEMT 0x40 +#define UART_LSR_THRE 0x20 +#define UART_LSR_BI 0x10 +#define UART_LSR_FE 0x08 +#define UART_LSR_PE 0x04 +#define UART_LSR_OE 0x02 +#define UART_LSR_DR 0x01 + +#define UART_IER_ELSI 0x04 +#define UART_IER_ETBEI 0x02 +#define UART_IER_ERBFI 0x01 + +#define UART_IIR_STATUS_MASK 0x06 +#define UART_IIR_STATUS_THRE 0x02 +#define UART_IIR_STATUS_RDR 0x04 +#define UART_IIR_STATUS_LS 0x06 +#define UART_IIR_NINT 0x01 + +#define UART_GCTL_FFE 0x20 +#define UART_GCTL_FPE 0x10 +#define UART_GCTL_RPOLC 0x08 +#define UART_GCTL_TPOLC 0x04 +#define UART_GCTL_IREN 0x02 +#define UART_GCTL_UCEN 0x01 + +#endif /* _uartRegs_h_ */ + |