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authorJoel Sherrill <joel.sherrill@OARcorp.com>2008-08-15 20:18:41 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2008-08-15 20:18:41 +0000
commit30abd24b7e7bc1f66b22527792931cf4468b06b8 (patch)
treefba359b7e4b04fdd1f008f54fcca7b69d810bab6 /c/src/lib/libcpu/bfin/cache/cache_.h
parent2008-08-15 Joel Sherrill <joel.sherrill@OARcorp.com> (diff)
downloadrtems-30abd24b7e7bc1f66b22527792931cf4468b06b8.tar.bz2
2008-08-15 Allan Hessenflow <allanh@kallisti.com>
* ChangeLog, Makefile.am, README, configure.ac, preinstall.am, cache/cache.c, cache/cache_.h, clock/clock.c, clock/rtc.c, clock/tod.h, include/bf533.h, include/bf537.h, include/cecRegs.h, include/coreTimerRegs.h, include/dmaRegs.h, include/ebiuRegs.h, include/ethernetRegs.h, include/gpioRegs.h, include/memoryRegs.h, include/mmuRegs.h, include/ppiRegs.h, include/rtcRegs.h, include/sicRegs.h, include/spiRegs.h, include/sportRegs.h, include/timerRegs.h, include/twiRegs.h, include/uartRegs.h, include/wdogRegs.h, interrupt/interrupt.c, interrupt/interrupt.h, mmu/mmu.c, mmu/mmu.h, network/ethernet.c, network/ethernet.h, serial/spi.c, serial/spi.h, serial/sport.c, serial/sport.h, serial/twi.c, serial/twi.h, serial/uart.c, serial/uart.h, timer/timer.c: New files.
Diffstat (limited to 'c/src/lib/libcpu/bfin/cache/cache_.h')
-rw-r--r--c/src/lib/libcpu/bfin/cache/cache_.h21
1 files changed, 21 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/bfin/cache/cache_.h b/c/src/lib/libcpu/bfin/cache/cache_.h
new file mode 100644
index 0000000000..728ac0609e
--- /dev/null
+++ b/c/src/lib/libcpu/bfin/cache/cache_.h
@@ -0,0 +1,21 @@
+/*
+ * Blackfin Cache Manager Support
+ *
+ * $Id$
+ */
+
+#ifndef _cache__h_
+#define _cache__h_
+
+#define CPU_DATA_CACHE_ALIGNMENT 32
+#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
+
+#ifdef BSP_DATA_CACHE_CONFIG
+#define LIBCPU_DATA_CACHE_CONFIG BSP_DATA_CACHE_CONFIG
+#else
+/* use 16K of each SRAM bank */
+#define LIBCPU_DATA_CACHE_CONFIG (3 << DMEM_CONTROL_DMC_SHIFT)
+#endif
+
+#endif /* _cache__h_ */
+