Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step.  It
copied header files from arbitrary locations into the build tree.  The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

* The make preinstall step itself needs time and disk space.

* Errors in header files show up in the build tree copy.  This makes it
  hard for editors to open the right file to fix the error.

* There is no clear relationship between source and build tree header
  files.  This makes an audit of the build process difficult.

* The visibility of all header files in the build tree makes it
  difficult to enforce API barriers.  For example it is discouraged to
  use BSP-specifics in the cpukit.

* An introduction of a new build system is difficult.

* Include paths specified by the -B option are system headers.  This
  may suppress warnings.

* The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step.   All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc.  Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

* cpukit/include

* cpukit/score/cpu/@RTEMS_CPU@/include

* cpukit/libnetworking

The new BSP include directories are:

* bsps/include

* bsps/@RTEMS_CPU@/include

* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed.  The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

7 files changed, 2 insertions, 1198 deletions

diff --git a/c/src/lib/libcpu/arm/Makefile.am b/c/src/lib/libcpu/arm/Makefile.am
index 7f76673cfd..35b08e2495 100644
--- a/c/src/lib/libcpu/arm/Makefile.am
+++ b/c/src/lib/libcpu/arm/Makefile.am
@@ -6,17 +6,9 @@ EXTRA_DIST =
 
 noinst_PROGRAMS =
 
-include_bspdir = $(includedir)/bsp
-include_libcpudir = $(includedir)/libcpu
-
-include_bsp_HEADERS =
-include_libcpu_HEADERS =
-
 ## shared/include
 if shared
 
-include_libcpu_HEADERS += shared/include/mmu.h
-
 ## shared/arm920
 noinst_PROGRAMS += shared/arm920.rel
 shared_arm920_rel_SOURCES = shared/arm920/mmu.c
@@ -24,5 +16,4 @@ shared_arm920_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/src
 shared_arm920_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
 endif
 
-include $(srcdir)/preinstall.am
 include $(top_srcdir)/../../../automake/local.am
diff --git a/c/src/lib/libcpu/arm/configure.ac b/c/src/lib/libcpu/arm/configure.ac
index c72c34eb19..a5e3e1cc88 100644
--- a/c/src/lib/libcpu/arm/configure.ac
+++ b/c/src/lib/libcpu/arm/configure.ac
@@ -4,6 +4,8 @@ AC_PREREQ([2.69])
 AC_INIT([rtems-c-src-lib-libcpu-arm],[_RTEMS_VERSION],[https://devel.rtems.org/newticket])
 AC_CONFIG_SRCDIR([shared])
 RTEMS_TOP([../../../../..],[../../..])
+RTEMS_SOURCE_TOP
+RTEMS_BUILD_TOP
 
 RTEMS_CANONICAL_TARGET_CPU
 
diff --git a/c/src/lib/libcpu/arm/preinstall.am b/c/src/lib/libcpu/arm/preinstall.am
deleted file mode 100644
index 31e0da295b..0000000000
--- a/c/src/lib/libcpu/arm/preinstall.am
+++ /dev/null
@@ -1,30 +0,0 @@
-## Automatically generated by ampolish3 - Do not edit
-
-if AMPOLISH3
-$(srcdir)/preinstall.am: Makefile.am
-	$(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
-endif
-
-PREINSTALL_DIRS =
-DISTCLEANFILES = $(PREINSTALL_DIRS)
-
-all-am: $(PREINSTALL_FILES)
-
-PREINSTALL_FILES =
-CLEANFILES = $(PREINSTALL_FILES)
-
-$(PROJECT_INCLUDE)/bsp/$(dirstamp):
-	@$(MKDIR_P) $(PROJECT_INCLUDE)/bsp
-	@: > $(PROJECT_INCLUDE)/bsp/$(dirstamp)
-PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp)
-
-$(PROJECT_INCLUDE)/libcpu/$(dirstamp):
-	@$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu
-	@: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
-PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
-
-if shared
-$(PROJECT_INCLUDE)/libcpu/mmu.h: shared/include/mmu.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/mmu.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/mmu.h
-endif
diff --git a/c/src/lib/libcpu/arm/shared/include/am335x.h b/c/src/lib/libcpu/arm/shared/include/am335x.h
deleted file mode 100644
index 367e97cae9..0000000000
--- a/c/src/lib/libcpu/arm/shared/include/am335x.h
+++ /dev/null
@@ -1,704 +0,0 @@
-/*
- * Copyright (c) 2012 Claas Ziemke. All rights reserved.
- *
- *  Claas Ziemke
- *  Kernerstrasse 11
- *  70182 Stuttgart
- *  Germany
- *  <claas.ziemke@gmx.net>
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- *
- * Modified by Ben Gras <beng@shrike-systems.com> to add lots
- * of beagleboard/beaglebone definitions, delete lpc32xx specific
- * ones, and merge with some other header files.
- */
-
-#if !defined(_AM335X_H_)
-#define _AM335X_H_
-
-/* Interrupt controller memory map */
-#define OMAP3_DM37XX_INTR_BASE 0x48200000 /* INTCPS physical address */
-
-/* Interrupt controller memory map */
-#define OMAP3_AM335X_INTR_BASE 0x48200000 /* INTCPS physical address */
-
-#define AM335X_INT_EMUINT             0
-    /* Emulation interrupt (EMUICINTR) */
-#define AM335X_INT_COMMTX             1
-    /* CortexA8 COMMTX */
-#define AM335X_INT_COMMRX             2
-    /* CortexA8 COMMRX */
-#define AM335X_INT_BENCH              3
-    /* CortexA8 NPMUIRQ */
-#define AM335X_INT_ELM_IRQ            4
-    /* Sinterrupt (Error location process completion) */
-#define AM335X_INT_NMI                7
-    /* nmi_int */
-#define AM335X_INT_L3DEBUG            9
-    /* l3_FlagMux_top_FlagOut1 */
-#define AM335X_INT_L3APPINT           10
-    /* l3_FlagMux_top_FlagOut0  */
-#define AM335X_INT_PRCMINT            11
-    /* irq_mpu */
-#define AM335X_INT_EDMACOMPINT        12
-    /* tpcc_int_pend_po0 */
-#define AM335X_INT_EDMAMPERR          13
-    /* tpcc_mpint_pend_po */
-#define AM335X_INT_EDMAERRINT         14
-    /* tpcc_errint_pend_po */
-#define AM335X_INT_ADC_TSC_GENINT     16
-    /* gen_intr_pend */
-#define AM335X_INT_USBSSINT           17
-    /* usbss_intr_pend */
-#define AM335X_INT_USB0               18
-    /* usb0_intr_pend */
-#define AM335X_INT_USB1               19
-    /* usb1_intr_pend */
-#define AM335X_INT_PRUSS1_EVTOUT0     20
-    /* pr1_host_intr0_intr_pend */
-#define AM335X_INT_PRUSS1_EVTOUT1     21
-    /* pr1_host_intr1_intr_pend */
-#define AM335X_INT_PRUSS1_EVTOUT2     22
-    /* pr1_host_intr2_intr_pend */
-#define AM335X_INT_PRUSS1_EVTOUT3     23
-    /* pr1_host_intr3_intr_pend */
-#define AM335X_INT_PRUSS1_EVTOUT4     24
-    /* pr1_host_intr4_intr_pend */
-#define AM335X_INT_PRUSS1_EVTOUT5     25
-    /* pr1_host_intr5_intr_pend */
-#define AM335X_INT_PRUSS1_EVTOUT6     26
-    /* pr1_host_intr6_intr_pend */
-#define AM335X_INT_PRUSS1_EVTOUT7     27
-    /* pr1_host_intr7_intr_pend */
-#define AM335X_INT_MMCSD1INT          28
-    /* MMCSD1  SINTERRUPTN */
-#define AM335X_INT_MMCSD2INT          29
-    /* MMCSD2  SINTERRUPT */
-#define AM335X_INT_I2C2INT            30
-    /* I2C2  POINTRPEND */
-#define AM335X_INT_eCAP0INT           31
-    /* ecap_intr_intr_pend */
-#define AM335X_INT_GPIOINT2A          32
-    /* GPIO 2  POINTRPEND1 */
-#define AM335X_INT_GPIOINT2B          33
-    /* GPIO 2  POINTRPEND2 */
-#define AM335X_INT_USBWAKEUP          34
-    /* USBSS  slv0p_Swakeup */
-#define AM335X_INT_LCDCINT            36
-    /* LCDC  lcd_irq */
-#define AM335X_INT_GFXINT             37
-    /* SGX530  THALIAIRQ */
-#define AM335X_INT_ePWM2INT           39
-    /* (PWM Subsystem)  epwm_intr_intr_pend */
-#define AM335X_INT_3PGSWRXTHR0        40
-    /* (Ethernet)  c0_rx_thresh_pend (RX_THRESH_PULSE) */
-#define AM335X_INT_3PGSWRXINT0        41
-    /* CPSW (Ethernet)  c0_rx_pend */
-#define AM335X_INT_3PGSWTXINT0        42
-    /* CPSW (Ethernet)  c0_tx_pend */
-#define AM335X_INT_3PGSWMISC0         43
-    /* CPSW (Ethernet)  c0_misc_pend */
-#define AM335X_INT_UART3INT           44
-    /* UART3  niq */
-#define AM335X_INT_UART4INT           45
-    /* UART4  niq */
-#define AM335X_INT_UART5INT           46
-    /* UART5  niq */
-#define AM335X_INT_eCAP1INT           47
-    /* (PWM Subsystem)  ecap_intr_intr_pend */
-#define AM335X_INT_DCAN0_INT0         52
-    /* DCAN0  dcan_intr0_intr_pend */
-#define AM335X_INT_DCAN0_INT1         53
-    /* DCAN0  dcan_intr1_intr_pend */
-#define AM335X_INT_DCAN0_PARITY       54
-    /* DCAN0  dcan_uerr_intr_pend */
-#define AM335X_INT_DCAN1_INT0         55
-    /* DCAN1  dcan_intr0_intr_pend */
-#define AM335X_INT_DCAN1_INT1         56
-    /* DCAN1  dcan_intr1_intr_pend */
-#define AM335X_INT_DCAN1_PARITY       57
-    /* DCAN1  dcan_uerr_intr_pend */
-#define AM335X_INT_ePWM0_TZINT        58
-    /* eHRPWM0 TZ interrupt (PWM  epwm_tz_intr_pend Subsystem) */
-#define AM335X_INT_ePWM1_TZINT        59
-    /* eHRPWM1 TZ interrupt (PWM  epwm_tz_intr_pend Subsystem) */
-#define AM335X_INT_ePWM2_TZINT        60
-    /* eHRPWM2 TZ interrupt (PWM  epwm_tz_intr_pend Subsystem) */
-#define AM335X_INT_eCAP2INT           61
-    /* eCAP2 (PWM Subsystem)  ecap_intr_intr_pend */
-#define AM335X_INT_GPIOINT3A          62
-    /* GPIO 3  POINTRPEND1 */
-#define AM335X_INT_GPIOINT3B          63
-    /* GPIO 3  POINTRPEND2 */
-#define AM335X_INT_MMCSD0INT          64
-    /* MMCSD0  SINTERRUPTN */
-#define AM335X_INT_SPI0INT            65
-    /* McSPI0  SINTERRUPTN */
-#define AM335X_INT_TINT0              66
-    /* Timer0  POINTR_PEND */
-#define AM335X_INT_TINT1_1MS          67
-    /* DMTIMER_1ms  POINTR_PEND */
-#define AM335X_INT_TINT2              68
-    /* DMTIMER2  POINTR_PEND */
-#define AM335X_INT_TINT3              69
-    /* DMTIMER3  POINTR_PEND */
-#define AM335X_INT_I2C0INT            70
-    /* I2C0  POINTRPEND */
-#define AM335X_INT_I2C1INT            71
-    /* I2C1  POINTRPEND */
-#define AM335X_INT_UART0INT           72
-    /* UART0  niq */
-#define AM335X_INT_UART1INT           73
-    /* UART1  niq */
-#define AM335X_INT_UART2INT           74
-    /* UART2  niq */
-#define AM335X_INT_RTCINT             75
-    /* RTC  timer_intr_pend */
-#define AM335X_INT_RTCALARMINT        76
-    /* RTC  alarm_intr_pend */
-#define AM335X_INT_MBINT0             77
-    /* Mailbox0 (mail_u0_irq)  initiator_sinterrupt_q_n */
-#define AM335X_INT_M3_TXEV            78
-    /* Wake M3 Subsystem  TXEV */
-#define AM335X_INT_eQEP0INT           79
-    /* eQEP0 (PWM Subsystem)  eqep_intr_intr_pend */
-#define AM335X_INT_MCATXINT0          80
-    /* McASP0  mcasp_x_intr_pend */
-#define AM335X_INT_MCARXINT0          81
-    /* McASP0  mcasp_r_intr_pend */
-#define AM335X_INT_MCATXINT1          82
-    /* McASP1  mcasp_x_intr_pend */
-#define AM335X_INT_MCARXINT1          83
-    /* McASP1  mcasp_r_intr_pend */
-#define AM335X_INT_ePWM0INT           86
-    /* (PWM Subsystem)  epwm_intr_intr_pend */
-#define AM335X_INT_ePWM1INT           87
-    /* (PWM Subsystem)  epwm_intr_intr_pend */
-#define AM335X_INT_eQEP1INT           88
-    /* (PWM Subsystem)  eqep_intr_intr_pend */
-#define AM335X_INT_eQEP2INT           89
-    /* (PWM Subsystem)  eqep_intr_intr_pend */
-#define AM335X_INT_DMA_INTR_PIN2      90
-    /* External DMA/Interrupt Pin2  */
-#define AM335X_INT_WDT1INT            91
-    /* (Public Watchdog) WDTIMER1 PO_INT_PEND */
-#define AM335X_INT_TINT4              92
-    /* DMTIMER4  POINTR_PEN */
-#define AM335X_INT_TINT5              93
-    /* DMTIMER5  POINTR_PEN */
-#define AM335X_INT_TINT6              94
-    /* DMTIMER6  POINTR_PEND */
-#define AM335X_INT_TINT7              95
-    /* DMTIMER7  POINTR_PEND */
-#define AM335X_INT_GPIOINT0A          96
-    /* GPIO 0  POINTRPEND1 */
-#define AM335X_INT_GPIOINT0B          97
-    /* GPIO 0  POINTRPEND2 */
-#define AM335X_INT_GPIOINT1A          98
-    /* GPIO 1  POINTRPEND1 */
-#define AM335X_INT_GPIOINT1B          99
-    /* GPIO 1  POINTRPEND2 */
-#define AM335X_INT_GPMCINT            100
-    /* GPMC  gpmc_sinterrupt */
-#define AM335X_INT_DDRERR0            101
-    /* EMIF  sys_err_intr_pend */
-#define AM335X_INT_TCERRINT0          112
-    /* TPTC0  tptc_erint_pend_po */
-#define AM335X_INT_TCERRINT1          113
-    /* TPTC1  tptc_erint_pend_po */
-#define AM335X_INT_TCERRINT2          114
-    /* TPTC2  tptc_erint_pend_po */
-#define AM335X_INT_ADC_TSC_PENINT     115
-    /* ADC_TSC  pen_intr_pend */
-#define AM335X_INT_SMRFLX_Sabertooth  120
-    /* Smart Reflex 0  intrpen */
-#define AM335X_INT_SMRFLX_Core        121
-    /* Smart Reflex 1  intrpend */
-#define AM335X_INT_DMA_INTR_PIN0      123
-    /* pi_x_dma_event_intr0 (xdma_event_intr0) */
-#define AM335X_INT_DMA_INTR_PIN1      124
-    /* pi_x_dma_event_intr1 (xdma_event_intr1) */
-#define AM335X_INT_SPI1INT            125
-    /* McSPI1  SINTERRUPTN */
-
-#define OMAP3_AM335X_NR_IRQ_VECTORS    125
-
-#define AM335X_DMTIMER0_BASE      0x44E05000
-    /* DMTimer0 Registers */
-#define AM335X_DMTIMER1_1MS_BASE  0x44E31000
-    /* DMTimer1 1ms Registers (Accurate 1ms timer) */
-#define AM335X_DMTIMER2_BASE      0x48040000
-    /*  DMTimer2 Registers */
-#define AM335X_DMTIMER3_BASE      0x48042000
-    /*  DMTimer3 Registers */
-#define AM335X_DMTIMER4_BASE      0x48044000
-    /* DMTimer4 Registers  */
-#define AM335X_DMTIMER5_BASE      0x48046000
-    /* DMTimer5 Registers  */
-#define AM335X_DMTIMER6_BASE      0x48048000
-    /*  DMTimer6 Registers */
-#define AM335X_DMTIMER7_BASE      0x4804A000
-    /*  DMTimer7 Registers */
-
-/* General-purpose timer registers
-   AM335x non 1MS timers have different offsets */
-#define AM335X_TIMER_TIDR             0x000
-    /* IP revision code */
-#define AM335X_TIMER_TIOCP_CFG        0x010
-    /* Controls params for GP timer L4 interface */
-#define AM335X_TIMER_IRQSTATUS_RAW    0x024
-    /* Timer IRQSTATUS Raw Register */
-#define AM335X_TIMER_IRQSTATUS        0x028
-    /* Timer IRQSTATUS Register */
-#define AM335X_TIMER_IRQENABLE_SET    0x02C
-    /* Timer IRQENABLE Set Register */
-#define AM335X_TIMER_IRQENABLE_CLR    0x030
-    /* Timer IRQENABLE Clear Register */
-#define AM335X_TIMER_IRQWAKEEN        0x034
-    /* Timer IRQ Wakeup Enable Register */
-#define AM335X_TIMER_TCLR             0x038
-    /* Controls optional features */
-#define AM335X_TIMER_TCRR             0x03C
-    /* Internal counter value */
-#define AM335X_TIMER_TLDR             0x040
-    /* Timer load value */
-#define AM335X_TIMER_TTGR             0x044
-    /* Triggers counter reload */
-#define AM335X_TIMER_TWPS             0x048
-    /* Indicates if Write-Posted pending */
-#define AM335X_TIMER_TMAR             0x04C
-    /* Value to be compared with counter */
-#define AM335X_TIMER_TCAR1            0x050
-    /* First captured value of counter register */
-#define AM335X_TIMER_TSICR            0x054
-    /* Control posted mode and functional SW reset */
-#define AM335X_TIMER_TCAR2            0x058
-    /* Second captured value of counter register */
-#define AM335X_WDT_BASE                0x44E35000
-    /* Watchdog timer */
-#define AM335X_WDT_WWPS                0x34
-    /* Command posted status */
-#define AM335X_WDT_WSPR                0x48
-    /* Activate/deactivate sequence */
-
-/* RTC registers */
-#define AM335X_RTC_BASE         0x44E3E000
-#define AM335X_RTC_SECS         0x0
-#define AM335X_RTC_MINS         0x4
-#define AM335X_RTC_HOURS        0x8
-#define AM335X_RTC_DAYS         0xc
-#define AM335X_RTC_MONTHS       0x10
-#define AM335X_RTC_YEARS        0x14
-#define AM335X_RTC_WEEKS        0x18
-#define AM335X_RTC_CTRL_REG     0x40
-#define AM335X_RTC_STATUS_REG   0x44
-#define AM335X_RTC_REV_REG      0x74
-#define AM335X_RTC_SYSCONFIG    0x78
-#define AM335X_RTC_KICK0        0x6c
-#define AM335X_RTC_KICK1        0x70
-#define AM335X_RTC_OSC_CLOCK    0x54
-
-#define AM335X_RTC_KICK0_KEY    0x83E70B13
-#define AM335X_RTC_KICK1_KEY    0x95A4F1E0
-
-/* GPIO memory-mapped registers */
-
-#define AM335X_GPIO0_BASE           0x44E07000
-    /* GPIO Bank 0 base Register */
-#define AM335X_GPIO1_BASE           0x4804C000
-    /* GPIO Bank 1 base Register */
-#define AM335X_GPIO2_BASE           0x481AC000
-    /* GPIO Bank 2 base Register */
-#define AM335X_GPIO3_BASE           0x481AE000
-    /* GPIO Bank 3 base Register */
-
-#define AM335X_GPIO_REVISION        0x00
-#define AM335X_GPIO_SYSCONFIG       0x10
-#define AM335X_GPIO_EOI             0x20
-#define AM335X_GPIO_IRQSTATUS_RAW_0 0x24
-#define AM335X_GPIO_IRQSTATUS_RAW_1 0x28
-#define AM335X_GPIO_IRQSTATUS_0     0x2C
-#define AM335X_GPIO_IRQSTATUS_1     0x30
-#define AM335X_GPIO_IRQSTATUS_SET_0 0x34
-#define AM335X_GPIO_IRQSTATUS_SET_1 0x38
-#define AM335X_GPIO_IRQSTATUS_CLR_0 0x3C
-#define AM335X_GPIO_IRQSTATUS_CLR_1 0x40
-#define AM335X_GPIO_IRQWAKEN_0      0x44
-#define AM335X_GPIO_IRQWAKEN_1      0x48
-#define AM335X_GPIO_SYSSTATUS       0x114
-#define AM335X_GPIO_CTRL            0x130
-#define AM335X_GPIO_OE              0x134
-#define AM335X_GPIO_DATAIN          0x138
-#define AM335X_GPIO_DATAOUT         0x13C
-#define AM335X_GPIO_LEVELDETECT0    0x140
-#define AM335X_GPIO_LEVELDETECT1    0x144
-#define AM335X_GPIO_RISINGDETECT    0x148
-#define AM335X_GPIO_FALLINGDETECT   0x14C
-#define AM335X_GPIO_DEBOUNCENABLE   0x150
-#define AM335X_GPIO_DEBOUNCINGTIME  0x154
-#define AM335X_GPIO_CLEARDATAOUT    0x190
-#define AM335X_GPIO_SETDATAOUT      0x194
-
-/* AM335X Pad Configuration Register Base */
-#define AM335X_PADCONF_BASE 0x44E10000
-
-/* Memory mapped register offset for Control Module */
-#define AM335X_CONF_GPMC_AD0 0x800
-#define AM335X_CONF_GPMC_AD1 0x804
-#define AM335X_CONF_GPMC_AD2 0x808
-#define AM335X_CONF_GPMC_AD3 0x80C
-#define AM335X_CONF_GPMC_AD4 0x810
-#define AM335X_CONF_GPMC_AD5 0x814
-#define AM335X_CONF_GPMC_AD6 0x818
-#define AM335X_CONF_GPMC_AD7 0x81C
-#define AM335X_CONF_GPMC_AD8 0x820
-#define AM335X_CONF_GPMC_AD9 0x824
-#define AM335X_CONF_GPMC_AD10 0x828
-#define AM335X_CONF_GPMC_AD11 0x82C
-#define AM335X_CONF_GPMC_AD12 0x830
-#define AM335X_CONF_GPMC_AD13 0x834
-#define AM335X_CONF_GPMC_AD14 0x838
-#define AM335X_CONF_GPMC_AD15 0x83C
-#define AM335X_CONF_GPMC_A0 0x840
-#define AM335X_CONF_GPMC_A1 0x844
-#define AM335X_CONF_GPMC_A2 0x848
-#define AM335X_CONF_GPMC_A3 0x84C
-#define AM335X_CONF_GPMC_A4 0x850
-#define AM335X_CONF_GPMC_A5 0x854
-#define AM335X_CONF_GPMC_A6 0x858
-#define AM335X_CONF_GPMC_A7 0x85C
-#define AM335X_CONF_GPMC_A8 0x860
-#define AM335X_CONF_GPMC_A9 0x864
-#define AM335X_CONF_GPMC_A10 0x868
-#define AM335X_CONF_GPMC_A11 0x86C
-#define AM335X_CONF_GPMC_WAIT0 0x870
-#define AM335X_CONF_GPMC_WPN 0x874
-#define AM335X_CONF_GPMC_BEN1 0x878
-#define AM335X_CONF_GPMC_CSN0 0x87C
-#define AM335X_CONF_GPMC_CSN1 0x880
-#define AM335X_CONF_GPMC_CSN2 0x884
-#define AM335X_CONF_GPMC_CSN3 0x888
-#define AM335X_CONF_GPMC_CLK 0x88C
-#define AM335X_CONF_GPMC_ADVN_ALE 0x890
-#define AM335X_CONF_GPMC_OEN_REN 0x894
-#define AM335X_CONF_GPMC_WEN 0x898
-#define AM335X_CONF_GPMC_BEN0_CLE 0x89C
-#define AM335X_CONF_LCD_DATA0 0x8A0
-#define AM335X_CONF_LCD_DATA1 0x8A4
-#define AM335X_CONF_LCD_DATA2 0x8A8
-#define AM335X_CONF_LCD_DATA3 0x8AC
-#define AM335X_CONF_LCD_DATA4 0x8B0
-#define AM335X_CONF_LCD_DATA5 0x8B4
-#define AM335X_CONF_LCD_DATA6 0x8B8
-#define AM335X_CONF_LCD_DATA7 0x8BC
-#define AM335X_CONF_LCD_DATA8 0x8C0
-#define AM335X_CONF_LCD_DATA9 0x8C4
-#define AM335X_CONF_LCD_DATA10 0x8C8
-#define AM335X_CONF_LCD_DATA11 0x8CC
-#define AM335X_CONF_LCD_DATA12 0x8D0
-#define AM335X_CONF_LCD_DATA13 0x8D4
-#define AM335X_CONF_LCD_DATA14 0x8D8
-#define AM335X_CONF_LCD_DATA15 0x8DC
-#define AM335X_CONF_LCD_VSYNC 0x8E0
-#define AM335X_CONF_LCD_HSYNC 0x8E4
-#define AM335X_CONF_LCD_PCLK 0x8E8
-#define AM335X_CONF_LCD_AC_BIAS_EN 0x8EC
-#define AM335X_CONF_MMC0_DAT3 0x8F0
-#define AM335X_CONF_MMC0_DAT2 0x8F4
-#define AM335X_CONF_MMC0_DAT1 0x8F8
-#define AM335X_CONF_MMC0_DAT0 0x8FC
-#define AM335X_CONF_MMC0_CLK 0x900
-#define AM335X_CONF_MMC0_CMD 0x904
-#define AM335X_CONF_MII1_COL 0x908
-#define AM335X_CONF_MII1_CRS 0x90C
-#define AM335X_CONF_MII1_RX_ER 0x910
-#define AM335X_CONF_MII1_TX_EN 0x914
-#define AM335X_CONF_MII1_RX_DV 0x918
-#define AM335X_CONF_MII1_TXD3 0x91C
-#define AM335X_CONF_MII1_TXD2 0x920
-#define AM335X_CONF_MII1_TXD1 0x924
-#define AM335X_CONF_MII1_TXD0 0x928
-#define AM335X_CONF_MII1_TX_CLK 0x92C
-#define AM335X_CONF_MII1_RX_CLK 0x930
-#define AM335X_CONF_MII1_RXD3 0x934
-#define AM335X_CONF_MII1_RXD2 0x938
-#define AM335X_CONF_MII1_RXD1 0x93C
-#define AM335X_CONF_MII1_RXD0 0x940
-#define AM335X_CONF_RMII1_REF_CLK 0x944
-#define AM335X_CONF_MDIO 0x948
-#define AM335X_CONF_MDC 0x94C
-#define AM335X_CONF_SPI0_SCLK 0x950
-#define AM335X_CONF_SPI0_D0 0x954
-#define AM335X_CONF_SPI0_D1 0x958
-#define AM335X_CONF_SPI0_CS0 0x95C
-#define AM335X_CONF_SPI0_CS1 0x960
-#define AM335X_CONF_ECAP0_IN_PWM0_OUT 0x964
-#define AM335X_CONF_UART0_CTSN 0x968
-#define AM335X_CONF_UART0_RTSN 0x96C
-#define AM335X_CONF_UART0_RXD 0x970
-#define AM335X_CONF_UART0_TXD 0x974
-#define AM335X_CONF_UART1_CTSN 0x978
-#define AM335X_CONF_UART1_RTSN 0x97C
-#define AM335X_CONF_UART1_RXD 0x980
-#define AM335X_CONF_UART1_TXD 0x984
-#define AM335X_CONF_I2C0_SDA 0x988
-#define AM335X_CONF_I2C0_SCL 0x98C
-#define AM335X_CONF_MCASP0_ACLKX 0x990
-#define AM335X_CONF_MCASP0_FSX 0x994
-#define AM335X_CONF_MCASP0_AXR0 0x998
-#define AM335X_CONF_MCASP0_AHCLKR 0x99C
-#define AM335X_CONF_MCASP0_ACLKR 0x9A0
-#define AM335X_CONF_MCASP0_FSR 0x9A4
-#define AM335X_CONF_MCASP0_AXR1 0x9A8
-#define AM335X_CONF_MCASP0_AHCLKX 0x9AC
-#define AM335X_CONF_XDMA_EVENT_INTR0 0x9B0
-#define AM335X_CONF_XDMA_EVENT_INTR1 0x9B4
-#define AM335X_CONF_WARMRSTN 0x9B8
-#define AM335X_CONF_NNMI 0x9C0
-#define AM335X_CONF_TMS 0x9D0
-#define AM335X_CONF_TDI 0x9D4
-#define AM335X_CONF_TDO 0x9D8
-#define AM335X_CONF_TCK 0x9DC
-#define AM335X_CONF_TRSTN 0x9E0
-#define AM335X_CONF_EMU0 0x9E4
-#define AM335X_CONF_EMU1 0x9E8
-#define AM335X_CONF_RTC_PWRONRSTN 0x9F8
-#define AM335X_CONF_PMIC_POWER_EN 0x9FC
-#define AM335X_CONF_EXT_WAKEUP 0xA00
-#define AM335X_CONF_RTC_KALDO_ENN 0xA04
-#define AM335X_CONF_USB0_DRVVBUS 0xA1C
-#define AM335X_CONF_USB1_DRVVBUS 0xA34
-
-/* Registers for PWM Subsystem */
-#define AM335X_PWMSS_CTRL      (0x664)
-#define AM335X_CM_PER_EPWMSS0_CLKCTRL    (0xD4)
-#define AM335X_CM_PER_EPWMSS1_CLKCTRL    (0xCC)
-#define AM335X_CM_PER_EPWMSS2_CLKCTRL    (0xD8)
-#define AM335X_CONTROL_MODULE      (0x44e10000)
-#define AM335X_CM_PER_ADDR     (0x44e00000)
-#define AM335X_PWMSS_CLKSTATUS         (0xC)
-#define AM335X_PWMSS0_MMAP_ADDR        0x48300000
-#define AM335X_PWMSS1_MMAP_ADDR        0x48302000
-#define AM335X_PWMSS2_MMAP_ADDR        0x48304000
-#define AM335X_PWMSS_MMAP_LEN          0x1000
-#define AM335X_PWMSS_IDVER         0x0
-#define AM335X_PWMSS_SYSCONFIG     0x4
-#define AM335X_PWMSS_CLKCONFIG     0x8
-#define AM335X_PWMSS_CLK_EN_ACK        0x100
-#define AM335X_EPWM_TBCTL          0x0
-#define AM335X_EPWM_TBSTS          0x2
-#define AM335X_EPWM_TBPHSHR        0x4
-#define AM335X_EPWM_TBPHS          0x6
-#define AM335X_EPWM_TBCNT          0x8
-#define AM335X_EPWM_TBPRD          0xA
-#define AM335X_EPWM_CMPCTL         0xE
-#define AM335X_EPWM_CMPAHR         0x10
-#define AM335X_EPWM_CMPA           0x12
-#define AM335X_EPWM_CMPB           0x14
-#define AM335X_EPWM_AQCTLA         0x16
-#define AM335X_EPWM_AQCTLB         0x18
-#define AM335X_EPWM_AQSFRC         0x1A
-#define AM335X_EPWM_AQCSFRC        0x1C
-#define AM335X_EPWM_DBCTL          0x1E
-#define AM335X_EPWM_DBRED          0x20
-#define AM335X_EPWM_DBFED          0x22
-#define AM335X_TBCTL_CTRMODE_UP        0x0
-#define AM335X_TBCTL_CTRMODE_DOWN      0x1
-#define AM335X_TBCTL_CTRMODE_UPDOWN    0x2
-#define AM335X_TBCTL_CTRMODE_FREEZE    0x3
-#define AM335X_EPWM_AQCTLA_ZRO_XALOW         (0x0001u)
-#define AM335X_EPWM_AQCTLA_ZRO_XAHIGH        (0x0002u)
-#define AM335X_EPWM_AQCTLA_CAU_EPWMXATOGGLE   (0x0003u)
-#define AM335X_EPWM_AQCTLA_CAU_SHIFT          (0x0004u)
-#define AM335X_EPWM_AQCTLA_ZRO_XBLOW         (0x0001u)
-#define AM335X_EPWM_AQCTLB_ZRO_XBHIGH        (0x0002u)
-#define AM335X_EPWM_AQCTLB_CBU_EPWMXBTOGGLE   (0x0003u)
-#define AM335X_EPWM_AQCTLB_CBU_SHIFT          (0x0008u)
-#define AM335X_EPWM_TBCTL_CTRMODE_STOPFREEZE  (0x0003u)
-#define AM335X_PWMSS_CTRL_PWMSS0_TBCLKEN      (0x00000001u)
-#define AM335X_PWMSS_CTRL_PWMSS1_TBCLKEN      (0x00000002u)
-#define AM335X_PWMSS_CTRL_PWMSS2_TBCLKEN      (0x00000004u)
-#define AM335X_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
-#define AM335X_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
-#define AM335X_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
-#define AM335X_TBCTL_CLKDIV_MASK              (3 << 10)
-#define AM335X_TBCTL_HSPCLKDIV_MASK           (3 << 7)
-#define AM335X_EPWM_TBCTL_CLKDIV              (0x1C00u)
-#define AM335X_EPWM_TBCTL_CLKDIV_SHIFT        (0x000Au)
-#define AM335X_EPWM_TBCTL_HSPCLKDIV           (0x0380u)
-#define AM335X_EPWM_TBCTL_HSPCLKDIV_SHIFT     (0x0007u)
-#define AM335X_EPWM_TBCTL_PRDLD               (0x0008u)
-#define AM335X_EPWM_PRD_LOAD_SHADOW_MASK      AM335X_EPWM_TBCTL_PRDLD
-#define AM335X_EPWM_SHADOW_WRITE_ENABLE       0x0
-#define AM335X_EPWM_SHADOW_WRITE_DISABLE      0x1
-#define AM335X_EPWM_TBCTL_PRDLD_SHIFT         (0x0003u)
-#define AM335X_EPWM_TBCTL_CTRMODE             (0x0003u)
-#define AM335X_EPWM_COUNTER_MODE_MASK         AM335X_EPWM_TBCTL_CTRMODE
-#define AM335X_TBCTL_FREERUN                  (2 << 14)
-#define AM335X_TBCTL_CTRMODE_SHIFT            (0x0000u)
-#define AM335X_EPWM_COUNT_UP                  (AM335X_TBCTL_CTRMODE_UP << \
-                                                     AM335X_TBCTL_CTRMODE_SHIFT)
-
-#define AM335X_EPWM_REGS                       (0x00000200)
-#define AM335X_EPWM_0_REGS                     (AM335X_PWMSS0_MMAP_ADDR + AM335X_EPWM_REGS)
-#define AM335X_EPWM_1_REGS                     (AM335X_PWMSS1_MMAP_ADDR + AM335X_EPWM_REGS)
-#define AM335X_EPWM_2_REGS                     (AM335X_PWMSS2_MMAP_ADDR + AM335X_EPWM_REGS)
-
-#define AM335X_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE   (0x00000003u)
-#define AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST_FUNC  (0x0u)
-#define AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST_SHIFT (0x00000010u)
-#define AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST       (0x00030000u)
-
-#define AM335X_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE   (0x00000003u)
-#define AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST       (0x00030000u)
-#define AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST_FUNC  (0x0u)
-#define AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST_SHIFT (0x00000010u)
-
-#define AM335X_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE   (0x00000003u)
-#define AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST_FUNC  (0x0u)
-#define AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST_SHIFT (0x00000010u)
-#define AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST       (0x00030000u)
-
-
-
-/* I2C registers */
-#define AM335X_I2C0_BASE 0x44e0b000
-    /* I2C0 base address */
-#define AM335X_I2C1_BASE 0x4802a000
-    /* I2C1 base address */
-#define AM335X_I2C2_BASE 0x4819c000
-    /* I2C2 base address */
-#define AM335X_I2C_REVNB_LO        0x00
-    /* Module Revision Register (low bytes) */
-#define AM335X_I2C_REVNB_HI        0x04
-    /* Module Revision Register (high bytes) */
-#define AM335X_I2C_SYSC            0x10
-    /* System Configuration Register */
-#define AM335X_I2C_IRQSTATUS_RAW   0x24
-    /* I2C Status Raw Register */
-#define AM335X_I2C_IRQSTATUS       0x28
-    /* I2C Status Register */
-#define AM335X_I2C_IRQENABLE_SET   0x2c
-    /* I2C Interrupt Enable Set Register */
-#define AM335X_I2C_IRQENABLE_CLR   0x30
-    /* I2C Interrupt Enable Clear Register */
-#define AM335X_I2C_WE              0x34
-    /* I2C Wakeup Enable Register */
-#define AM335X_I2C_DMARXENABLE_SET 0x38
-    /* Receive DMA Enable Set Register */
-#define AM335X_I2C_DMATXENABLE_SET 0x3c
-    /* Transmit DMA Enable Set Register */
-#define AM335X_I2C_DMARXENABLE_CLR 0x40
-    /* Receive DMA Enable Clear Register */
-#define AM335X_I2C_DMATXENABLE_CLR 0x44
-    /* Transmit DMA Enable Clear Register */
-#define AM335X_I2C_DMARXWAKE_EN    0x48
-    /* Receive DMA Wakeup Register */
-#define AM335X_I2C_DMATXWAKE_EN    0x4c
-    /* Transmit DMA Wakeup Register */
-#define AM335X_I2C_SYSS            0x90
-    /* System Status Register */
-#define AM335X_I2C_BUF             0x94
-    /* Buffer Configuration Register */
-#define AM335X_I2C_CNT             0x98
-    /* Data Counter Register */
-#define AM335X_I2C_DATA            0x9c
-    /* Data Access Register */
-#define AM335X_I2C_CON             0xa4
-    /* I2C Configuration Register */
-#define AM335X_I2C_OA              0xa8
-    /* I2C Own Address Register */
-#define AM335X_I2C_SA              0xac
-    /* I2C Slave Address Register */
-#define AM335X_I2C_PSC             0xb0
-    /* I2C Clock Prescaler Register */
-#define AM335X_I2C_SCLL            0xb4
-    /* I2C SCL Low Time Register */
-#define AM335X_I2C_SCLH            0xb8
-    /* I2C SCL High Time Register */
-#define AM335X_I2C_SYSTEST         0xbc
-    /* System Test Register */
-#define AM335X_I2C_BUFSTAT         0xc0
-    /* I2C Buffer Status Register */
-#define AM335X_I2C_OA1             0xc4
-    /* I2C Own Address 1 Register */
-#define AM335X_I2C_OA2             0xc8
-    /* I2C Own Address 2 Register */
-#define AM335X_I2C_OA3             0xcc
-    /* I2C Own Address 3 Register */
-#define AM335X_I2C_ACTOA           0xd0
-    /* Active Own Address Register */
-#define AM335X_I2C_SBLOCK          0xd4
-    /* I2C Clock Blocking Enable Register */
-
-#define AM335X_CM_PER_L4LS_CLKSTCTRL  (0x0)
-#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP  (0x2u)
-#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL  (0x00000003u)
-#define AM335X_CM_PER_L4LS_CLKCTRL  (0x60)
-#define AM335X_CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE  (0x2u)
-#define AM335X_CM_PER_L4LS_CLKCTRL_MODULEMODE  (0x00000003u)
-#define AM335X_CM_PER_I2C1_CLKCTRL  (0x48)
-#define AM335X_CM_PER_I2C1_CLKCTRL_MODULEMODE_ENABLE  (0x2u)
-#define AM335X_CM_PER_I2C1_CLKCTRL_MODULEMODE  (0x00000003u)
-#define AM335X_CM_PER_I2C2_CLKCTRL (0x44)
-#define AM335X_CM_PER_I2C2_CLKCTRL_MODULEMODE_ENABLE  (0x2u)
-#define AM335X_CM_PER_I2C2_CLKCTRL_MODULEMODE  (0x00000003u)
-#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK (0x00000100u)
-#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_I2C_FCLK (0x01000000u)
-#define AM335X_CM_PER_I2C1_CLKCTRL_MODULEMODE   (0x00000003u)
-#define AM335X_I2C_CON_XSA  (0x00000100u)
-#define AM335X_I2C_CFG_10BIT_SLAVE_ADDR  AM335X_I2C_CON_XSA
-#define AM335X_I2C_CON_XSA_SHIFT  (0x00000008u)
-#define AM335X_I2C_CFG_7BIT_SLAVE_ADDR  (0 << AM335X_I2C_CON_XSA_SHIFT)
-#define AM335X_I2C_CON_I2C_EN   (0x00008000u)
-#define AM335X_I2C_CON_TRX   (0x00000200u)
-#define AM335X_I2C_CON_MST   (0x00000400u)
-#define AM335X_I2C_CON_STB   (0x00000800u)
-#define AM335X_I2C_SYSC_AUTOIDLE   (0x00000001u)
-
-/*I2C0 module clock registers*/
-
-#define AM335X_CM_WKUP_CONTROL_CLKCTRL   (0x4)
-#define AM335X_CM_WKUP_CLKSTCTRL   (0x0)
-#define AM335X_CM_WKUP_I2C0_CLKCTRL   (0xb8)
-#define AM335X_CM_WKUP_I2C0_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
-#define AM335X_CM_WKUP_I2C0_CLKCTRL_MODULEMODE   (0x00000003u)
-#define AM335X_CM_WKUP_CONTROL_CLKCTRL_IDLEST_FUNC   (0x0u)
-#define AM335X_CM_WKUP_CONTROL_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
-#define AM335X_CM_WKUP_CONTROL_CLKCTRL_IDLEST   (0x00030000u)
-#define AM335X_CM_WKUP_CLKSTCTRL_CLKACTIVITY_I2C0_GFCLK   (0x00000800u)
-#define AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST_FUNC   (0x0u)
-#define AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
-#define AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST   (0x00030000u)
-#define AM335X_SOC_CM_WKUP_REGS                     (AM335X_CM_PER_ADDR + 0x400)
-
-/* I2C status Register */
-#define AM335X_I2C_IRQSTATUS_NACK (1 << 1)
-#define AM335X_I2C_IRQSTATUS_ROVR (1 << 11)
-#define AM335X_I2C_IRQSTATUS_AL   (1<<0)
-#define AM335X_I2C_IRQSTATUS_ARDY (1 << 2)
-#define AM335X_I2C_IRQSTATUS_RRDY (1 << 3)
-#define AM335X_I2C_IRQSTATUS_XRDY (1 << 4)
-#define AM335X_I2C_IRQSTATUS_XUDF (1 << 10)
-#define AM335X_I2C_BUF_TXFIFO_CLR   (0x00000040u)
-#define AM335X_I2C_BUF_RXFIFO_CLR   (0x00004000u)
-#define AM335X_I2C_IRQSTATUS_AAS  (1 << 9)
-#define AM335X_I2C_IRQSTATUS_BF  (1 << 8)
-#define AM335X_I2C_IRQSTATUS_STC  (1 << 6)
-#define AM335X_I2C_IRQSTATUS_GC (1 << 5)
-#define AM335X_I2C_IRQSTATUS_XDR (1 << 14)
-#define AM335X_I2C_IRQSTATUS_RDR (1 << 13)
-
-#define AM335X_I2C_INT_RECV_READY AM335X_I2C_IRQSTATUS_RRDY
-#define AM335X_I2C_CON_STOP  (0x00000002u)
-#define AM335X_I2C_CON_START (0x00000001u)
-#define AM335X_I2C_CFG_MST_RX AM335X_I2C_CON_MST
-#define AM335X_I2C_CFG_MST_TX  (AM335X_I2C_CON_TRX | AM335X_I2C_CON_MST)
-#define AM335X_I2C_IRQSTATUS_RAW_BB   (0x00001000u)
-#define AM335X_CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK (0x00000020u)
-#define AM335X_I2C_INT_STOP_CONDITION AM335X_I2C_IRQSTATUS_BF
-
-#endif
diff --git a/c/src/lib/libcpu/arm/shared/include/mmu.h b/c/src/lib/libcpu/arm/shared/include/mmu.h
deleted file mode 100644
index b82e838695..0000000000
--- a/c/src/lib/libcpu/arm/shared/include/mmu.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- *  ARM MMU header file
- */
-
-/*
- *  Copyright (c) 2004 by Cogent Computer Systems
- *  Written by Jay Monkman <jtm@lopingdog.com>
- */
-
-#ifndef __LIBCPU_MMU_H__
-#define __LIBCPU_MMU_H__
-
-#include <stdint.h>
-
-#define MMU_SECT_SIZE         0x100000
-
-#define MMU_CACHE_NONE        0x0
-#define MMU_CACHE_BUFFERED    0x1
-#define MMU_CACHE_WTHROUGH    0x2
-#define MMU_CACHE_WBACK       0x3
-
-typedef struct {
-    uint32_t paddr;
-    uint32_t vaddr;
-    uint32_t size;         /* in MB */
-    uint8_t  cache_flags;
-} mmu_sect_map_t;
-
-void mmu_init(mmu_sect_map_t *map);
-void mmu_set_cpu_async_mode(void);
-
-#endif /* __MMU_H__ */
diff --git a/c/src/lib/libcpu/arm/shared/include/omap3.h b/c/src/lib/libcpu/arm/shared/include/omap3.h
deleted file mode 100644
index 0cc43d6383..0000000000
--- a/c/src/lib/libcpu/arm/shared/include/omap3.h
+++ /dev/null
@@ -1,384 +0,0 @@
-/*
- * Copyright (c) 2012 Claas Ziemke. All rights reserved.
- *
- *  Claas Ziemke
- *  Kernerstrasse 11
- *  70182 Stuttgart
- *  Germany
- *  <claas.ziemke@gmx.net>
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- *
- * Modified by Ben Gras <beng@shrike-systems.com> to add lots
- * of beagleboard/beaglebone definitions, delete lpc32xx specific
- * ones, and merge with some other header files.
- */
-
-/* Interrupt controller memory map */
-#define OMAP3_DM37XX_INTR_BASE 0x48200000 /* INTCPS physical address */
-
-/* Interrupt controller memory map */
-#define OMAP3_AM335X_INTR_BASE 0x48200000 /* INTCPS physical address */
-
-/* Interrupt controller registers */
-#define OMAP3_INTCPS_REVISION     0x000 /* IP revision code */
-#define OMAP3_INTCPS_SYSCONFIG    0x010 /* Controls params */
-#define OMAP3_INTCPS_SYSSTATUS    0x014 /* Status */
-#define OMAP3_INTCPS_SIR_IRQ      0x040 /* Active IRQ number */
-#define OMAP3_INTCPS_SIR_FIQ      0x044 /* Active FIQ number */
-#define OMAP3_INTCPS_CONTROL      0x048 /* New int agreement bits */
-#define OMAP3_INTCPS_PROTECTION   0x04C /* Protection for other regs */
-#define OMAP3_INTCPS_IDLE         0x050 /* Clock auto-idle/gating */
-#define OMAP3_INTCPS_IRQ_PRIORITY 0x060 /* Active IRQ priority level */
-#define OMAP3_INTCPS_FIQ_PRIORITY 0x064 /* Active FIQ priority level */
-#define OMAP3_INTCPS_THRESHOLD    0x068 /* Priority threshold */
-#define OMAP3_INTCPS_ITR0         0x080 /* Raw pre-masking interrupt status */
-#define OMAP3_INTCPS_MIR0         0x084 /* Interrupt mask */
-#define OMAP3_INTCPS_MIR1         0x0A4 /* Interrupt mask */
-#define OMAP3_INTCPS_MIR2         0x0C4 /* Interrupt mask */
-#define OMAP3_INTCPS_MIR3         0x0E4 /* Interrupt mask */
-#define OMAP3_INTCPS_MIR_CLEAR0   0x088 /* Clear interrupt mask bits */
-#define OMAP3_INTCPS_MIR_SET0     0x08C /* Set interrupt mask bits */
-#define OMAP3_INTCPS_ISR_SET0     0x090 /* Set software int bits */
-#define OMAP3_INTCPS_ISR_CLEAR0   0x094 /* Clear software int bits */
-#define OMAP3_INTCPS_PENDING_IRQ0 0x098 /* IRQ status post-masking */
-#define OMAP3_INTCPS_PENDING_IRQ1 0x0b8 /* IRQ status post-masking */
-#define OMAP3_INTCPS_PENDING_IRQ2 0x0d8 /* IRQ status post-masking */
-#define OMAP3_INTCPS_PENDING_IRQ3 0x0f8 /* IRQ status post-masking */
-#define OMAP3_INTCPS_PENDING_FIQ0 0x09C /* FIQ status post-masking */
-#define OMAP3_INTCPS_ILR0         0x100 /* Priority for interrupts */
-
-/* SYSCONFIG */
-#define OMAP3_SYSCONFIG_AUTOIDLE	0x01	/* SYSCONFIG.AUTOIDLE bit */
-
-#define OMAP3_INTR_ITR(base,n) \
-    (base + OMAP3_INTCPS_ITR0 + 0x20 * (n))
-#define OMAP3_INTR_MIR(base,n) \
-    (base + OMAP3_INTCPS_MIR0 + 0x20 * (n))
-#define OMAP3_INTR_MIR_CLEAR(base,n)	\
-    (base + OMAP3_INTCPS_MIR_CLEAR0 + 0x20 * (n))
-#define OMAP3_INTR_MIR_SET(base,n) \
-    (base + OMAP3_INTCPS_MIR_SET0 + 0x20 * (n))
-#define OMAP3_INTR_ISR_SET(base,n) \
-    (base + OMAP3_INTCPS_ISR_SET0 + 0x20 * (n))
-#define OMAP3_INTR_ISR_CLEAR(base,n) \
-    (base + OMAP3_INTCPS_ISR_CLEAR0 + 0x20 * (n))
-#define OMAP3_INTR_PENDING_IRQ(base,n) \
-    (base + OMAP3_INTCPS_PENDING_IRQ0 + 0x20 * (n))
-#define OMAP3_INTR_PENDING_FIQ(base,n) \
-    (base + OMAP3_INTCPS_PENDING_FIQ0 + 0x20 * (n))
-#define OMAP3_INTR_ILR(base,m) \
-    (base + OMAP3_INTCPS_ILR0 + 0x4 * (m))
-
-#define OMAP3_INTR_SPURIOUSIRQ_MASK (0x1FFFFFF << 7) /* Spurious IRQ mask for SIR_IRQ */
-#define OMAP3_INTR_ACTIVEIRQ_MASK 0x7F /* Active IRQ mask for SIR_IRQ */
-#define OMAP3_INTR_NEWIRQAGR      0x1  /* New IRQ Generation */
-
-#define OMAP3_DM337X_NR_IRQ_VECTORS    96
-
-/* Interrupt mappings */
-#define OMAP3_MCBSP2_ST_IRQ  4  /* Sidestone McBSP2 overflow */
-#define OMAP3_MCBSP3_ST_IRQ  5  /* Sidestone McBSP3 overflow */
-#define OMAP3_SYS_NIRQ       7  /* External source (active low) */
-#define OMAP3_SMX_DBG_IRQ    9  /* L3 interconnect error for debug */
-#define OMAP3_SMX_APP_IRQ   10  /* L3 interconnect error for application */
-#define OMAP3_PRCM_IRQ      11  /* PRCM module */
-#define OMAP3_SDMA0_IRQ     12  /* System DMA request 0 */
-#define OMAP3_SDMA1_IRQ     13  /* System DMA request 1 */
-#define OMAP3_SDMA2_IRQ     14  /* System DMA request 2 */
-#define OMAP3_SDMA3_IRQ     15  /* System DMA request 3 */
-#define OMAP3_MCBSP1_IRQ    16  /* McBSP module 1 */
-#define OMAP3_MCBSP2_IRQ    17  /* McBSP module 2 */
-#define OMAP3_GPMC_IRQ      20  /* General-purpose memory controller */
-#define OMAP3_SGX_IRQ       21  /* 2D/3D graphics module */
-#define OMAP3_MCBSP3_IRQ    22  /* McBSP module 3 */
-#define OMAP3_MCBSP4_IRQ    23  /* McBSP module 4 */
-#define OMAP3_CAM0_IRQ      24  /* Camera interface request 0 */
-#define OMAP3_DSS_IRQ       25  /* Display subsystem module */
-#define OMAP3_MAIL_U0_IRQ   26  /* Mailbox user 0 request */
-#define OMAP3_MCBSP5_IRQ    27  /* McBSP module 5 */
-#define OMAP3_IVA2_MMU_IRQ  28  /* IVA2 MMU */
-#define OMAP3_GPIO1_IRQ     29  /* GPIO module 1 */
-#define OMAP3_GPIO2_IRQ     30  /* GPIO module 2 */
-#define OMAP3_GPIO3_IRQ     31  /* GPIO module 3 */
-#define OMAP3_GPIO4_IRQ     32  /* GPIO module 4 */
-#define OMAP3_GPIO5_IRQ     33  /* GPIO module 5 */
-#define OMAP3_GPIO6_IRQ     34  /* GPIO module 6 */
-#define OMAP3_WDT3_IRQ      36  /* Watchdog timer module 3 overflow */
-#define OMAP3_GPT1_IRQ      37  /* General-purpose timer module 1 */
-#define OMAP3_GPT2_IRQ      38  /* General-purpose timer module 2 */
-#define OMAP3_GPT3_IRQ      39  /* General-purpose timer module 3 */
-#define OMAP3_GPT4_IRQ      40  /* General-purpose timer module 4 */
-#define OMAP3_GPT5_IRQ      41  /* General-purpose timer module 5 */
-#define OMAP3_GPT6_IRQ      42  /* General-purpose timer module 6 */
-#define OMAP3_GPT7_IRQ      43  /* General-purpose timer module 7 */
-#define OMAP3_GPT8_IRQ      44  /* General-purpose timer module 8 */
-#define OMAP3_GPT9_IRQ      45  /* General-purpose timer module 9 */
-#define OMAP3_GPT10_IRQ     46  /* General-purpose timer module 10 */
-#define OMAP3_GPT11_IRQ     47  /* General-purpose timer module 11 */
-#define OMAP3_SPI4_IRQ      48  /* McSPI module 4 */
-#define OMAP3_MCBSP4_TX_IRQ 54  /* McBSP module 4 transmit */
-#define OMAP3_MCBSP4_RX_IRQ 55  /* McBSP module 4 receive */
-#define OMAP3_I2C1_IRQ      56  /* I2C module 1 */
-#define OMAP3_I2C2_IRQ      57  /* I2C module 2 */
-#define OMAP3_HDQ_IRQ       58  /* HDQ/1-Wire */
-#define OMAP3_MCBSP1_TX_IRQ 59  /* McBSP module 1 transmit */
-#define OMAP3_MCBSP1_RX_IRQ 60  /* McBSP module 1 receive */
-#define OMAP3_I2C3_IRQ      61  /* I2C module 3 */
-#define OMAP3_MCBSP2_TX_IRQ 62  /* McBSP module 2 transmit */
-#define OMAP3_MCBSP2_RX_IRQ 63  /* McBSP module 2 receive */
-#define OMAP3_SPI1_IRQ      65  /* McSPI module 1 */
-#define OMAP3_SPI2_IRQ      66  /* McSPI module 2 */
-#define OMAP3_UART1_IRQ     72  /* UART module 1 */
-#define OMAP3_UART2_IRQ     73  /* UART module 2 */
-#define OMAP3_UART3_IRQ     74  /* UART module 3 */
-#define OMAP3_PBIAS_IRQ     75  /* Merged interrupt for PBIASlite 1/2 */
-#define OMAP3_OHCI_IRQ      76  /* OHCI HSUSB MP Host Interrupt */
-#define OMAP3_EHCI_IRQ      77  /* EHCI HSUSB MP Host Interrupt */
-#define OMAP3_TLL_IRQ       78  /* HSUSB MP TLL Interrupt */
-#define OMAP3_MCBSP5_TX_IRQ 81  /* McBSP module 5 transmit */
-#define OMAP3_MCBSP5_RX_IRQ 82  /* McBSP module 5 receive */
-#define OMAP3_MMC1_IRQ      83  /* MMC/SD module 1 */
-#define OMAP3_MMC2_IRQ      86  /* MMC/SD module 2 */
-#define OMAP3_ICR_IRQ       87  /* MPU ICR */
-#define OMAP3_D2DFRINT_IRQ  88  /* 3G coproc (in stacked modem config) */
-#define OMAP3_MCBSP3_TX_IRQ 89  /* McBSP module 3 transmit */
-#define OMAP3_MCBSP3_RX_IRQ 90  /* McBSP module 3 receive */
-#define OMAP3_SPI3_IRQ      91  /* McSPI module 3 */
-#define OMAP3_HSUSB_MC_IRQ  92  /* High-speed USB OTG */
-#define OMAP3_HSUSB_DMA_IRQ 93  /* High-speed USB OTG DMA */
-#define OMAP3_MMC3_IRQ      94  /* MMC/SD module 3 */
-
-/* General-purpose timer register map */
-#define OMAP3_GPTIMER1_BASE  0x48318000
-    /* GPTIMER1 physical address */
-#define OMAP3_GPTIMER2_BASE  0x49032000
-    /* GPTIMER2 physical address */
-#define OMAP3_GPTIMER3_BASE  0x49034000
-    /* GPTIMER3 physical address */
-#define OMAP3_GPTIMER4_BASE  0x49036000
-    /* GPTIMER4 physical address */
-#define OMAP3_GPTIMER5_BASE  0x49038000
-    /* GPTIMER5 physical address */
-#define OMAP3_GPTIMER6_BASE  0x4903A000
-    /* GPTIMER6 physical address */
-#define OMAP3_GPTIMER7_BASE  0x4903C000
-    /* GPTIMER7 physical address */
-#define OMAP3_GPTIMER8_BASE  0x4903E000
-    /* GPTIMER8 physical address */
-#define OMAP3_GPTIMER9_BASE  0x49040000
-    /* GPTIMER9 physical address */
-#define OMAP3_GPTIMER10_BASE 0x48086000
-    /* GPTIMER10 physical address */
-#define OMAP3_GPTIMER11_BASE 0x48088000
-    /* GPTIMER11 physical address */
-
-
-/* General-purpose timer registers */
-#define OMAP3_TIMER_TIDR      0x000
-    /* IP revision code */
-#define OMAP3_TIMER_TIOCP_CFG 0x010
-    /* Controls params for GP timer L4 iface */
-#define OMAP3_TIMER_TISTAT    0x014
-    /* Status (excl. interrupt status) */
-#define OMAP3_TIMER_TISR      0x018
-    /* Pending interrupt status */
-#define OMAP3_TIMER_TIER      0x01C
-    /* Interrupt enable */
-#define OMAP3_TIMER_TWER      0x020
-    /* Wakeup enable */
-#define OMAP3_TIMER_TCLR      0x024
-    /* Controls optional features */
-#define OMAP3_TIMER_TCRR      0x028
-    /* Internal counter value */
-#define OMAP3_TIMER_TLDR      0x02C
-    /* Timer load value */
-#define OMAP3_TIMER_TTGR      0x030
-    /* Triggers counter reload */
-#define OMAP3_TIMER_TWPS      0x034
-    /* Indicates if Write-Posted pending */
-#define OMAP3_TIMER_TMAR      0x038
-    /* Value to be compared with counter */
-#define OMAP3_TIMER_TCAR1     0x03C
-    /* First captured value of counter reg */
-#define OMAP3_TIMER_TSICR     0x040
-    /* Control posted mode and functional SW rst */
-#define OMAP3_TIMER_TCAR2     0x044
-    /* Second captured value of counter register */
-#define OMAP3_TIMER_TPIR      0x048
-    /* Positive increment (1 ms tick) */
-#define OMAP3_TIMER_TNIR      0x04C
-    /* Negative increment (1 ms tick) */
-#define OMAP3_TIMER_TCVR      0x050
-    /* Defines TCRR is sub/over-period (1 ms tick) */
-#define OMAP3_TIMER_TOCR      0x054
-    /* Masks tick interrupt */
-#define OMAP3_TIMER_TOWR      0x058
-    /* Number of masked overflow interrupts */
-
-/* Interrupt status register fields */
-#define OMAP3_TISR_MAT_IT_FLAG  (1 << 0) /* Pending match interrupt status */
-#define OMAP3_TISR_OVF_IT_FLAG  (1 << 1) /* Pending overflow interrupt status */
-#define OMAP3_TISR_TCAR_IT_FLAG (1 << 2) /* Pending capture interrupt status */
-
-/* Interrupt enable register fields */
-#define OMAP3_TIER_MAT_IT_ENA  (1 << 0) /* Enable match interrupt */
-#define OMAP3_TIER_OVF_IT_ENA  (1 << 1) /* Enable overflow interrupt */
-#define OMAP3_TIER_TCAR_IT_ENA (1 << 2) /* Enable capture interrupt */
-
-/* Timer control fields */
-#define OMAP3_TCLR_ST       (1 << 0)  /* Start/stop timer */
-#define OMAP3_TCLR_AR       (1 << 1)  /* Autoreload or one-shot mode */
-#define OMAP3_TCLR_PRE      (1 << 5)  /* Prescaler on */
-#define OMAP3_TCLR_PTV      (1 << 1)  /* looks like "bleed" from Minix */
-#define OMAP3_TCLR_OVF_TRG  (1 << 10) /* Overflow trigger */
-
-
-#define OMAP3_CM_CLKSEL_GFX		0x48004b40
-#define OMAP3_CM_CLKEN_PLL		0x48004d00
-#define OMAP3_CM_FCLKEN1_CORE	0x48004A00
-#define OMAP3_CM_CLKSEL_CORE	0x48004A40 /* GPT10 src clock sel. */
-#define OMAP3_CM_FCLKEN_PER		0x48005000
-#define OMAP3_CM_CLKSEL_PER		0x48005040
-#define OMAP3_CM_CLKSEL_WKUP    0x48004c40 /* GPT1 source clock selection */
-
-
-#define CM_MODULEMODE_MASK        (0x3 << 0)
-#define CM_MODULEMODE_ENABLE      (0x2 << 0)
-#define CM_MODULEMODE_DISABLED    (0x0 << 0)
-
-#define CM_CLKCTRL_IDLEST         (0x3 << 16)
-#define CM_CLKCTRL_IDLEST_FUNC    (0x0 << 16)
-#define CM_CLKCTRL_IDLEST_TRANS   (0x1 << 16)
-#define CM_CLKCTRL_IDLEST_IDLE    (0x2 << 16)
-#define CM_CLKCTRL_IDLEST_DISABLE (0x3 << 16)
-
-#define CM_WKUP_BASE 0x44E00400 /* Clock Module Wakeup Registers */
-
-#define CM_WKUP_TIMER1_CLKCTRL	(CM_WKUP_BASE + 0xC4)
-    /* This register manages the TIMER1 clocks. [Memory Mapped] */
-
-#define CM_PER_BASE 0x44E00000 /* Clock Module Peripheral Registers */
-#define CM_PER_TIMER7_CLKCTRL	(CM_PER_BASE + 0x7C)
-    /* This register manages the TIMER7 clocks. [Memory Mapped] */
-
-/* CM_DPLL registers */
-
-#define CM_DPLL_BASE 	0x44E00500 /* Clock Module PLL Registers */
-
-#define CLKSEL_TIMER1MS_CLK (CM_DPLL_BASE + 0x28)
-
-#define CLKSEL_TIMER1MS_CLK_SEL_MASK (0x7 << 0)
-#define CLKSEL_TIMER1MS_CLK_SEL_SEL1 (0x0 << 0)
-    /* Select CLK_M_OSC clock */
-#define CLKSEL_TIMER1MS_CLK_SEL_SEL2 (0x1 << 0)
-    /* Select CLK_32KHZ clock */
-#define CLKSEL_TIMER1MS_CLK_SEL_SEL3 (0x2 << 0)
-    /* Select TCLKIN clock */
-#define CLKSEL_TIMER1MS_CLK_SEL_SEL4 (0x3 << 0)
-    /* Select CLK_RC32K clock */
-#define CLKSEL_TIMER1MS_CLK_SEL_SEL5 (0x4 << 0)
-    /* Selects the CLK_32768 from 32KHz Crystal Osc */
-
-#define CLKSEL_TIMER7_CLK   (CM_DPLL_BASE + 0x04)
-#define CLKSEL_TIMER7_CLK_SEL_MASK (0x3 << 0)
-#define CLKSEL_TIMER7_CLK_SEL_SEL1 (0x0 << 0) /* Select TCLKIN clock */
-#define CLKSEL_TIMER7_CLK_SEL_SEL2 (0x1 << 0) /* Select CLK_M_OSC clock */
-#define CLKSEL_TIMER7_CLK_SEL_SEL3 (0x2 << 0) /* Select CLK_32KHZ clock */
-#define CLKSEL_TIMER7_CLK_SEL_SEL4 (0x3 << 0) /* Reserved */
-
-/*RTC CLOCK BASE & Registers*/
-#define CM_RTC_BASE            0x44E00800
-#define CM_RTC_RTC_CLKCTRL     0x0
-#define CM_RTC_CLKSTCTRL       0x4
-
-
-#define OMAP3_CLKSEL_GPT1    (1 << 0)
-#define OMAP3_CLKSEL_GPT10   (1 << 6)
-#define OMAP3_CLKSEL_GPT11   (1 << 7)
-
-#define OMAP34XX_CORE_L4_IO_BASE  0x48000000
-
-#define ARM_TTBR_ADDR_MASK (0xffffc000)
-#define ARM_TTBR_OUTER_NC    (0x0 << 3) /* Non-cacheable*/
-#define ARM_TTBR_OUTER_WBWA  (0x1 << 3) /* Outer Write-Back */
-#define ARM_TTBR_OUTER_WT    (0x2 << 3) /* Outer Write-Through */
-#define ARM_TTBR_OUTER_WBNWA (0x3 << 3) /* Outer Write-Back */
-#define ARM_TTBR_FLAGS_CACHED ARM_TTBR_OUTER_WBWA
-
-/* cpu control flags */
-/* CPU control register (CP15 register 1) */
-#define CPU_CONTROL_MMU_ENABLE  0x00000001 /* M: MMU/Protection unit enable */
-#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */
-#define CPU_CONTROL_DC_ENABLE   0x00000004 /* C: IDC/DC enable */
-#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */
-#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */
-#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */
-#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */
-#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */
-#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */
-#define CPU_CONTROL_ROM_ENABLE  0x00000200 /* R: ROM protection bit */
-#define CPU_CONTROL_CPCLK       0x00000400 /* F: Implementation defined */
-#define CPU_CONTROL_SWP_ENABLE  0x00000400 /* SW: SWP{B} perform normally. */
-#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */
-#define CPU_CONTROL_IC_ENABLE   0x00001000 /* I: IC enable */
-#define CPU_CONTROL_VECRELOC    0x00002000 /* V: Vector relocation */
-#define CPU_CONTROL_ROUNDROBIN  0x00004000 /* RR: Predictable replacement */
-#define CPU_CONTROL_V4COMPAT    0x00008000 /* L4: ARMv4 compat LDR R15 etc */
-#define CPU_CONTROL_FI_ENABLE   0x00200000 /* FI: Low interrupt latency */
-#define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */
-#define CPU_CONTROL_XP_ENABLE   0x00800000 /* XP: extended page table */
-#define CPU_CONTROL_V_ENABLE    0x01000000 /* VE: Interrupt vectors enable */
-#define CPU_CONTROL_EX_BEND     0x02000000 /* EE: exception endianness */
-#define CPU_CONTROL_NMFI        0x08000000 /* NMFI: Non maskable FIQ */
-#define CPU_CONTROL_TR_ENABLE   0x10000000 /* TRE: */
-#define CPU_CONTROL_AF_ENABLE   0x20000000 /* AFE: Access flag enable */
-#define CPU_CONTROL_TE_ENABLE   0x40000000 /* TE: Thumb Exception enable */
-
-#define CPU_CONTROL_IDC_ENABLE  CPU_CONTROL_DC_ENABLE
-
-/* VM bits */
-
-/* Big page (1MB section) specific flags. */
-#define ARM_VM_SECTION                  (1 << 1)
-    /* 1MB section */
-#define ARM_VM_SECTION_PRESENT          (1 << 1)
-    /* Section is present */
-#define ARM_VM_SECTION_B                (1 << 2)
-    /* B Bit */
-#define ARM_VM_SECTION_C                (1 << 3)
-    /* C Bit */
-#define ARM_VM_SECTION_DOMAIN           (0xF << 5)
-    /* Domain Number */
-#define ARM_VM_SECTION_SUPER            (0x1 << 10)
-    /* Super access only AP[1:0] */
-#define ARM_VM_SECTION_USER             (0x3 << 10)
-    /* Super/User access AP[1:0] */
-#define ARM_VM_SECTION_TEX0             (1 << 12)
-    /* TEX[0] */
-#define ARM_VM_SECTION_TEX1             (1 << 13)
-    /* TEX[1] */
-#define ARM_VM_SECTION_TEX2             (1 << 14)
-    /* TEX[2] */
-#define ARM_VM_SECTION_RO               (1 << 15)
-    /* Read only access AP[2] */
-#define ARM_VM_SECTION_SHAREABLE        (1 << 16)
-    /* Shareable */
-#define ARM_VM_SECTION_NOTGLOBAL        (1 << 17)
-    /* Not Global */
-
-#define ARM_VM_SECTION_WB \
-    (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX0 | ARM_VM_SECTION_B )
-/* inner and outer write-back, write-allocate */
-#define ARM_VM_SECTION_WT \
-    (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX1 | ARM_VM_SECTION_C )
-/* inner and outer write-through, no write-allocate */
-#define ARM_VM_SECTION_WTWB \
-    (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX0 | ARM_VM_SECTION_C )
-/* Inner , Write through, No Write Allocate Outer - Write Back, Write Allocate */
-
-/* shareable device */
-#define ARM_VM_SECTION_CACHED   ARM_VM_SECTION_WTWB
-#define ARM_VM_SECTION_DEVICE   (ARM_VM_SECTION_B)
diff --git a/c/src/lib/libcpu/arm/shared/include/omap_timer.h b/c/src/lib/libcpu/arm/shared/include/omap_timer.h
deleted file mode 100644
index ef8787a571..0000000000
--- a/c/src/lib/libcpu/arm/shared/include/omap_timer.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/**
- * @file
- *
- * @brief Clock driver configuration.
- */
-
-#include <stdint.h>
-
-typedef struct omap_timer_registers
-{
-  uint32_t TIDR;
-  uint32_t TIOCP_CFG;
-  uint32_t TISTAT;
-  uint32_t TISR;
-  uint32_t TIER;
-  uint32_t TWER;
-  uint32_t TCLR;
-  uint32_t TCRR;
-  uint32_t TLDR;
-  uint32_t TTGR;
-  uint32_t TWPS;
-  uint32_t TMAR;
-  uint32_t TCAR1;
-  uint32_t TSICR;
-  uint32_t TCAR2;
-  uint32_t TPIR;
-  uint32_t TNIR;
-  uint32_t TCVR;
-  uint32_t TOCR;
-  uint32_t TOWR;
-
-} omap_timer_registers_t;
-
-typedef struct omap_timer
-{
-  uint32_t base;
-  int irq_nr;
-  struct omap_timer_registers *regs;
-} omap_timer_t;