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author | Daniel Cederman <cederman@gaisler.com> | 2014-07-11 16:37:56 +0200 |
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committer | Daniel Hellstrom <daniel@gaisler.com> | 2014-08-22 13:10:59 +0200 |
commit | ddbc3f8d83678313ca61d2936e6efd50b3e044b0 (patch) | |
tree | 305f3c4a7df80244bac626682d43718e7284e714 /c/src/lib/libbsp | |
parent | bsp/sparc: Flush only instruction cache (diff) | |
download | rtems-ddbc3f8d83678313ca61d2936e6efd50b3e044b0.tar.bz2 |
score: Add SMP support to the cache manager
Adds functions that allows the user to specify which cores that should
perform the cache operation. SMP messages are sent to all the specified
cores and the caller waits until all cores have acknowledged that they
have flushed their cache. If CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING is
defined the instruction cache invalidation function will perform the
operation on all cores using the previous method.
Diffstat (limited to 'c/src/lib/libbsp')
-rw-r--r-- | c/src/lib/libbsp/sparc/leon3/include/cache_.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/sparc/leon3/include/cache_.h b/c/src/lib/libbsp/sparc/leon3/include/cache_.h index c7813678b9..ced5b6dd0a 100644 --- a/c/src/lib/libbsp/sparc/leon3/include/cache_.h +++ b/c/src/lib/libbsp/sparc/leon3/include/cache_.h @@ -26,6 +26,8 @@ extern "C" { #define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS +#define CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING + #define CPU_INSTRUCTION_CACHE_ALIGNMENT 64 #define CPU_DATA_CACHE_ALIGNMENT 64 |