diff options
author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2008-08-21 14:57:19 +0000 |
---|---|---|
committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2008-08-21 14:57:19 +0000 |
commit | d79a27be40c6c21732f83fbec61275fed78d2a2c (patch) | |
tree | 0525916dc976bf44de7fe684ac873ce6f00fd060 /c/src/lib/libbsp | |
parent | 2008-08-21 Joel Sherrill <joel.sherrill@OARcorp.com> (diff) | |
download | rtems-d79a27be40c6c21732f83fbec61275fed78d2a2c.tar.bz2 |
2008-08-21 Sebastian Huber <sebastian.huber@embedded-brains.de>
* startup/cpuinit.h: Uses now powerpc-utility.h. Changed invalid usage
of a boolean type to a proper integer type in calc_dbat_regvals().
Througout code formatting.
Diffstat (limited to 'c/src/lib/libbsp')
-rw-r--r-- | c/src/lib/libbsp/powerpc/gen83xx/ChangeLog | 6 | ||||
-rw-r--r-- | c/src/lib/libbsp/powerpc/gen83xx/startup/cpuinit.c | 314 |
2 files changed, 186 insertions, 134 deletions
diff --git a/c/src/lib/libbsp/powerpc/gen83xx/ChangeLog b/c/src/lib/libbsp/powerpc/gen83xx/ChangeLog index 6f36141809..4aed65fab1 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/ChangeLog +++ b/c/src/lib/libbsp/powerpc/gen83xx/ChangeLog @@ -1,3 +1,9 @@ +2008-08-21 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * startup/cpuinit.h: Uses now powerpc-utility.h. Changed invalid usage + of a boolean type to a proper integer type in calc_dbat_regvals(). + Througout code formatting. + 2008-08-20 Sebastian Huber <sebastian.huber@embedded-brains.de> * include/tm27.h: Uses now a decrementer exception handler. Replaces diff --git a/c/src/lib/libbsp/powerpc/gen83xx/startup/cpuinit.c b/c/src/lib/libbsp/powerpc/gen83xx/startup/cpuinit.c index c07b414713..95a84e197c 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/startup/cpuinit.c +++ b/c/src/lib/libbsp/powerpc/gen83xx/startup/cpuinit.c @@ -70,183 +70,229 @@ /* */ /***********************************************************************/ -#include <bsp.h> -#include <rtems/powerpc/registers.h> -#include <mpc83xx/mpc83xx.h> +#include <stdbool.h> +#include <string.h> +#include <libcpu/powerpc-utility.h> #include <libcpu/mmu.h> -#include <libcpu/spr.h> -#include <string.h> -#define USE_IMMU - -/* Macros for HID0 access */ -#define SET_HID0(r) __asm__ volatile ("mtspr 0x3F0,%0\n" ::"r"(r)) -#define GET_HID0(r) __asm__ volatile ("mfspr %0,0x3F0\n" :"=r"(r)) - -#define DBAT_MTSPR(val,name) __MTSPR(val,name); -#define SET_DBAT(n,uv,lv) {DBAT_MTSPR(lv,DBAT##n##L);DBAT_MTSPR(uv,DBAT##n##U);} -#if defined(USE_IMMU ) -#define IBAT_MTSPR(val,name) __MTSPR(val,name); -#define SET_IBAT(n,uv,lv) {IBAT_MTSPR(lv,IBAT##n##L);IBAT_MTSPR(uv,IBAT##n##U);} -#endif - -static void calc_dbat_regvals(BAT *bat_ptr, - uint32_t base_addr, - uint32_t size, - boolean flg_w, - boolean flg_i, - boolean flg_m, - boolean flg_g, - boolean flg_bpp) +#include <mpc83xx/mpc83xx.h> + +#include <bsp.h> + +#define SET_DBAT( n, uv, lv) \ + do { \ + PPC_SET_SPECIAL_PURPOSE_REGISTER( DBAT##n##L, lv); \ + PPC_SET_SPECIAL_PURPOSE_REGISTER( DBAT##n##U, uv); \ + } while (0) + +#define SET_IBAT( n, uv, lv) \ + do { \ + PPC_SET_SPECIAL_PURPOSE_REGISTER( IBAT##n##L, lv); \ + PPC_SET_SPECIAL_PURPOSE_REGISTER( IBAT##n##U, uv); \ + } while (0) + +static void calc_dbat_regvals( + BAT *bat_ptr, + uint32_t base_addr, + uint32_t size, + bool flg_w, + bool flg_i, + bool flg_m, + bool flg_g, + uint32_t flg_bpp +) { - uint32_t block_mask; - uint32_t end_addr; + uint32_t block_mask = 0xffffffff; + uint32_t end_addr = base_addr + size - 1; - /* - * determine block mask, that overlaps the whole block - */ - end_addr = base_addr+size-1; - block_mask = 0xffffffff; + /* Determine block mask, that overlaps the whole block */ while ((end_addr & block_mask) != (base_addr & block_mask)) { block_mask <<= 1; } - bat_ptr->batu.bepi = base_addr >> (32-15); - bat_ptr->batu.bl = ~(block_mask >> (28-11)); - bat_ptr->batu.vs = 1; - bat_ptr->batu.vp = 1; + bat_ptr->batu.bepi = base_addr >> (32 - 15); + bat_ptr->batu.bl = ~(block_mask >> (28 - 11)); + bat_ptr->batu.vs = 1; + bat_ptr->batu.vp = 1; - bat_ptr->batl.brpn = base_addr >> (32-15); - bat_ptr->batl.w = flg_w; - bat_ptr->batl.i = flg_i; - bat_ptr->batl.m = flg_m; - bat_ptr->batl.g = flg_g; - bat_ptr->batl.pp = flg_bpp; + bat_ptr->batl.brpn = base_addr >> (32 - 15); + bat_ptr->batl.w = flg_w; + bat_ptr->batl.i = flg_i; + bat_ptr->batl.m = flg_m; + bat_ptr->batl.g = flg_g; + bat_ptr->batl.pp = flg_bpp; } -static void clear_mmu_regs(void) +static void clear_mmu_regs( void) { uint32_t i; - /* - * clear segment registers - */ + + /* Clear segment registers */ for (i = 0;i < 16;i++) { - asm volatile(" mtsrin %0, %1\n"::"r" (i * 0x1000),"r"(i<<(31-3))); + asm volatile( "mtsrin %0, %1\n" : : "r" (i * 0x1000), "r" (i << (31 - 3))); } - /* - * clear TLBs - */ + + /* Clear TLBs */ for (i = 0;i < 32;i++) { - asm volatile(" tlbie %0\n"::"r" (i << (31-19))); + asm volatile( "tlbie %0\n" : : "r" (i << (31 - 19))); } } -void cpu_init(void) +void cpu_init( void) { - register unsigned long reg; - BAT dbat,ibat; + BAT dbat, ibat; + uint32_t msr; - /* - * clear MMU/Segment registers - */ + /* Clear MMU and segment registers */ clear_mmu_regs(); - /* - * clear caches - */ - GET_HID0(reg); - reg = (reg & ~(HID0_ILOCK | HID0_DLOCK)) | HID0_ICFI | HID0_DCI; - SET_HID0(reg); - reg &= ~(HID0_ICFI | HID0_DCI); - SET_HID0(reg); + + /* Clear caches */ + PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_ILOCK | HID0_DLOCK); + PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_ICFI | HID0_DCI); + PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_ICFI | HID0_DCI); /* - * set up IBAT registers in MMU + * Set up IBAT registers in MMU */ - memset(&ibat,0,sizeof(ibat)); - SET_IBAT(2,ibat.batu,ibat.batl); - SET_IBAT(3,ibat.batu,ibat.batl); - SET_IBAT(4,ibat.batu,ibat.batl); - SET_IBAT(5,ibat.batu,ibat.batl); - SET_IBAT(6,ibat.batu,ibat.batl); - SET_IBAT(7,ibat.batu,ibat.batl); -#ifdef HAS_UBOOT - calc_dbat_regvals(&ibat,mpc83xx_uboot_board_info.bi_memstart,mpc83xx_uboot_board_info.bi_memsize,0,0,0,0,BPP_RX); -#else /* HAS_UBOOT */ - calc_dbat_regvals(&ibat,(uint32_t) bsp_ram_start,(uint32_t) bsp_ram_size,0,0,0,0,BPP_RX); -#endif /* HAS_UBOOT */ - - SET_IBAT(0,ibat.batu,ibat.batl); - -#ifdef HAS_UBOOT - calc_dbat_regvals(&ibat,mpc83xx_uboot_board_info.bi_flashstart,mpc83xx_uboot_board_info.bi_flashsize,0,0,0,0,BPP_RX); -#else /* HAS_UBOOT */ - calc_dbat_regvals(&ibat,(uint32_t) bsp_rom_start,(uint32_t) bsp_rom_size,0,0,0,0,BPP_RX); -#endif /* HAS_UBOOT */ - - SET_IBAT(1,ibat.batu,ibat.batl); - /* - * set up DBAT registers in MMU - */ - memset(&dbat,0,sizeof(dbat)); - SET_DBAT(3,dbat.batu,dbat.batl); - SET_DBAT(4,dbat.batu,dbat.batl); - SET_DBAT(5,dbat.batu,dbat.batl); - SET_DBAT(6,dbat.batu,dbat.batl); - SET_DBAT(7,dbat.batu,dbat.batl); + memset(&ibat, 0, sizeof( ibat)); + SET_IBAT( 2, ibat.batu, ibat.batl); + SET_IBAT( 3, ibat.batu, ibat.batl); + SET_IBAT( 4, ibat.batu, ibat.batl); + SET_IBAT( 5, ibat.batu, ibat.batl); + SET_IBAT( 6, ibat.batu, ibat.batl); + SET_IBAT( 7, ibat.batu, ibat.batl); + + calc_dbat_regvals( + &ibat, + #ifdef HAS_UBOOT + mpc83xx_uboot_board_info.bi_memstart, + mpc83xx_uboot_board_info.bi_memsize, + #else /* HAS_UBOOT */ + (uint32_t) bsp_ram_start, + (uint32_t) bsp_ram_size, + #endif /* HAS_UBOOT */ + false, + false, + false, + false, + BPP_RX + ); + SET_IBAT( 0, ibat.batu, ibat.batl); -#ifdef HAS_UBOOT - calc_dbat_regvals(&dbat,mpc83xx_uboot_board_info.bi_memstart,mpc83xx_uboot_board_info.bi_memsize,0,0,0,0,BPP_RW); -#else /* HAS_UBOOT */ - calc_dbat_regvals(&dbat,(uint32_t) bsp_ram_start,(uint32_t) bsp_ram_size,0,0,0,0,BPP_RW); -#endif /* HAS_UBOOT */ + calc_dbat_regvals( + &ibat, + #ifdef HAS_UBOOT + mpc83xx_uboot_board_info.bi_flashstart, + mpc83xx_uboot_board_info.bi_flashsize, + #else /* HAS_UBOOT */ + (uint32_t) bsp_rom_start, + (uint32_t) bsp_rom_size, + #endif /* HAS_UBOOT */ + false, + false, + false, + false, + BPP_RX + ); + SET_IBAT( 1, ibat.batu, ibat.batl); - SET_DBAT(0,dbat.batu,dbat.batl); + /* + * Set up DBAT registers in MMU + */ -#ifdef HAS_UBOOT - calc_dbat_regvals(&dbat,mpc83xx_uboot_board_info.bi_flashstart,mpc83xx_uboot_board_info.bi_flashsize,0,0,0,0,BPP_RX); -#else /* HAS_UBOOT */ - calc_dbat_regvals(&dbat,(uint32_t) bsp_rom_start,(uint32_t) bsp_rom_size,0,0,0,0,BPP_RX); -#endif /* HAS_UBOOT */ + memset(&dbat, 0, sizeof( dbat)); + SET_DBAT( 3, dbat.batu, dbat.batl); + SET_DBAT( 4, dbat.batu, dbat.batl); + SET_DBAT( 5, dbat.batu, dbat.batl); + SET_DBAT( 6, dbat.batu, dbat.batl); + SET_DBAT( 7, dbat.batu, dbat.batl); - SET_DBAT(1,dbat.batu,dbat.batl); + calc_dbat_regvals( + &dbat, + #ifdef HAS_UBOOT + mpc83xx_uboot_board_info.bi_memstart, + mpc83xx_uboot_board_info.bi_memsize, + #else /* HAS_UBOOT */ + (uint32_t) bsp_ram_start, + (uint32_t) bsp_ram_size, + #endif /* HAS_UBOOT */ + false, + false, + false, + false, + BPP_RW + ); + SET_DBAT( 0, dbat.batu, dbat.batl); -#ifdef HAS_UBOOT - calc_dbat_regvals(&dbat,mpc83xx_uboot_board_info.bi_immrbar,1024*1024,0,1,0,1,BPP_RW); -#else /* HAS_UBOOT */ - calc_dbat_regvals(&dbat,(uint32_t) IMMRBAR,1024*1024,0,1,0,1,BPP_RW); -#endif /* HAS_UBOOT */ + calc_dbat_regvals( + &dbat, + #ifdef HAS_UBOOT + mpc83xx_uboot_board_info.bi_flashstart, + mpc83xx_uboot_board_info.bi_flashsize, + #else /* HAS_UBOOT */ + (uint32_t) bsp_rom_start, + (uint32_t) bsp_rom_size, + #endif /* HAS_UBOOT */ + false, + false, + false, + false, + BPP_RX + ); + SET_DBAT( 1, dbat.batu, dbat.batl); - SET_DBAT(2,dbat.batu,dbat.batl); + calc_dbat_regvals( + &dbat, + #ifdef HAS_UBOOT + mpc83xx_uboot_board_info.bi_immrbar, + #else /* HAS_UBOOT */ + (uint32_t) IMMRBAR, + #endif /* HAS_UBOOT */ + 1024 * 1024, + false, + true, + false, + true, + BPP_RW + ); + SET_DBAT( 2, dbat.batu, dbat.batl); #ifdef MPC8313ERDB /* Enhanced Local Bus Controller (eLBC) */ - calc_dbat_regvals( &dbat, 0xfa000000, 128 * 1024, 0, 1, 0, 1, BPP_RW); + calc_dbat_regvals( + &dbat, + 0xfa000000, + 128 * 1024, + false, + true, + false, + true, + BPP_RW + ); SET_DBAT( 3, dbat.batu, dbat.batl); #endif /* MPC8313ERDB */ - /* - * enable data/instruction MMU in MSR - */ - _write_MSR(_read_MSR() | MSR_DR | MSR_IR); + /* Read MSR */ + msr = ppc_machine_state_register(); - /* - * enable FPU in MSR - */ - _write_MSR(_read_MSR() | MSR_FP); + /* Enable data and instruction MMU in MSR */ + msr |= MSR_DR | MSR_IR; - /* - * in HID0: - * - enable dynamic power management - * - enable machine check interrupts - */ - GET_HID0(reg); - reg |= (HID0_EMCP | HID0_DPM) ; - SET_HID0(reg); + /* Enable FPU in MSR */ + msr |= MSR_FP; + + /* Update MSR */ + ppc_set_machine_state_register( msr); /* - * enable timebase clock + * In HID0: + * - Enable dynamic power management + * - Enable machine check interrupts */ + PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_EMCP | HID0_DPM); + + /* Enable timebase clock */ mpc83xx.syscon.spcr |= M83xx_SYSCON_SPCR_TBEN; } |