2002-02-27 Greg Menke <gregory.menke@gsfc.nasa.gov>

	* cpu_asm.S: Fixed exception return address, modified FP context
	switch so FPU is properly enabled and also doesn't screw up the
	exception FP handling.
	* idtcpu.h: Added C0_TAR, the MIPS target address register used for
	returning from exceptions.
	* iregdef.h: Added R_TAR to the stack frame so the target address
	can be saved on a per-exception basis.  The new entry is past the
	end of the frame gdb cares about, so doesn't affect gdb or cpu.h
	stuff.
	* rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
	to obtain FPU defines without systax errors generated by the C
	defintions.
	* cpu.c: Improved interrupt level saves & restores.

0 files changed, 0 insertions, 0 deletions