diff options
author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-04-25 15:06:08 +0200 |
---|---|---|
committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-04-26 07:17:57 +0200 |
commit | eb36d1198cdf9dc1e2f776ef6e1e38755f6d13c5 (patch) | |
tree | 14177ad7a58c06a3c537d1e55dae7bc369a1a4b9 /c/src/lib/libbsp/sparc64 | |
parent | bsps: Remove unmaintained times files (diff) | |
download | rtems-eb36d1198cdf9dc1e2f776ef6e1e38755f6d13c5.tar.bz2 |
bsps: Move documentation, etc. files to bsps
This patch is a part of the BSP source reorganization.
Update #3285.
Diffstat (limited to 'c/src/lib/libbsp/sparc64')
-rw-r--r-- | c/src/lib/libbsp/sparc64/niagara/README | 65 | ||||
-rw-r--r-- | c/src/lib/libbsp/sparc64/usiii/README | 57 |
2 files changed, 0 insertions, 122 deletions
diff --git a/c/src/lib/libbsp/sparc64/niagara/README b/c/src/lib/libbsp/sparc64/niagara/README deleted file mode 100644 index ea393587cf..0000000000 --- a/c/src/lib/libbsp/sparc64/niagara/README +++ /dev/null @@ -1,65 +0,0 @@ -BSP NAME: niagara -BOARD: -BUS: n/a -CPU FAMILY: SPARC V9 with UltraSPARC Architecture 2005 (a.k.a. sun4v) -CPU: UltraSPARC T1 (OpenSPARC T1) -COPROCESSORS: -MODE: n/a - -DEBUG MONITOR: - -PERIPHERALS -=========== -TIMERS: TICK and STICK registers (ASRs 4 and 24) - RESOLUTION: CPU clock resolution -SERIAL PORTS: -REAL-TIME CLOCK: -DMA: none -VIDEO: none -SCSI: none -NETWORKING: none - -DRIVER INFORMATION -================== -CLOCK DRIVER: -IOSUPP DRIVER: -SHMSUPP: -TIMER DRIVER: -TTY DRIVER: - -STDIO -===== -PORT: -ELECTRICAL: -BAUD: -BITS PER CHARACTER: -PARITY: -STOP BITS: - -NOTES -===== - -Board description ------------------ -clock rate: -bus width: -ROM: -RAM: - -This BSP is designed to operate on the UltraSPARC T1 (Niagara) SPARC64 -and similar processors. - -This BSP has been run on the Simics simulator with the niagara target, which -simulates the OpenSPARC T1 Niagara implementation. - -This BSP has been run on the M5 simulator with the SPARC_FS target, which -simulates the OpenSPARC T1 Niagara implementation. - -Simics: -A commercially available simulator licensed by Virtutech. -https://www.simics.net/ - -M5: -An open-source simulator. -http://www.m5sim.org/wiki/index.php/Main_Page - diff --git a/c/src/lib/libbsp/sparc64/usiii/README b/c/src/lib/libbsp/sparc64/usiii/README deleted file mode 100644 index 83c6b68b22..0000000000 --- a/c/src/lib/libbsp/sparc64/usiii/README +++ /dev/null @@ -1,57 +0,0 @@ -BSP NAME: usiii -BOARD: -BUS: n/a -CPU FAMILY: SPARC V9 (a.k.a. sun4u) -CPU: UltraSPARC III -COPROCESSORS: -MODE: n/a - -DEBUG MONITOR: - -PERIPHERALS -=========== -TIMERS: TICK register (ASR 4) - RESOLUTION: CPU clock resolution -SERIAL PORTS: -REAL-TIME CLOCK: -DMA: none -VIDEO: none -SCSI: none -NETWORKING: none - -DRIVER INFORMATION -================== -CLOCK DRIVER: -IOSUPP DRIVER: -SHMSUPP: -TIMER DRIVER: -TTY DRIVER: - -STDIO -===== -PORT: -ELECTRICAL: -BAUD: -BITS PER CHARACTER: -PARITY: -STOP BITS: - -NOTES -===== - -Board description ------------------ -clock rate: -bus width: -ROM: -RAM: - -This BSP is designed to operate on the UltraSPARC III SPARC64 -and similar processors. - -This BSP has been run on the Simics simulator with the serengeti target. - -Simics: -A commercially available simulator licensed by Virtutech. -https://www.simics.net/ - |