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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-04-22 07:46:56 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-04-28 09:26:19 +0200 |
| commit | b2ec2d15971503466e1debf596dc84b6af0f9b13 (patch) | |
| tree | 9c5ccc58cf5c957d5c21f36cd1eb5a73e899b377 /c/src/lib/libbsp/sparc/shared/irq_asm.S | |
| parent | score: Add _CPU_Get_current_per_CPU_control() (diff) | |
| download | rtems-b2ec2d15971503466e1debf596dc84b6af0f9b13.tar.bz2 | |
sparc: Optimize context switch
The registers g2 through g4 are reserved for applications. GCC uses
them as volatile registers by default. So they are treated like
volatile registers in RTEMS as well.
Diffstat (limited to 'c/src/lib/libbsp/sparc/shared/irq_asm.S')
| -rw-r--r-- | c/src/lib/libbsp/sparc/shared/irq_asm.S | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/c/src/lib/libbsp/sparc/shared/irq_asm.S b/c/src/lib/libbsp/sparc/shared/irq_asm.S index fc4c0be6d8..fd8269f0ce 100644 --- a/c/src/lib/libbsp/sparc/shared/irq_asm.S +++ b/c/src/lib/libbsp/sparc/shared/irq_asm.S @@ -52,8 +52,7 @@ .align 4 PUBLIC(_CPU_Context_switch) SYM(_CPU_Context_switch): - std %g2, [%o0 + G2_OFFSET] ! save the global registers - std %g4, [%o0 + G4_OFFSET] + st %g5, [%o0 + G5_OFFSET] ! save the global registers std %g6, [%o0 + G6_OFFSET] std %l0, [%o0 + L0_OFFSET] ! save the local registers @@ -185,8 +184,7 @@ done_flushing: nop nop - ldd [%o1 + G2_OFFSET], %g2 ! restore the global registers - ldd [%o1 + G4_OFFSET], %g4 + ld [%o1 + G5_OFFSET], %g5 ! restore the global registers ldd [%o1 + G6_OFFSET], %g6 ! Load thread specific ISR dispatch prevention flag |