From b2ec2d15971503466e1debf596dc84b6af0f9b13 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Tue, 22 Apr 2014 07:46:56 +0200 Subject: sparc: Optimize context switch The registers g2 through g4 are reserved for applications. GCC uses them as volatile registers by default. So they are treated like volatile registers in RTEMS as well. --- c/src/lib/libbsp/sparc/shared/irq_asm.S | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'c/src/lib/libbsp/sparc/shared/irq_asm.S') diff --git a/c/src/lib/libbsp/sparc/shared/irq_asm.S b/c/src/lib/libbsp/sparc/shared/irq_asm.S index fc4c0be6d8..fd8269f0ce 100644 --- a/c/src/lib/libbsp/sparc/shared/irq_asm.S +++ b/c/src/lib/libbsp/sparc/shared/irq_asm.S @@ -52,8 +52,7 @@ .align 4 PUBLIC(_CPU_Context_switch) SYM(_CPU_Context_switch): - std %g2, [%o0 + G2_OFFSET] ! save the global registers - std %g4, [%o0 + G4_OFFSET] + st %g5, [%o0 + G5_OFFSET] ! save the global registers std %g6, [%o0 + G6_OFFSET] std %l0, [%o0 + L0_OFFSET] ! save the local registers @@ -185,8 +184,7 @@ done_flushing: nop nop - ldd [%o1 + G2_OFFSET], %g2 ! restore the global registers - ldd [%o1 + G4_OFFSET], %g4 + ld [%o1 + G5_OFFSET], %g5 ! restore the global registers ldd [%o1 + G6_OFFSET], %g6 ! Load thread specific ISR dispatch prevention flag -- cgit v1.2.3