LEON3: new Console driver, APBUART driver using Driver Manager

This patch reimplements the console driver of the LEON3 BSP, it
has split up the console driver in two parts: Console driver and
UART driver. Before the only UART supported was APBUART and only
on-chip APBUARTs found during startup. However splitting the
driver in two allows any UART interface to reuse the termios
attach code of the console driver, pratically this has always
been a problem when discovering APBUARTs after startup for
example the PCI board GR-RASTA-IO has APBUARTs and must wait
until after PCI has been setup.

Since the only current driver that supports the new console
driver uses the Driver Manager, the new console driver is
only enabled when Driver Manager is initialized during startup.

The new APBUART driver supports:
 * polling mode
 * interrupt mode
 * task-driven mode
 * set UART attributes
 * read UART attributes (system console inherit settings from
   boot loader)
 * Driver manager for finding/initialization of the hardware

1 files changed, 37 insertions, 0 deletions

diff --git a/c/src/lib/libbsp/sparc/leon3/include/leon.h b/c/src/lib/libbsp/sparc/leon3/include/leon.h
index 6057c42f4b..8d7a03a3ac 100644
--- a/c/src/lib/libbsp/sparc/leon3/include/leon.h
+++ b/c/src/lib/libbsp/sparc/leon3/include/leon.h
@@ -87,6 +87,43 @@ extern "C" {
                                               /* 0 = no function */
 
 /*
+ *  The following defines the bits in the UART Control Registers.
+ */
+
+#define LEON_REG_UART_CONTROL_RTD  0x000000FF /* RX/TX data */
+
+/*
+ *  The following defines the bits in the LEON UART Status Register.
+ */
+
+#define LEON_REG_UART_STATUS_DR   0x00000001 /* Data Ready */
+#define LEON_REG_UART_STATUS_TSE  0x00000002 /* TX Send Register Empty */
+#define LEON_REG_UART_STATUS_THE  0x00000004 /* TX Hold Register Empty */
+#define LEON_REG_UART_STATUS_BR   0x00000008 /* Break Error */
+#define LEON_REG_UART_STATUS_OE   0x00000010 /* RX Overrun Error */
+#define LEON_REG_UART_STATUS_PE   0x00000020 /* RX Parity Error */
+#define LEON_REG_UART_STATUS_FE   0x00000040 /* RX Framing Error */
+#define LEON_REG_UART_STATUS_TF   0x00000200 /* FIFO Full */
+#define LEON_REG_UART_STATUS_ERR  0x00000078 /* Error Mask */
+
+/*
+ *  The following defines the bits in the LEON UART Control Register.
+ */
+
+#define LEON_REG_UART_CTRL_RE     0x00000001 /* Receiver enable */
+#define LEON_REG_UART_CTRL_TE     0x00000002 /* Transmitter enable */
+#define LEON_REG_UART_CTRL_RI     0x00000004 /* Receiver interrupt enable */
+#define LEON_REG_UART_CTRL_TI     0x00000008 /* Transmitter interrupt enable */
+#define LEON_REG_UART_CTRL_PS     0x00000010 /* Parity select */
+#define LEON_REG_UART_CTRL_PE     0x00000020 /* Parity enable */
+#define LEON_REG_UART_CTRL_FL     0x00000040 /* Flow control enable */
+#define LEON_REG_UART_CTRL_LB     0x00000080 /* Loop Back enable */
+#define LEON_REG_UART_CTRL_DB     0x00000800 /* Debug FIFO enable */
+#define LEON_REG_UART_CTRL_SI     0x00004000 /* TX shift register empty IRQ enable */
+#define LEON_REG_UART_CTRL_FA     0x80000000 /* FIFO Available */
+#define LEON_REG_UART_CTRL_FA_BIT 31
+
+/*
  *  The following defines the bits in the LEON Cache Control Register.
  */
 #define LEON3_REG_CACHE_CTRL_FI      0x00200000 /* Flush instruction cache */