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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-02-24 10:48:13 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-02-28 09:06:19 +0100 |
| commit | 64f4ac28a612880a0dfb723e19bff7f06519be31 (patch) | |
| tree | d5e1f57692f88eb97b2ef35b2165f8b0e5fe544f /c/src/lib/libbsp/sparc/leon3/Makefile.am | |
| parent | bsp/leon3: Add and use cache register functions (diff) | |
| download | rtems-64f4ac28a612880a0dfb723e19bff7f06519be31.tar.bz2 | |
bsp/leon3: Add new cache manager implementation
The previous implementation used an instruction cache line size of 0,
this is a bogus value. Use a instruction cache line size of 64 since
the L2 cache may have a line size of 32 or 64. A greater value should
cause no harm.
Use a FLUSH operation for _CPU_cache_invalidate_instruction_range().
This is a preperation step to support the L2 cache.
Diffstat (limited to 'c/src/lib/libbsp/sparc/leon3/Makefile.am')
| -rw-r--r-- | c/src/lib/libbsp/sparc/leon3/Makefile.am | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/c/src/lib/libbsp/sparc/leon3/Makefile.am b/c/src/lib/libbsp/sparc/leon3/Makefile.am index a66da9be82..3c87e181ec 100644 --- a/c/src/lib/libbsp/sparc/leon3/Makefile.am +++ b/c/src/lib/libbsp/sparc/leon3/Makefile.am @@ -117,6 +117,11 @@ libbsp_a_SOURCES += ../../sparc/shared/i2c/i2cmst.c # timer libbsp_a_SOURCES += timer/timer.c +# Cache +libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c +libbsp_a_SOURCES += include/cache_.h +libbsp_a_CPPFLAGS = -I$(srcdir)/include + if HAS_SMP libbsp_a_SOURCES += smp/getcpuid.c libbsp_a_SOURCES += smp/smp_leon3.c @@ -155,7 +160,6 @@ endif libbsp_a_LIBADD = \ ../../../libcpu/@RTEMS_CPU@/access.rel \ - ../../../libcpu/@RTEMS_CPU@/cache.rel \ ../../../libcpu/@RTEMS_CPU@/reg_win.rel \ ../../../libcpu/@RTEMS_CPU@/syscall.rel |