bsps/sparc: Make lines in SPARC BSPs adhere to 80 character limit.

1 files changed, 117 insertions, 64 deletions

diff --git a/c/src/lib/libbsp/sparc/leon2/pci/pci.c b/c/src/lib/libbsp/sparc/leon2/pci/pci.c
index fcc63df567..f34a173a7f 100644
--- a/c/src/lib/libbsp/sparc/leon2/pci/pci.c
+++ b/c/src/lib/libbsp/sparc/leon2/pci/pci.c
@@ -44,14 +44,14 @@
 
 /* allow for overriding these definitions */
 #ifndef PCI_CONFIG_ADDR
-#define PCI_CONFIG_ADDR			0xcf8
+#define PCI_CONFIG_ADDR      0xcf8
 #endif
 #ifndef PCI_CONFIG_DATA
-#define PCI_CONFIG_DATA			0xcfc
+#define PCI_CONFIG_DATA      0xcfc
 #endif
 
 /* define a shortcut */
-#define pci	BSP_pci_configuration
+#define pci  BSP_pci_configuration
 
 /*
  * Bit encode for PCI_CONFIG_HEADER_TYPE register
@@ -59,34 +59,62 @@
 unsigned char ucMaxPCIBus;
 
 typedef struct {
-    volatile unsigned int pciid1;        /* 0x80000100 - PCI Device identification register 1         */
-    volatile unsigned int pcisc;         /* 0x80000104 - PCI Status & Command                         */
-    volatile unsigned int pciid2;        /* 0x80000108 - PCI Device identification register 2         */
-    volatile unsigned int pcibhlc;       /* 0x8000010c - BIST, Header type, Cache line size register  */
-    volatile unsigned int mbar1;         /* 0x80000110 - Memory Base Address Register 1               */
-    volatile unsigned int mbar2;         /* 0x80000114 - Memory Base Address Register 2               */
-    volatile unsigned int iobar3;        /* 0x80000118 - IO Base Address Register 3                   */
-    volatile unsigned int dummy1[4];     /* 0x8000011c - 0x80000128                                   */
-    volatile unsigned int pcisid;        /* 0x8000012c - Subsystem identification register            */
-    volatile unsigned int dummy2;        /* 0x80000130                                                */
-    volatile unsigned int pcicp;         /* 0x80000134 - PCI capabilities pointer register            */
-    volatile unsigned int dummy3;        /* 0x80000138                                                */
-    volatile unsigned int pcili;         /* 0x8000013c - PCI latency interrupt register               */
-    volatile unsigned int pcirt;         /* 0x80000140 - PCI retry, trdy config                       */
-    volatile unsigned int pcicw;         /* 0x80000144 - PCI configuration write register             */
-    volatile unsigned int pcisa;         /* 0x80000148 - PCI Initiator Start Address                  */
-    volatile unsigned int pciiw;         /* 0x8000014c - PCI Initiator Write Register                 */
-    volatile unsigned int pcidma;        /* 0x80000150 - PCI DMA configuration register               */
-    volatile unsigned int pciis;         /* 0x80000154 - PCI Initiator Status Register                */
-    volatile unsigned int pciic;         /* 0x80000158 - PCI Initiator Configuration                  */
-    volatile unsigned int pcitpa;        /* 0x8000015c - PCI Target Page Address Register             */
-    volatile unsigned int pcitsc;        /* 0x80000160 - PCI Target Status-Command Register           */
-    volatile unsigned int pciite;        /* 0x80000164 - PCI Interrupt Enable Register                */
-    volatile unsigned int pciitp;        /* 0x80000168 - PCI Interrupt Pending Register               */
-    volatile unsigned int pciitf;        /* 0x8000016c - PCI Interrupt Force Register                 */
-    volatile unsigned int pcid;          /* 0x80000170 - PCI Data Register                            */
-    volatile unsigned int pcibe;         /* 0x80000174 - PCI Burst End Register                       */
-    volatile unsigned int pcidmaa;       /* 0x80000178 - PCI DMA Address Register                     */
+  /* 0x80000100 - PCI Device identification register 1         */
+    volatile unsigned int pciid1;
+    /* 0x80000104 - PCI Status & Command                         */
+    volatile unsigned int pcisc;
+    /* 0x80000108 - PCI Device identification register 2         */
+    volatile unsigned int pciid2;
+    /* 0x8000010c - BIST, Header type, Cache line size register  */
+    volatile unsigned int pcibhlc;
+    /* 0x80000110 - Memory Base Address Register 1               */
+    volatile unsigned int mbar1;
+    /* 0x80000114 - Memory Base Address Register 2               */
+    volatile unsigned int mbar2;
+    /* 0x80000118 - IO Base Address Register 3                   */
+    volatile unsigned int iobar3;
+    /* 0x8000011c - 0x80000128                                   */
+    volatile unsigned int dummy1[4];
+    /* 0x8000012c - Subsystem identification register            */
+    volatile unsigned int pcisid;
+    /* 0x80000130                                                */
+    volatile unsigned int dummy2;
+    /* 0x80000134 - PCI capabilities pointer register            */
+    volatile unsigned int pcicp;
+    /* 0x80000138                                                */
+    volatile unsigned int dummy3;
+    /* 0x8000013c - PCI latency interrupt register               */
+    volatile unsigned int pcili;
+    /* 0x80000140 - PCI retry, trdy config                       */
+    volatile unsigned int pcirt;
+    /* 0x80000144 - PCI configuration write register             */
+    volatile unsigned int pcicw;
+    /* 0x80000148 - PCI Initiator Start Address                  */
+    volatile unsigned int pcisa;
+    /* 0x8000014c - PCI Initiator Write Register                 */
+    volatile unsigned int pciiw;
+    /* 0x80000150 - PCI DMA configuration register               */
+    volatile unsigned int pcidma;
+    /* 0x80000154 - PCI Initiator Status Register                */
+    volatile unsigned int pciis;
+    /* 0x80000158 - PCI Initiator Configuration                  */
+    volatile unsigned int pciic;
+    /* 0x8000015c - PCI Target Page Address Register             */
+    volatile unsigned int pcitpa;
+    /* 0x80000160 - PCI Target Status-Command Register           */
+    volatile unsigned int pcitsc;
+    /* 0x80000164 - PCI Interrupt Enable Register                */
+    volatile unsigned int pciite;
+    /* 0x80000168 - PCI Interrupt Pending Register               */
+    volatile unsigned int pciitp;
+    /* 0x8000016c - PCI Interrupt Force Register                 */
+    volatile unsigned int pciitf;
+    /* 0x80000170 - PCI Data Register                            */
+    volatile unsigned int pcid;
+    /* 0x80000174 - PCI Burst End Register                       */
+    volatile unsigned int pcibe;
+    /* 0x80000178 - PCI DMA Address Register                     */
+    volatile unsigned int pcidmaa;
 } AT697_PCI_Map;
 
 AT697_PCI_Map *pcic = (AT697_PCI_Map *) 0x80000100;
@@ -107,7 +135,8 @@ struct pci_res {
  */
 
 static int
-BSP_pci_read_config_dword(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned int *val) {
+BSP_pci_read_config_dword(unsigned char bus, unsigned char slot,
+    unsigned char function, unsigned char offset, unsigned int *val) {
 
     volatile unsigned int data;
 
@@ -131,14 +160,17 @@ BSP_pci_read_config_dword(unsigned char bus, unsigned char slot, unsigned char f
     else
         *val = data;
 
-    DBG("pci_read - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n", bus, slot, function, offset,  (1<<(11+slot) ) | ((function & 7)<<8) |  (offset&0x3f), *val);
+    DBG("pci_read - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n",
+        bus, slot, function, offset,
+        (1<<(11+slot) ) | ((function & 7)<<8) |  (offset&0x3f), *val);
 
     return PCIBIOS_SUCCESSFUL;
 }
 
 
 static int
-BSP_pci_read_config_word(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned short *val) {
+BSP_pci_read_config_word(unsigned char bus, unsigned char slot,
+    unsigned char function, unsigned char offset, unsigned short *val) {
     unsigned int v;
 
     if (offset & 1) return PCIBIOS_BAD_REGISTER_NUMBER;
@@ -151,7 +183,8 @@ BSP_pci_read_config_word(unsigned char bus, unsigned char slot, unsigned char fu
 
 
 static int
-BSP_pci_read_config_byte(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned char *val) {
+BSP_pci_read_config_byte(unsigned char bus, unsigned char slot,
+    unsigned char function, unsigned char offset, unsigned char *val) {
     unsigned int v;
 
     pci_read_config_dword(bus, slot, function, offset&~3, &v);
@@ -163,7 +196,8 @@ BSP_pci_read_config_byte(unsigned char bus, unsigned char slot, unsigned char fu
 
 
 static int
-BSP_pci_write_config_dword(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned int val) {
+BSP_pci_write_config_dword(unsigned char bus, unsigned char slot,
+    unsigned char function, unsigned char offset, unsigned int val) {
 
     if (offset & 3) return PCIBIOS_BAD_REGISTER_NUMBER;
 
@@ -182,14 +216,17 @@ BSP_pci_write_config_dword(unsigned char bus, unsigned char slot, unsigned char
 
     pcic->pciitp = 0xff; /* clear interrupts */
 
-/*    DBG("pci write - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n", bus, slot, function, offset, (1<<(11+slot) ) | ((function & 7)<<8) |  (offset&0x3f), val); */
+/*  DBG("pci write - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n",
+    bus, slot, function, offset,
+    (1<<(11+slot) ) | ((function & 7)<<8) |  (offset&0x3f), val); */
 
     return PCIBIOS_SUCCESSFUL;
 }
 
 
 static int
-BSP_pci_write_config_word(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned short val) {
+BSP_pci_write_config_word(unsigned char bus, unsigned char slot,
+    unsigned char function, unsigned char offset, unsigned short val) {
     unsigned int v;
 
     if (offset & 1) return PCIBIOS_BAD_REGISTER_NUMBER;
@@ -203,7 +240,8 @@ BSP_pci_write_config_word(unsigned char bus, unsigned char slot, unsigned char f
 
 
 static int
-BSP_pci_write_config_byte(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned char val) {
+BSP_pci_write_config_byte(unsigned char bus, unsigned char slot,
+    unsigned char function, unsigned char offset, unsigned char val) {
     unsigned int v;
 
     pci_read_config_dword(bus, slot, function, offset&~3, &v);
@@ -236,7 +274,8 @@ static void init_at697_pci(void) {
     /* Reset */
     pcic->pciic = 0xffffffff;
 
-    /* Map system RAM at pci address 0x40000000 and system SDRAM to pci address 0x60000000  */
+    /* Map system RAM at pci address 0x40000000
+       and system SDRAM to pci address 0x60000000  */
     pcic->mbar1  = 0x40000000;
     pcic->mbar2  = 0x60000000;
     pcic->pcitpa = 0x40006000;
@@ -247,7 +286,8 @@ static void init_at697_pci(void) {
     /* Set latency timer to 64 */
     pcic->pcibhlc = 0x00004000;
 
-    /* Set Inititator configuration so that AHB slave accesses generate memory read/write commands */
+    /* Set Inititator configuration so that AHB slave accesses
+       generate memory read/write commands */
     pcic->pciic = 0x41;
 
     pcic->pciite = 0xff;
@@ -383,19 +423,23 @@ int dma_from_pci(unsigned int addr, unsigned int paddr, unsigned int len) {
     return 0;
 }
 
-void pci_mem_enable(unsigned char bus, unsigned char slot, unsigned char function) {
+void pci_mem_enable(unsigned char bus, unsigned char slot,
+    unsigned char function) {
     unsigned int data;
 
     pci_read_config_dword(0, slot, function, PCI_COMMAND, &data);
-    pci_write_config_dword(0, slot, function, PCI_COMMAND, data | PCI_COMMAND_MEMORY);
+    pci_write_config_dword(0, slot, function, PCI_COMMAND,
+        data | PCI_COMMAND_MEMORY);
 
 }
 
-void pci_master_enable(unsigned char bus, unsigned char slot, unsigned char function) {
+void pci_master_enable(unsigned char bus, unsigned char slot,
+    unsigned char function) {
     unsigned int data;
 
     pci_read_config_dword(0, slot, function, PCI_COMMAND, &data);
-    pci_write_config_dword(0, slot, function, PCI_COMMAND, data | PCI_COMMAND_MASTER);
+    pci_write_config_dword(0, slot, function, PCI_COMMAND,
+        data | PCI_COMMAND_MASTER);
 
 }
 
@@ -409,18 +453,19 @@ static inline void swap_res(struct pci_res **p1, struct pci_res **p2) {
 
 /* pci_allocate_resources
  *
- * This function scans the bus and assigns PCI addresses to all devices. It handles both
- * single function and multi function devices. All allocated devices are enabled and
- * latency timers are set to 40.
+ * This function scans the bus and assigns PCI addresses to all devices. It
+ * handles both single function and multi function devices. All allocated
+ * devices are enabled and latency timers are set to 40.
  *
- * NOTE that it only allocates PCI memory space devices. IO spaces are not enabled.
- * Also, it does not handle pci-pci bridges. They are left disabled.
+ * NOTE that it only allocates PCI memory space devices. IO spaces are
+ * not enabled. Also, it does not handle pci-pci bridges. They are left
+ * disabled.
  *
- *
-*/
+ */
 static void pci_allocate_resources(void) {
 
-    unsigned int slot, numfuncs, func, id, pos, size, tmp, i, swapped, addr, dev, fn;
+    unsigned int slot, numfuncs, func, id, pos, size, tmp;
+    unsigned int i, swapped, addr, dev, fn;
     unsigned char header;
     struct pci_res **res;
 
@@ -445,7 +490,7 @@ static void pci_allocate_resources(void) {
 
         pci_read_config_byte(0, slot, 0, PCI_HEADER_TYPE, &header);
 
-        if(header & PCI_HEADER_TYPE_MULTI_FUNCTION)	{
+        if(header & PCI_HEADER_TYPE_MULTI_FUNCTION)  {
             numfuncs = PCI_MAX_FUNCTIONS;
         }
         else {
@@ -466,11 +511,14 @@ static void pci_allocate_resources(void) {
             }
 
             for (pos = 0; pos < 6; pos++) {
-                pci_write_config_dword(0, slot, func, PCI_BASE_ADDRESS_0 + (pos<<2), 0xffffffff);
-                pci_read_config_dword(0, slot, func, PCI_BASE_ADDRESS_0 + (pos<<2), &size);
+                pci_write_config_dword(0, slot, func,
+                    PCI_BASE_ADDRESS_0 + (pos<<2), 0xffffffff);
+                pci_read_config_dword(0, slot, func,
+                    PCI_BASE_ADDRESS_0 + (pos<<2), &size);
 
                 if (size == 0 || size == 0xffffffff || (size & 0xff) != 0) {
-                    pci_write_config_dword(0, slot, func, PCI_BASE_ADDRESS_0 + (pos<<2), 0);
+                    pci_write_config_dword(0, slot, func,
+                        PCI_BASE_ADDRESS_0 + (pos<<2), 0);
                     continue;
                 }
 
@@ -479,7 +527,8 @@ static void pci_allocate_resources(void) {
                     res[slot*8*6+func*6+pos]->devfn = slot*8 + func;
                     res[slot*8*6+func*6+pos]->bar   = pos;
 
-                    DBG("Slot: %d, function: %d, bar%d size: %x\n", slot, func, pos, ~size+1);
+                    DBG("Slot: %d, function: %d, bar%d size: %x\n",
+                        slot, func, pos, ~size+1);
                 }
             }
         }
@@ -516,8 +565,10 @@ static void pci_allocate_resources(void) {
         dev = res[i]->devfn >> 3;
         fn  = res[i]->devfn & 7;
 
-        DBG("Assigning PCI addr %x to device %d, function %d, bar %d\n", addr, dev, fn, res[i]->bar);
-        pci_write_config_dword(0, dev, fn, PCI_BASE_ADDRESS_0+res[i]->bar*4, addr);
+        DBG("Assigning PCI addr %x to device %d, function %d, bar %d\n",
+            addr, dev, fn, res[i]->bar);
+        pci_write_config_dword(0, dev, fn,
+            PCI_BASE_ADDRESS_0+res[i]->bar*4, addr);
         addr += res[i]->size;
 
         /* Set latency timer to 64 */
@@ -538,7 +589,7 @@ done:
 
         pci_read_config_byte(0, slot, 0, PCI_HEADER_TYPE, &header);
 
-        if(header & PCI_HEADER_TYPE_MULTI_FUNCTION)	{
+        if(header & PCI_HEADER_TYPE_MULTI_FUNCTION)  {
             numfuncs = PCI_MAX_FUNCTIONS;
         }
         else {
@@ -555,10 +606,12 @@ done:
 
                 if (id == PCI_INVALID_VENDORDEVICEID || id == 0) continue;
 
-                printk("\nSlot %d function: %d\nVendor id: 0x%x, device id: 0x%x\n", slot, func, id & 0xffff, id>>16);
+                printk("\nSlot %d function: %d\nVendor id: 0x%x, "
+                    "device id: 0x%x\n", slot, func, id & 0xffff, id>>16);
 
                 for (pos = 0; pos < 6; pos++) {
-                    pci_read_config_dword(0, slot, func, PCI_BASE_ADDRESS_0 + pos*4, &tmp);
+                    pci_read_config_dword(0, slot, func,
+                        PCI_BASE_ADDRESS_0 + pos*4, &tmp);
 
                     if (tmp != 0 && tmp != 0xffffffff && (tmp & 0xff) == 0) {
 
@@ -620,7 +673,7 @@ int init_pci(void)
                                    0,
                                    PCI_HEADER_TYPE,
                                    &ucHeader);
-        if(ucHeader&PCI_HEADER_TYPE_MULTI_FUNCTION)	{
+        if(ucHeader&PCI_HEADER_TYPE_MULTI_FUNCTION)  {
             ucNumFuncs=PCI_MAX_FUNCTIONS;
         }
         else {