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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-04-25 15:06:08 +0200 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-04-26 07:17:57 +0200 |
commit | eb36d1198cdf9dc1e2f776ef6e1e38755f6d13c5 (patch) | |
tree | 14177ad7a58c06a3c537d1e55dae7bc369a1a4b9 /c/src/lib/libbsp/sparc/erc32 | |
parent | bsps: Remove unmaintained times files (diff) | |
download | rtems-eb36d1198cdf9dc1e2f776ef6e1e38755f6d13c5.tar.bz2 |
bsps: Move documentation, etc. files to bsps
This patch is a part of the BSP source reorganization.
Update #3285.
Diffstat (limited to 'c/src/lib/libbsp/sparc/erc32')
-rw-r--r-- | c/src/lib/libbsp/sparc/erc32/README | 78 |
1 files changed, 0 insertions, 78 deletions
diff --git a/c/src/lib/libbsp/sparc/erc32/README b/c/src/lib/libbsp/sparc/erc32/README deleted file mode 100644 index 248f14f26a..0000000000 --- a/c/src/lib/libbsp/sparc/erc32/README +++ /dev/null @@ -1,78 +0,0 @@ -# -# Description of SIS as related to this BSP -# - -BSP NAME: sis -BOARD: any based on the European Space Agency's ERC32 -BUS: N/A -CPU FAMILY: sparc -CPU: ERC32 (SPARC V7 + on-CPU peripherals) - based on Cypress 601/602 -COPROCESSORS: on-chip 602 compatible FPU -MODE: 32 bit mode - -DEBUG MONITOR: none - -PERIPHERALS -=========== -TIMERS: - NAME: General Purpose Timer - RESOLUTION: 50 nanoseconds - 12.8 microseconds - NAME: Real Time Clock Timer - RESOLUTION: 50 nanoseconds - 3.2768 milliseconds - NAME: Watchdog Timer - RESOLUTION: XXX -SERIAL PORTS: 2 using on-chip UART -REAL-TIME CLOCK: none -DMA: on-chip -VIDEO: none -SCSI: none -NETWORKING: none - -DRIVER INFORMATION -================== -CLOCK DRIVER: ERC32 internal Real Time Clock Timer -IOSUPP DRIVER: N/A -SHMSUPP: N/A -TIMER DRIVER: ERC32 internal General Purpose Timer -CONSOLE DRIVER: ERC32 internal UART - -STDIO -===== -PORT: Channel A -ELECTRICAL: na since using simulator -BAUD: na -BITS PER CHARACTER: na -PARITY: na -STOP BITS: na - -Notes -===== - -ERC32 BSP only supports single processor operations. - -A nice feature of this BSP is that the RAM and PROM size are set in the -linkcmds file and the startup code programs the Memory Configuration -Register based on those sizes. - -The Watchdog Timer is disabled. - -This code was developed and tested entirely using the SPARC Instruction -Simulator (SIS) for the ERC32. All tests were known to run correctly -against sis v1.7. - - -Memory Map -========== - -0x00000000 - 0x00000000 + _PROM_SIZE code and initialized data -0x01f80000 on chip peripherals -0x00000000 - 0x02000000 + _RAM_SIZE destination for initialized data - BSS (i.e. unitialized data) - C Heap (i.e. malloc area) - RTEMS Workspace - -The C heap is assigned all memory between the end of the BSS and the -RTEMS Workspace. The size of the RTEMS Workspace is based on that -specified in the application's configuration table. - |