diff options
| author | Daniel Hellstrom <daniel@gaisler.com> | 2012-04-06 05:05:07 -0500 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@oarcorp.com> | 2012-04-06 08:17:58 -0500 |
| commit | 95518e59bd6dda4bda22f4f02a22613b67e39400 (patch) | |
| tree | 6cfb21ea5492179731efad5a3a91813eb0f76df3 /c/src/lib/libbsp/sparc/erc32/include/erc32.h | |
| parent | LEON3: console use register pointers instead of UART indexes (diff) | |
| download | rtems-95518e59bd6dda4bda22f4f02a22613b67e39400.tar.bz2 | |
SPARC BSPs: implemented shared-irq using libbsp/shared layer
The implementation use IRQ number instead of vector number since
some IRQs does not have a unique vector, for example the extended
interrupts all enter the same trap vector entry.
Added support for the LEON3 extended interrupt controller when using
the shared IRQ layer.
ERC32 patches untested.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
Regenerate
Diffstat (limited to 'c/src/lib/libbsp/sparc/erc32/include/erc32.h')
| -rw-r--r-- | c/src/lib/libbsp/sparc/erc32/include/erc32.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/sparc/erc32/include/erc32.h b/c/src/lib/libbsp/sparc/erc32/include/erc32.h index dcc619069f..2795dcb13b 100644 --- a/c/src/lib/libbsp/sparc/erc32/include/erc32.h +++ b/c/src/lib/libbsp/sparc/erc32/include/erc32.h @@ -324,6 +324,11 @@ typedef struct { extern ERC32_Register_Map ERC32_MEC; +static __inline__ int bsp_irq_fixup(int irq) +{ + return irq; +} + /* * Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask, * and the Interrupt Pending Registers. @@ -396,6 +401,18 @@ extern ERC32_Register_Map ERC32_MEC; sparc_enable_interrupts( _level ); \ } while (0) +/* Make all SPARC BSPs have common macros for interrupt handling */ +#define BSP_Clear_interrupt(_source) ERC32_Clear_interrupt(_source) +#define BSP_Force_interrupt(_source) ERC32_Force_interrupt(_source) +#define BSP_Is_interrupt_pending(_source) ERC32_Is_interrupt_pending(_source) +#define BSP_Is_interrupt_masked(_source) ERC32_Is_interrupt_masked(_source) +#define BSP_Unmask_interrupt(_source) ERC32_Unmask_interrupt(_source) +#define BSP_Mask_interrupt(_source) ERC32_Mask_interrupt(_source) +#define BSP_Disable_interrupt(_source, _previous) \ + ERC32_Disable_interrupt(_source, _prev) +#define BSP_Restore_interrupt(_source, _previous) \ + ERC32_Restore_interrupt(_source, _previous) + /* * The following macros attempt to hide the fact that the General Purpose * Timer and Real Time Clock Timer share the Timer Control Register. Because |