diff options
| author | Daniel Cederman <cederman@gaisler.com> | 2014-05-08 15:42:12 +0200 |
|---|---|---|
| committer | Daniel Hellstrom <daniel@gaisler.com> | 2014-05-27 09:46:13 +0200 |
| commit | 363b1f7f021c71f3e5d81a045a43f337e8bb6734 (patch) | |
| tree | 7c8384ab3b00cf4810e760375489f5a04d5a77f5 /c/src/lib/libbsp/sparc/erc32/include/erc32.h | |
| parent | bsp/gdbarmsim: Switch to the standard arm/shared/startup. (diff) | |
| download | rtems-363b1f7f021c71f3e5d81a045a43f337e8bb6734.tar.bz2 | |
bsps/sparc: Make lines in SPARC BSPs adhere to 80 character limit.
Diffstat (limited to 'c/src/lib/libbsp/sparc/erc32/include/erc32.h')
| -rw-r--r-- | c/src/lib/libbsp/sparc/erc32/include/erc32.h | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/c/src/lib/libbsp/sparc/erc32/include/erc32.h b/c/src/lib/libbsp/sparc/erc32/include/erc32.h index 5520cdb8d1..f3eb293faa 100644 --- a/c/src/lib/libbsp/sparc/erc32/include/erc32.h +++ b/c/src/lib/libbsp/sparc/erc32/include/erc32.h @@ -257,23 +257,23 @@ typedef struct { * The following defines the bits in the Timer Control Register. */ -#define ERC32_MEC_TIMER_CONTROL_GCR 0x00000001 /* 1 = reload at 0 */ - /* 0 = stop at 0 */ -#define ERC32_MEC_TIMER_CONTROL_GCL 0x00000002 /* 1 = load and start */ - /* 0 = no function */ -#define ERC32_MEC_TIMER_CONTROL_GSE 0x00000004 /* 1 = enable counting */ - /* 0 = hold scalar and counter */ -#define ERC32_MEC_TIMER_CONTROL_GSL 0x00000008 /* 1 = load scalar and start */ - /* 0 = no function */ - -#define ERC32_MEC_TIMER_CONTROL_RTCCR 0x00000100 /* 1 = reload at 0 */ - /* 0 = stop at 0 */ -#define ERC32_MEC_TIMER_CONTROL_RTCCL 0x00000200 /* 1 = load and start */ - /* 0 = no function */ -#define ERC32_MEC_TIMER_CONTROL_RTCSE 0x00000400 /* 1 = enable counting */ - /* 0 = hold scalar and counter */ -#define ERC32_MEC_TIMER_CONTROL_RTCSL 0x00000800 /* 1 = load scalar and start */ - /* 0 = no function */ +#define ERC32_MEC_TIMER_CONTROL_GCR 0x00000001 /* 1 = reload at 0 */ + /* 0 = stop at 0 */ +#define ERC32_MEC_TIMER_CONTROL_GCL 0x00000002 /* 1 = load and start */ + /* 0 = no function */ +#define ERC32_MEC_TIMER_CONTROL_GSE 0x00000004 /* 1 = enable counting */ + /* 0 = hold scalar and counter */ +#define ERC32_MEC_TIMER_CONTROL_GSL 0x00000008 /* 1 = load scalar and start*/ + /* 0 = no function */ + +#define ERC32_MEC_TIMER_CONTROL_RTCCR 0x00000100 /* 1 = reload at 0 */ + /* 0 = stop at 0 */ +#define ERC32_MEC_TIMER_CONTROL_RTCCL 0x00000200 /* 1 = load and start */ + /* 0 = no function */ +#define ERC32_MEC_TIMER_CONTROL_RTCSE 0x00000400 /* 1 = enable counting */ + /* 0 = hold scalar and counter */ +#define ERC32_MEC_TIMER_CONTROL_RTCSL 0x00000800 /* 1 = load scalar and start*/ + /* 0 = no function */ /* * The following defines the bits in the UART Control Registers. |