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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2009-07-06 15:45:45 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2009-07-06 15:45:45 +0000 |
| commit | 45d3b3304e557be177eff40aa1dae484b6544079 (patch) | |
| tree | afaf38f5142af30c4f1bff65741374dc095748a6 /c/src/lib/libbsp/shared/setvec.c | |
| parent | 2009-07-03 Josh Switnicki <josh.switnicki@utoronto.ca> (diff) | |
| download | rtems-45d3b3304e557be177eff40aa1dae484b6544079.tar.bz2 | |
2009-07-06 Joel Sherrill <joel.sherrill@oarcorp.com>
* setvec.c: Add CVS Id.
Diffstat (limited to 'c/src/lib/libbsp/shared/setvec.c')
| -rw-r--r-- | c/src/lib/libbsp/shared/setvec.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/c/src/lib/libbsp/shared/setvec.c b/c/src/lib/libbsp/shared/setvec.c index 826f13b399..dda3c91b53 100644 --- a/c/src/lib/libbsp/shared/setvec.c +++ b/c/src/lib/libbsp/shared/setvec.c @@ -1,6 +1,9 @@ -/* set_vector - * - * This routine installs an interrupt vector on the SPARC simulator. +/* + * This routine installs an interrupt vector on CPU architectures + * using the Simple Vectored Interrupt Model. This is the shared + * version which does nothing BSP specific. A BSP specific version + * will be needed if you need to enable an interrupt source via + * some register. * * INPUT PARAMETERS: * handler - interrupt handler entry point @@ -13,13 +16,14 @@ * RETURNS: * address of previous interrupt handler * - * COPYRIGHT (c) 1989-1999. + * COPYRIGHT (c) 1989-2009. * On-Line Applications Research Corporation (OAR). * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. * + * $Id$ */ #include <bsp.h> |