bsp/gensh2: Move libcpu files to BSP

Update #3254.

16 files changed, 3043 insertions, 7 deletions

diff --git a/c/src/lib/libbsp/sh/gensh2/Makefile.am b/c/src/lib/libbsp/sh/gensh2/Makefile.am
index dd8fb2d752..2ca4e76b05 100644
--- a/c/src/lib/libbsp/sh/gensh2/Makefile.am
+++ b/c/src/lib/libbsp/sh/gensh2/Makefile.am
@@ -2,6 +2,8 @@ ACLOCAL_AMFLAGS = -I ../../../../aclocal
 
 include $(top_srcdir)/../../../../automake/compile.am
 
+include_shdir = $(includedir)/sh
+include_rtems_scoredir = $(includedir)/rtems/score
 include_bspdir = $(includedir)/bsp
 
 dist_project_lib_DATA = bsp_specs
@@ -9,6 +11,15 @@ dist_project_lib_DATA = bsp_specs
 include_HEADERS = include/bsp.h
 include_HEADERS += include/tm27.h
 
+include_sh_HEADERS = include/sh/io_types.h
+include_sh_HEADERS += include/sh/sci.h
+include_sh_HEADERS += include/sh/sh7_pfc.h
+include_sh_HEADERS += include/sh/sh7_sci.h
+include_sh_HEADERS += include/sh/sci_termios.h
+
+include_rtems_score_HEADERS = include/rtems/score/ispsh7045.h
+include_rtems_score_HEADERS += include/rtems/score/iosh7045.h
+
 nodist_include_HEADERS = include/bspopts.h
 nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
 DISTCLEANFILES = include/bspopts.h
@@ -41,19 +52,19 @@ libbsp_a_SOURCES += startup/hw_init.c \
     ../../shared/gnatinstallhandler.c ../../shared/bspclean.c \
     ../shared/bsphwinit.c
 libbsp_a_SOURCES += ../../shared/bspreset.c
+libbsp_a_SOURCES += clock/ckinit.c
+libbsp_a_SOURCES += startup/cpu_asm.c startup/ispsh7045.c
+libbsp_a_SOURCES += timer/timer.c
 # scitab
 libbsp_a_SOURCES += scitab.c
 # console
 libbsp_a_SOURCES += ../../sh/shared/console.c console/config.c
+libbsp_a_SOURCES += console/sci.c
+libbsp_a_SOURCES += console/sci_termios.c
 # debugio
 libbsp_a_SOURCES += ../../shared/dummy_printk_support.c
 
-libbsp_a_LIBADD = \
-    ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/clock.rel \
-    ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/timer.rel \
-    ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/sci.rel \
-    ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/score.rel \
-    ../../../libcpu/@RTEMS_CPU@/cache.rel
+libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/cache.rel
 
 include $(srcdir)/preinstall.am
 include $(top_srcdir)/../../../../automake/local.am
diff --git a/c/src/lib/libbsp/sh/gensh2/clock/ckinit.c b/c/src/lib/libbsp/sh/gensh2/clock/ckinit.c
new file mode 100644
index 0000000000..5120b594eb
--- /dev/null
+++ b/c/src/lib/libbsp/sh/gensh2/clock/ckinit.c
@@ -0,0 +1,243 @@
+/*
+ *  This file contains the clock driver the Hitachi SH 704X
+ */
+
+/*
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *      Modified to reflect registers of sh7045 processor:
+ *      John M. Mills (jmills@tga.com)
+ *      TGA Technologies, Inc.
+ *      100 Pinnacle Way, Suite 140
+ *      Norcross, GA 30071 U.S.A.
+ *      August, 1999
+ *
+ *	This modified file may be copied and distributed in accordance
+ *	the above-referenced license. It is provided for critique and
+ *	developmental purposes without any warranty nor representation
+ *	by the authors or by TGA Technologies.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+
+#include <stdlib.h>
+
+#include <rtems/clockdrv.h>
+#include <rtems/score/sh_io.h>
+#include <rtems/score/sh.h>
+#include <rtems/score/ispsh7045.h>
+#include <rtems/score/iosh7045.h>
+
+extern uint32_t bsp_clicks_per_second;
+
+#define _MTU_COUNTER0_MICROSECOND (Clock_MHZ/16)
+
+#ifndef CLOCKPRIO
+#define CLOCKPRIO 10
+#endif
+
+#define MTU0_STARTMASK 	0xfe
+#define MTU0_SYNCMASK 	0xfe
+#define MTU0_MODEMASK 	0xc0
+#define MTU0_TCRMASK 	0x22 /* bit 7 also used, vs 703x */
+#define MTU0_STAT_MASK 	0xc0
+#define MTU0_IRQMASK 	0xfe
+#define MTU0_TIERMASK 	0x01
+#define IPRC_MTU0_MASK 	0xff0f
+#define MTU0_TIORVAL 	0x08
+
+/*
+ *  The interrupt vector number associated with the clock tick device
+ *  driver.
+ */
+
+#define CLOCK_VECTOR MTUA0_ISP_V
+
+/*
+ *  Clock_driver_ticks is a monotonically increasing counter of the
+ *  number of clock ticks since the driver was initialized.
+ */
+volatile uint32_t   Clock_driver_ticks;
+
+static rtems_isr Clock_isr( rtems_vector_number vector );
+static uint32_t   Clock_MHZ ;
+
+/*
+ *  Clock_isrs is the number of clock ISRs until the next invocation of
+ *  the RTEMS clock tick routine.  The clock tick device driver
+ *  gets an interrupt once a millisecond and counts down until the
+ *  length of time between the user configured microseconds per tick
+ *  has passed.
+ */
+uint32_t   Clock_isrs;              /* ISRs until next tick */
+static uint32_t   Clock_isrs_const;        /* only calculated once */
+
+/*
+ *  The previous ISR on this clock tick interrupt vector.
+ */
+rtems_isr_entry  Old_ticker;
+
+/*
+ *  Isr Handler
+ */
+static rtems_isr Clock_isr(
+  rtems_vector_number vector
+)
+{
+  /*
+   * bump the number of clock driver ticks since initialization
+   *
+
+   * determine if it is time to announce the passing of tick as configured
+   * to RTEMS through the rtems_clock_tick directive
+   *
+   * perform any timer dependent tasks
+   */
+  uint8_t   temp;
+
+  /* reset the flags of the status register */
+  temp = read8( MTU_TSR0) & MTU0_STAT_MASK;
+  write8( temp, MTU_TSR0);
+
+  Clock_driver_ticks++ ;
+
+  if( Clock_isrs == 1)
+    {
+      rtems_clock_tick();
+      Clock_isrs = Clock_isrs_const;
+    }
+  else
+    {
+      Clock_isrs-- ;
+    }
+}
+
+/*
+ *  Install_clock
+ *
+ *  Install a clock tick handler and reprograms the chip.  This
+ *  is used to initially establish the clock tick.
+ */
+static void Install_clock(
+  rtems_isr_entry clock_isr
+)
+{
+  uint8_t   temp8 = 0;
+  uint32_t   factor = 1000000;
+
+  /*
+   *  Initialize the clock tick device driver variables
+   */
+
+  Clock_driver_ticks = 0;
+  Clock_isrs_const = rtems_configuration_get_microseconds_per_tick() / 10000;
+  Clock_isrs = Clock_isrs_const;
+
+  factor /= rtems_configuration_get_microseconds_per_tick(); /* minimalization of integer division error */
+  Clock_MHZ = bsp_clicks_per_second / factor ;
+
+  rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker );
+
+  /*
+   *  Hardware specific initialize goes here
+   */
+
+  /* stop Timer 0 */
+  temp8 = read8( MTU_TSTR) & MTU0_STARTMASK;
+  write8( temp8, MTU_TSTR);
+
+  /* set initial counter value to 0 */
+  write16( 0, MTU_TCNT0);
+
+  /* Timer 0 runs independent */
+  temp8 = read8( MTU_TSYR) & MTU0_SYNCMASK;
+  write8( temp8, MTU_TSYR);
+
+  /* Timer 0 normal mode */
+  temp8 = read8( MTU_TMDR0) & MTU0_MODEMASK;
+  write8( temp8, MTU_TMDR0);
+
+  /* TCNT is cleared by GRA ; internal clock /16 */
+  write8( MTU0_TCRMASK , MTU_TCR0);
+
+  /* use GRA without I/O - pins  */
+  write8( MTU0_TIORVAL, MTU_TIORL0);
+
+  /* reset flags of the status register */
+  temp8 = read8( MTU_TSR0) & MTU0_STAT_MASK;
+  write8( temp8, MTU_TSR0);
+
+  /* Irq if is equal GRA */
+  temp8 = read8( MTU_TIER0) | MTU0_TIERMASK;
+  write8( temp8, MTU_TIER0);
+
+  /* set interrupt priority */
+  if( sh_set_irq_priority( CLOCK_VECTOR, CLOCKPRIO ) != RTEMS_SUCCESSFUL)
+    rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
+
+  /* set counter limits */
+  write16( _MTU_COUNTER0_MICROSECOND, MTU_GR0A);
+
+  /* start counter */
+  temp8 = read8( MTU_TSTR) |~MTU0_STARTMASK;
+  write8( temp8, MTU_TSTR);
+
+  /*
+   *  Schedule the clock cleanup routine to execute if the application exits.
+   */
+  atexit( Clock_exit );
+}
+
+/*
+ *  Clean up before the application exits
+ */
+void Clock_exit( void )
+{
+  uint8_t   temp8 = 0;
+
+  /* turn off the timer interrupts */
+  /* set interrupt priority to 0 */
+  if( sh_set_irq_priority( CLOCK_VECTOR, 0 ) != RTEMS_SUCCESSFUL)
+    rtems_fatal_error_occurred( RTEMS_UNSATISFIED);
+
+/*
+ *   temp16 = read16( MTU_TIER0) & IPRC_MTU0_IRQMASK;
+ *   write16( temp16, MTU_TIER0);
+ */
+
+  /* stop counter */
+  temp8 = read8( MTU_TSTR) & MTU0_STARTMASK;
+  write8( temp8, MTU_TSTR);
+
+  /* old vector shall not be installed */
+}
+
+/*
+ *  Clock_initialize
+ *
+ *  Device driver entry point for clock tick driver initialization.
+ */
+rtems_device_driver Clock_initialize(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void *pargp
+)
+{
+  Install_clock( Clock_isr );
+
+  return RTEMS_SUCCESSFUL;
+}
diff --git a/c/src/lib/libbsp/sh/gensh2/console/sci.c b/c/src/lib/libbsp/sh/gensh2/console/sci.c
new file mode 100644
index 0000000000..143fc1bb94
--- /dev/null
+++ b/c/src/lib/libbsp/sh/gensh2/console/sci.c
@@ -0,0 +1,554 @@
+/*
+ * /dev/sci[0|1] for Hitachi SH 704X
+ *
+ * The SH doesn't have a designated console device. Therefore we "alias"
+ * another device as /dev/console and revector all calls to /dev/console
+ * to this device.
+ *
+ * This approach is similar to installing a sym-link from one device to
+ * another device. If rtems once will support sym-links for devices files,
+ * this implementation could be dropped.
+ */
+
+/*
+ *  Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ *
+ *  Modified to reflect sh7045 processor:
+ *  John M. Mills (jmills@tga.com)
+ *  TGA Technologies, Inc.
+ *  100 Pinnacle Way, Suite 140
+ *  Norcross, GA 30071 U.S.A.
+ *
+ *  This modified file may be copied and distributed in accordance
+ *  the above-referenced license. It is provided for critique and
+ *  developmental purposes without any warranty nor representation
+ *  by the authors or by TGA Technologies.
+ */
+
+#include <bsp.h>
+
+
+#include <stdlib.h>
+
+#include <rtems/libio.h>
+#include <rtems/iosupp.h>
+#include <rtems/score/sh_io.h>
+#include <rtems/score/ispsh7045.h>
+#include <rtems/score/iosh7045.h>
+#include <sh/sh7_sci.h>
+#include <sh/sh7_pfc.h>
+
+#include <sh/sci.h>
+
+#ifndef STANDALONE_EVB
+#define STANDALONE_EVB 0
+#endif
+
+/*
+ * NOTE: Some SH variants have 3 sci devices
+ */
+
+#define SCI_MINOR_DEVICES       2
+
+/*
+ * FIXME: sh7045 register names match Hitachi data book,
+ *  but conflict with RTEMS sh7032 usage.
+ */
+
+#define SH_SCI_BASE_0   SCI_SMR0
+#define SH_SCI_BASE_1   SCI_SMR1
+
+#define SH_SCI_DEF_COMM_0   CS8, B9600
+#define SH_SCI_DEF_COMM_1   CS8, B38400
+/*  #define SH_SCI_DEF_COMM_1   CS8, B9600 */
+
+struct scidev_t {
+  char *                     name;
+  uint32_t                   addr;
+  rtems_device_minor_number  minor;
+  unsigned short             opened;
+  tcflag_t                   cflags;
+  speed_t                    spd;
+} sci_device[SCI_MINOR_DEVICES] =
+{
+  { "/dev/sci0", SH_SCI_BASE_0, 0, 0, SH_SCI_DEF_COMM_0 },
+  { "/dev/sci1", SH_SCI_BASE_1, 1, 0, SH_SCI_DEF_COMM_1 }
+};
+
+/*  local data structures maintain hardware configuration */
+#if UNUSED
+static sci_setup_t sio_param[2];
+#endif
+
+/* Translate termios' tcflag_t into sci settings */
+static int _sci_set_cflags(
+  struct scidev_t  *sci_dev,
+  tcflag_t          c_cflag,
+  speed_t           spd
+)
+{
+  uint8_t  smr;
+  uint8_t  brr;
+
+  if ( spd )
+  {
+    if ( _sci_get_brparms( spd, &smr, &brr ) != 0 )
+      return -1;
+  }
+
+  if ( c_cflag & CSIZE )
+  {
+    if ( c_cflag & CS8 )
+      smr &= ~SCI_SEVEN_BIT_DATA;
+    else if ( c_cflag & CS7 )
+      smr |= SCI_SEVEN_BIT_DATA;
+    else
+      return -1;
+  }
+
+  if ( c_cflag & CSTOPB )
+    smr |= SCI_STOP_BITS_2;
+  else
+    smr &= ~SCI_STOP_BITS_2;
+
+  if ( c_cflag & PARENB )
+    smr |= SCI_PARITY_ON;
+  else
+    smr &= ~SCI_PARITY_ON;
+
+  if ( c_cflag & PARODD )
+    smr |= SCI_ODD_PARITY;
+  else
+    smr &= ~SCI_ODD_PARITY;
+
+  write8( smr, sci_dev->addr + SCI_SMR );
+  write8( brr, sci_dev->addr + SCI_BRR );
+
+  return 0;
+}
+
+/*
+ * local functions operate SCI ports 0 and 1
+ * called from polling routines or ISRs
+ */
+static bool wrtSCI0(unsigned char ch)
+{
+  uint8_t   temp;
+  bool result = false;
+
+  if ((read8(SCI_SSR0) & SCI_TDRE) != 0x00) {
+    /* Write the character to the TDR */
+    write8(ch, SCI_TDR0);
+    /* Clear the TDRE bit */
+    temp = read8(SCI_SSR0) & ~SCI_TDRE;
+    write8(temp, SCI_SSR0);
+    result = true;
+  }
+  return result;
+} /* wrtSCI0 */
+
+static bool wrtSCI1(unsigned char ch)
+{
+  uint8_t   temp;
+  bool result = false;
+
+  if ((read8(SCI_SSR1) & SCI_TDRE) != 0x00) {
+     /* Write the character to the TDR */
+     write8(ch, SCI_TDR1);
+     /* Clear the TDRE bit */
+     temp = read8(SCI_SSR1) & ~SCI_TDRE;
+     write8(temp, SCI_SSR1);
+     result = true;
+  }
+  return result;
+} /* wrtSCI1 */
+
+/* polled output steers byte to selected port */
+static void sh_sci_outbyte_polled(
+  rtems_device_minor_number  minor,
+  char ch )
+{
+  if (minor == 0) /* blocks until port ready */
+    while (wrtSCI0(ch) != true); /* SCI0*/
+  else
+    while (wrtSCI1(ch) != true); /* SCI1*/
+} /* sh_sci_outbyte_polled */
+
+/*
+ * Initial version calls polled output driver and blocks
+ */
+static void outbyte(
+  rtems_device_minor_number  minor,
+  char ch)
+{
+  sh_sci_outbyte_polled(minor, (unsigned char)ch);
+} /* outbyte */
+
+static bool rdSCI0(unsigned char *ch)
+{
+  uint8_t   temp;
+  bool result = false;
+
+  if ((read8(SCI_SSR0) & SCI_RDRF) != 0x00) {
+    /* read input */
+    *ch = read8(SCI_RDR0);
+    /* Clear RDRF flag */
+    temp = read8(SCI_SSR0) & ~SCI_RDRF;
+    write8(temp, SCI_SSR0);
+    /* Check for transmission errors */
+    if (temp & (SCI_ORER | SCI_FER | SCI_PER)) {
+        /* TODO: report to RTEMS transmission error */
+
+        /* clear error flags*/
+        temp &= ~(SCI_ORER | SCI_FER | SCI_PER);
+        write8(temp, SCI_SSR0);
+    }
+    result = true;
+  }
+  return result;
+} /* rdSCI0 */
+
+static bool rdSCI1(unsigned char *ch)
+{
+  uint8_t   temp;
+  bool result = false;
+
+  if ((read8(SCI_SSR1) & SCI_RDRF) != 0x00) {
+    /* read input */
+    *ch = read8(SCI_RDR1);
+    /* Clear RDRF flag */
+    temp= read8(SCI_SSR1) & ~SCI_RDRF;
+    write8(temp, SCI_SSR1);
+    /* Check for transmission errors */
+    if (temp & (SCI_ORER | SCI_FER | SCI_PER)) {
+        /* TODO: report to RTEMS transmission error */
+
+        /* clear error flags*/
+        temp &= ~(SCI_ORER | SCI_FER | SCI_PER);
+        write8(temp, SCI_SSR1);
+    }
+    result = true;
+  }
+  return result;
+} /* rdSCI1 */
+
+/* initial version pulls byte from selected port */
+static char sh_sci_inbyte_polled( rtems_device_minor_number  minor )
+{
+  uint8_t ch = 0;
+
+  if (minor == 0) /* blocks until char.ready */
+    while (rdSCI0(&ch) != true); /* SCI0 */
+  else
+    while (rdSCI1(&ch) != true); /* SCI1 */
+  return ch;
+} /* sh_sci_inbyte_polled */
+
+/* Initial version calls polled input driver */
+static char inbyte( rtems_device_minor_number  minor )
+{
+  char ch;
+
+  ch = sh_sci_inbyte_polled(minor);
+  return ch;
+} /* inbyte */
+
+/*  sh_sci_initialize
+ *
+ *  This routine initializes (registers) the sh_sci IO drivers.
+ *
+ *  Input parameters: ignored
+ *
+ *  Output parameters:  NONE
+ *
+ *  Return values: RTEMS_SUCCESSFUL
+ *   if all sci[...] register, else calls
+ *   rtems_fatal_error_occurred(status)
+ */
+rtems_device_driver sh_sci_initialize(
+  rtems_device_major_number  major,
+  rtems_device_minor_number  minor,
+  void                      *arg )
+{
+  rtems_device_driver status;
+  rtems_device_minor_number i;
+
+  /*
+   * register all possible devices.
+   * the initialization of the hardware is done by sci_open
+   *
+   * One of devices could be previously registered by console
+   * initialization therefore we check it everytime
+   */
+  for ( i = 0 ; i < SCI_MINOR_DEVICES ; i++ ) {
+    /* OK. We assume it is not registered yet. */
+    status = rtems_io_register_name(
+      sci_device[i].name,
+      major,
+      sci_device[i].minor
+    );
+    if (status != RTEMS_SUCCESSFUL)
+      rtems_fatal_error_occurred(status);
+  }
+
+  /* non-default hardware setup occurs in sh_sci_open() */
+  return RTEMS_SUCCESSFUL;
+}
+
+/*
+ *  Open entry point
+ *   Sets up port and pins for selected sci.
+ */
+rtems_device_driver sh_sci_open(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void                    * arg )
+{
+  uint8_t    temp8;
+  uint16_t   temp16;
+
+  unsigned   a;
+
+ /* check for valid minor number */
+ if (( minor > ( SCI_MINOR_DEVICES -1 )) || ( minor < 0 )) {
+   return RTEMS_INVALID_NUMBER;
+ }
+
+  /* device already opened */
+  if ( sci_device[minor].opened > 0 ) {
+    sci_device[minor].opened++;
+    return RTEMS_SUCCESSFUL;
+  }
+
+  /* set PFC registers to enable I/O pins */
+
+  if ((minor == 0)) {
+    temp16 = read16(PFC_PACRL2);         /* disable SCK0, DMA, IRQ */
+    temp16 &= ~(PA2MD1 | PA2MD0);
+    temp16 |= (PA_TXD0 | PA_RXD0);       /* enable pins for Tx0, Rx0 */
+    write16(temp16, PFC_PACRL2);
+
+  } else if (minor == 1) {
+    temp16 = read16(PFC_PACRL2);          /* disable SCK1, DMA, IRQ */
+    temp16 &= ~(PA5MD1 | PA5MD0);
+    temp16 |= (PA_TXD1 | PA_RXD1);        /* enable pins for Tx1, Rx1 */
+    write16(temp16, PFC_PACRL2);
+
+  } /* add other devices and pins as req'd. */
+
+  /* set up SCI registers */
+      write8(0x00, sci_device[minor].addr + SCI_SCR);   /* Clear SCR */
+                                                   /* set SMR and BRR */
+    _sci_set_cflags( &sci_device[minor], sci_device[minor].cflags, sci_device[minor].spd );
+
+    for (a=0; a < 10000L; a++) {                      /* Delay */
+      __asm__ volatile ("nop");
+    }
+
+    write8((SCI_RE | SCI_TE),              /* enable async. Tx and Rx */
+     sci_device[minor].addr + SCI_SCR);
+
+    /* clear error flags */
+    temp8 = read8(sci_device[minor].addr + SCI_SSR);
+    while (temp8 & (SCI_RDRF | SCI_ORER | SCI_FER | SCI_PER)) {
+        temp8 = read8(sci_device[minor].addr + SCI_RDR);   /* flush input */
+        temp8 = read8(sci_device[minor].addr + SCI_SSR); /* clear some flags */
+        write8(temp8 & ~(SCI_RDRF | SCI_ORER | SCI_FER | SCI_PER),
+               sci_device[minor].addr + SCI_SSR);
+        temp8 = read8(sci_device[minor].addr + SCI_SSR); /* check if everything is OK */
+    }
+    /* Clear RDRF flag */
+    write8(0x00, sci_device[minor].addr + SCI_TDR);    /* force output */
+     /* Clear the TDRE bit */
+     temp8 = read8(sci_device[minor].addr + SCI_SSR) & ~SCI_TDRE;
+     write8(temp8, sci_device[minor].addr + SCI_SSR);
+
+    /* add interrupt setup if required */
+
+
+  sci_device[minor].opened++;
+
+  return RTEMS_SUCCESSFUL;
+}
+
+/*
+ *  Close entry point
+ */
+rtems_device_driver sh_sci_close(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void                    * arg
+)
+{
+  /* FIXME: Incomplete */
+  if ( sci_device[minor].opened > 0 )
+    sci_device[minor].opened--;
+  else
+    return RTEMS_INVALID_NUMBER;
+
+  return RTEMS_SUCCESSFUL;
+}
+
+/*
+ * read bytes from the serial port. We only have stdin.
+ */
+rtems_device_driver sh_sci_read(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void                    * arg
+)
+{
+  rtems_libio_rw_args_t *rw_args;
+  char *buffer;
+  int maximum;
+  int count = 0;
+
+  rw_args = (rtems_libio_rw_args_t *) arg;
+
+  buffer = rw_args->buffer;
+  maximum = rw_args->count;
+
+  for (count = 0; count < maximum; count++) {
+    buffer[ count ] = inbyte(minor);
+    if (buffer[ count ] == '\n' || buffer[ count ] == '\r') {
+      buffer[ count++ ]  = '\n';
+      break;
+    }
+  }
+
+  rw_args->bytes_moved = count;
+  return (count >= 0) ? RTEMS_SUCCESSFUL : RTEMS_UNSATISFIED;
+}
+
+/*
+ * write bytes to the serial port. Stdout and stderr are the same.
+ */
+rtems_device_driver sh_sci_write(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void                    * arg
+)
+{
+  int count;
+  int maximum;
+  rtems_libio_rw_args_t *rw_args;
+  char *buffer;
+
+  rw_args = (rtems_libio_rw_args_t *) arg;
+
+  buffer = rw_args->buffer;
+  maximum = rw_args->count;
+
+  for (count = 0; count < maximum; count++) {
+    if ( buffer[ count ] == '\n') {
+      outbyte(minor, '\r');
+    }
+    outbyte( minor, buffer[ count ] );
+  }
+
+  rw_args->bytes_moved = maximum;
+  return 0;
+}
+
+/*
+ *  IO Control entry point
+ */
+rtems_device_driver sh_sci_control(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void                    * arg
+)
+{
+  /* Not yet supported */
+  return RTEMS_SUCCESSFUL;
+}
+
+/*
+ * Termios polled first open
+ */
+static int _sh_sci_poll_first_open(int major, int minor, void *arg)
+{
+    return sh_sci_open(major, minor, arg);
+}
+
+/*
+ * Termios general last close
+ */
+static int _sh_sci_last_close(int major, int minor, void *arg)
+{
+    return sh_sci_close(major, minor, arg);
+}
+
+/*
+ * Termios polled read
+ */
+static int _sh_sci_poll_read(int minor)
+{
+  int value = -1;
+  uint8_t ch = 0;
+
+  if ( minor == 0 ) {
+    if ( rdSCI0( &ch ) )
+      value = (int) ch;
+  } else if ( minor == 1 ) {
+    if ( rdSCI1( &ch ) )
+      value = (int) ch;
+  }
+  return value;
+}
+
+/*
+ * Termios polled write
+ */
+static ssize_t _sh_sci_poll_write(int minor, const char *buf, size_t len)
+{
+    size_t count;
+
+    for (count = 0; count < len; count++)
+        outbyte( minor, buf[count] );
+    return count;
+}
+
+/*
+ * Termios set attributes
+ */
+static int _sh_sci_set_attributes( int minor, const struct termios *t)
+{
+    return _sci_set_cflags( &sci_device[ minor ], t->c_cflag, t->c_ospeed);
+}
+
+
+const rtems_termios_callbacks sci_poll_callbacks = {
+    _sh_sci_poll_first_open,    /* FirstOpen*/
+    _sh_sci_last_close,         /* LastClose*/
+    _sh_sci_poll_read,          /* PollRead  */
+    _sh_sci_poll_write,         /* Write */
+    _sh_sci_set_attributes,     /* setAttributes */
+    NULL,                       /* stopRemoteTX */
+    NULL,                       /* StartRemoteTX */
+    0                           /* outputUsesInterrupts */
+};
+
+/* FIXME: not yet supported */
+const rtems_termios_callbacks sci_interrupt_callbacks;
+
+const rtems_termios_callbacks* sh_sci_get_termios_handlers( bool poll )
+{
+  return poll ?
+      &sci_poll_callbacks :
+      &sci_interrupt_callbacks;
+}
diff --git a/c/src/lib/libbsp/sh/gensh2/console/sci_termios.c b/c/src/lib/libbsp/sh/gensh2/console/sci_termios.c
new file mode 100644
index 0000000000..5d588065af
--- /dev/null
+++ b/c/src/lib/libbsp/sh/gensh2/console/sci_termios.c
@@ -0,0 +1,449 @@
+/*
+ * Termios console serial driver.
+ */
+
+/*
+ * Based on SCI driver by Ralf Corsepius and John M. Mills
+ *
+ * Author: Radzislaw Galler <rgaller@et.put.poznan.pl>
+ *
+ *  COPYRIGHT (c) 1989-2001.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ *
+ */
+
+#include <bsp.h>
+#include <stdlib.h>
+
+#include <libchip/serial.h>
+#include <libchip/sersupp.h>
+
+#include <rtems/libio.h>
+#include <rtems/iosupp.h>
+
+#include <rtems/score/sh_io.h>
+#include <rtems/score/ispsh7045.h>
+#include <rtems/score/iosh7045.h>
+
+#include <sh/sh7_sci.h>
+#include <sh/sh7_pfc.h>
+#include <sh/sci_termios.h>
+
+
+/*
+ * Some handy macros
+ */
+#define SH_SCI_REG_DATA(_data, _minor, _register) \
+ (write8(_data, Console_Port_Tbl[_minor]->ulCtrlPort1 + (_register)))
+
+#define SH_SCI_REG_FLAG(_flag, _minor, _register) \
+ (write8(read8(Console_Port_Tbl[_minor]->ulCtrlPort1 + (_register)) | (_flag), \
+         Console_Port_Tbl[_minor]->ulCtrlPort1 + (_register)))
+
+#define SH_SCI_REG_MASK(_flag, _minor, _register) \
+ (write8(read8(Console_Port_Tbl[_minor]->ulCtrlPort1 + (_register)) & ~(_flag),\
+         Console_Port_Tbl[_minor]->ulCtrlPort1 + (_register)))
+
+/*
+ * NOTE: Some SH variants have 3 sci devices
+ */
+
+#define SCI_MINOR_DEVICES       2
+
+
+/*
+ * Automatically generated function imported from scitab.rel
+ */
+extern int _sci_get_brparms(
+  speed_t       spd,
+  unsigned char *smr,
+  unsigned char *brr
+);
+
+/*
+ * Translate termios flags into SCI settings
+ */
+int sh_sci_set_attributes(
+  int minor,
+  const struct termios *t
+)
+{
+    uint8_t  	smr;
+    uint8_t  	brr;
+    int a;
+
+    tcflag_t c_cflag = t->c_cflag;
+    speed_t spd = t->c_ospeed;
+
+    if ( spd ) {
+        if ( _sci_get_brparms( spd, &smr, &brr ) != 0 )
+            return -1 ;
+    }
+
+    if ( c_cflag & CSIZE ) {
+        if ( c_cflag & CS8 )
+            smr &= ~SCI_SEVEN_BIT_DATA;
+        else if ( c_cflag & CS7 )
+            smr |= SCI_SEVEN_BIT_DATA;
+        else
+            return -1 ;
+    }
+
+    if ( c_cflag & CSTOPB )
+        smr |= SCI_STOP_BITS_2;
+    else
+        smr &= ~SCI_STOP_BITS_2;
+
+    if ( c_cflag & PARENB )
+        smr |= SCI_PARITY_ON ;
+    else
+        smr &= ~SCI_PARITY_ON ;
+
+    if ( c_cflag & PARODD )
+        smr |= SCI_ODD_PARITY ;
+    else
+        smr &= ~SCI_ODD_PARITY;
+
+    SH_SCI_REG_MASK((SCI_RE | SCI_TE), minor, SCI_SCR);
+
+    SH_SCI_REG_DATA(smr, minor, SCI_SMR);
+    SH_SCI_REG_DATA(brr, minor, SCI_BRR);
+
+    for (a=0; a < 10000L; a++) { /* Delay one bit */
+        __asm__ volatile ("nop");
+    }
+
+    SH_SCI_REG_FLAG((SCI_RE | SCI_TE), minor, SCI_SCR);
+
+    return 0;
+}
+
+/*
+ * Receive-data-full ISR
+ *
+ * The same routine for all interrupt sources of the same type.
+ */
+static rtems_isr sh_sci_rx_isr(rtems_vector_number vector)
+{
+    int minor;
+
+    for (minor = 0; minor < Console_Port_Count; minor++) {
+        if (Console_Port_Tbl[minor]->ulIntVector == vector) {
+            char   temp8;
+
+            /*
+             * FIXME: error handling should be added
+             */
+            temp8 = read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_RDR);
+
+            rtems_termios_enqueue_raw_characters(
+                Console_Port_Data[minor].termios_data, &temp8, 1);
+
+            SH_SCI_REG_MASK(SCI_RDRF, minor, SCI_SSR);
+            break;
+        }
+    }
+}
+
+/*
+ * Transmit-data-empty ISR
+ *
+ * The same routine for all interrupt sources of the same type.
+ */
+static rtems_isr sh_sci_tx_isr(rtems_vector_number vector)
+{
+    int minor;
+
+    for (minor = 0; minor < Console_Port_Count; minor++) {
+        if (Console_Port_Tbl[minor]->ulDataPort == vector) {
+            /*
+             * FIXME: Error handling should be added
+             */
+
+            /*
+             * Mask end-of-transmission interrupt
+             */
+            SH_SCI_REG_MASK(SCI_TIE, minor, SCI_SCR);
+
+            if (rtems_termios_dequeue_characters(
+                   Console_Port_Data[minor].termios_data, 1)) {
+                /*
+                 * More characters to be received - interrupt must be enabled
+                 */
+                SH_SCI_REG_FLAG(SCI_TIE, minor, SCI_SCR);
+            }
+            break;
+        }
+    }
+}
+
+
+/*
+ * Initialization of serial port
+ */
+void sh_sci_init(int minor)
+{
+    uint16_t   temp16;
+
+    /*
+     * set PFC registers to enable I/O pins
+     */
+    if ((minor == 0)) {
+        temp16 = read16(PFC_PACRL2);         /* disable SCK0, DMA, IRQ */
+        temp16 &= ~(PA2MD1 | PA2MD0);
+        temp16 |= (PA_TXD0 | PA_RXD0);       /* enable pins for Tx0, Rx0 */
+        write16(temp16, PFC_PACRL2);
+
+    } else if (minor == 1) {
+        temp16 = read16(PFC_PACRL2);          /* disable SCK1, DMA, IRQ */
+        temp16 &= ~(PA5MD1 | PA5MD0);
+        temp16 |= (PA_TXD1 | PA_RXD1);        /* enable pins for Tx1, Rx1 */
+        write16(temp16, PFC_PACRL2);
+    }
+
+    /*
+     * Non-default hardware setup occurs in sh_sci_first_open
+     */
+}
+
+/*
+ * Initialization of interrupts
+ *
+ * Interrupts can be started only after opening a device, so interrupt
+ * flags are set up in sh_sci_first_open function
+ */
+void sh_sci_initialize_interrupts(int minor)
+{
+    rtems_isr_entry old_isr;
+    rtems_status_code status;
+
+    sh_sci_init(minor);
+    /*
+     * Disable IRQ of SCIx
+     */
+    status = sh_set_irq_priority( Console_Port_Tbl[minor]->ulIntVector, 0);
+
+    if (status != RTEMS_SUCCESSFUL)
+        rtems_fatal_error_occurred(status);
+
+    SH_SCI_REG_MASK(SCI_RIE, minor, SCI_SCR);
+
+    /*
+     * Catch apropriate vectors
+     */
+    status = rtems_interrupt_catch(
+        sh_sci_rx_isr,
+        Console_Port_Tbl[minor]->ulIntVector,
+        &old_isr);
+
+    if (status != RTEMS_SUCCESSFUL)
+        rtems_fatal_error_occurred(status);
+
+    status = rtems_interrupt_catch(
+        sh_sci_tx_isr,
+        Console_Port_Tbl[minor]->ulDataPort,
+        &old_isr);
+
+    if (status != RTEMS_SUCCESSFUL)
+        rtems_fatal_error_occurred(status);
+
+    /*
+     * Enable IRQ of SCIx
+     */
+    SH_SCI_REG_FLAG(SCI_RIE, minor, SCI_SCR);
+
+    status = sh_set_irq_priority(
+        Console_Port_Tbl[minor]->ulIntVector,
+        Console_Port_Tbl[minor]->ulCtrlPort2);
+
+    if (status != RTEMS_SUCCESSFUL)
+        rtems_fatal_error_occurred(status);
+}
+
+
+/*
+ *  Open entry point
+ *   Sets up port and pins for selected sci.
+ */
+
+int sh_sci_first_open(
+  int major,
+  int minor,
+  void *arg
+)
+{
+    char   temp8;
+    unsigned int a ;
+
+    /*
+     * check for valid minor number
+     */
+    if (( minor > ( SCI_MINOR_DEVICES -1 )) || ( minor < 0 )) {
+        return RTEMS_INVALID_NUMBER;
+    }
+
+    /*
+     * set up SCI registers
+     */
+    /* Clear SCR - disable Tx and Rx */
+    SH_SCI_REG_DATA(0x00, minor, SCI_SCR);
+
+    /* set SMR and BRR - baudrate and format */
+    sh_sci_set_attributes(minor, Console_Port_Tbl[minor]->pDeviceParams);
+
+    for (a=0; a < 10000L; a++) {                      /* Delay */
+        __asm__ volatile ("nop");
+    }
+
+    write8((SCI_RE | SCI_TE),              /* enable async. Tx and Rx */
+           Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_SCR);
+
+    /*
+     * clear error flags
+     */
+    temp8 = read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_SSR);
+    while(temp8 & (SCI_RDRF | SCI_ORER | SCI_FER | SCI_PER)) {
+        /* flush input */
+        temp8 = read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_RDR);
+
+        /* clear some flags */
+        SH_SCI_REG_FLAG((SCI_RDRF|SCI_ORER|SCI_FER|SCI_PER), minor, SCI_SSR);
+
+        /* check if everything is OK */
+        temp8 = read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_SSR);
+    }
+
+    /* Clear RDRF flag */
+    SH_SCI_REG_DATA(0x00, minor, SCI_TDR); /* force output */
+
+    /* Clear the TDRE bit */
+    SH_SCI_REG_FLAG(SCI_TDRE, minor, SCI_SSR);
+
+    /*
+     * Interrupt setup
+     */
+    if (Console_Port_Tbl[minor]->pDeviceFns->deviceOutputUsesInterrupts) {
+        SH_SCI_REG_FLAG(SCI_RIE, minor, SCI_SCR);
+    }
+
+    return RTEMS_SUCCESSFUL ;
+}
+
+/*
+ *  Close entry point
+ */
+
+int sh_sci_last_close(
+  int major,
+  int minor,
+  void *arg
+)
+{
+    /* FIXME: Incomplete */
+
+    /* Shutdown interrupts if necessary */
+    if (Console_Port_Tbl[minor]->pDeviceFns->deviceOutputUsesInterrupts)
+    {
+        SH_SCI_REG_MASK((SCI_TIE | SCI_RIE), minor, SCI_SCR);
+    }
+    return RTEMS_SUCCESSFUL ;
+}
+
+/*
+ * Interrupt aware write routine
+ */
+ssize_t sh_sci_write_support_int(
+  int            minor,
+  const char    *buf,
+  size_t         len
+)
+{
+    if (!len)
+        return 0;
+    /*
+     * Put data into TDR and clear transmission-end-flag
+     */
+    SH_SCI_REG_DATA(*buf, minor, SCI_TDR);
+    SH_SCI_REG_MASK(SCI_TDRE, minor, SCI_SSR);
+    /*
+     * Enable interrupt
+     */
+    SH_SCI_REG_FLAG(SCI_TIE, minor, SCI_SCR);
+
+    return 1;
+}
+
+/*
+ * Polled write method
+ */
+ssize_t sh_sci_write_support_polled(
+  int            minor,
+  const char    *buf,
+  size_t         len
+)
+{
+    int count = 0;
+
+    while(count < len) {
+        sh_sci_write_polled(minor, buf[count]);
+        count++;
+    }
+    /*
+     * Return number of bytes written
+     */
+    return count;
+}
+
+/*
+ * Polled write of one character at a time
+ */
+void sh_sci_write_polled(
+  int     minor,
+  char    c
+)
+{
+    /*
+     * Wait for end of previous character
+     */
+    while(!(read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_SSR) & SCI_TDRE));
+    /*
+     * Send the character
+     */
+    SH_SCI_REG_DATA(c, minor, SCI_TDR);
+
+    /*
+     * Clear TDRE flag
+     */
+    SH_SCI_REG_MASK(SCI_TDRE, minor, SCI_SSR);
+}
+
+/*
+ * Non-blocking read
+ */
+int sh_sci_inbyte_nonblocking_polled(int minor)
+{
+    char   inbyte;
+
+    /*
+     * Check if input buffer is full
+     */
+    if (read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_SSR) & SCI_RDRF) {
+        inbyte = read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_RDR);
+        SH_SCI_REG_MASK(SCI_RDRF, minor, SCI_SSR);
+
+        /*
+         * Check for errors
+         */
+        if (read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_SSR) &
+           (SCI_ORER | SCI_FER | SCI_PER)) {
+            SH_SCI_REG_MASK((SCI_ORER | SCI_FER | SCI_PER), minor, SCI_SSR);
+            return -1;
+        }
+        return (int)inbyte;
+    }
+    return -1;
+}
diff --git a/c/src/lib/libbsp/sh/gensh2/include/rtems/score/iosh7045.h b/c/src/lib/libbsp/sh/gensh2/include/rtems/score/iosh7045.h
new file mode 100644
index 0000000000..db3252b72d
--- /dev/null
+++ b/c/src/lib/libbsp/sh/gensh2/include/rtems/score/iosh7045.h
@@ -0,0 +1,322 @@
+/*
+ *  This include file contains information pertaining to the Hitachi SH
+ *  processor.
+ *
+ *  NOTE: NOT ALL VALUES HAVE BEEN CHECKED !!
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
+ *  contained no copyright notice.
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ *
+ *	Modified to reflect on-chip registers for sh7045 processor, based on
+ *	"Register.h" distributed with Hitachi's EVB7045F tutorials, and which
+ *  contained no copyright notice:
+ *	John M. Mills (jmills@tga.com)
+ *	TGA Technologies, Inc.
+ *  100 Pinnacle Way, Suite 140
+ *	Norcross, GA 30071 U.S.A.
+ *	August, 1999
+ *
+ *	This modified file may be copied and distributed in accordance
+ *	the above-referenced license. It is provided for critique and
+ *	developmental purposes without any warranty nor representation
+ *	by the authors or by TGA Technologies.
+ */
+
+#ifndef __IOSH7045_H
+#define __IOSH7045_H
+
+/*
+ * After each line is explained whether the access is char short or long.
+ * The functions read/writeb, w, l, 8, 16, 32 can be found
+ * in exec/score/cpu/sh/sh_io.h
+ *
+ * 8 bit  == char     ( readb, writeb, read8, write8)
+ * 16 bit == short    ( readw, writew, read16, write16 )
+ * 32 bit == long     ( readl, writel, read32, write32 )
+ * JMM: Addresses noted "[char, ]short,word" are per Hitachi _SuperH_RISC_
+ *      ENGINE_..Hardware_Manual; alignment access-restrictions may apply
+ */
+
+#define REG_BASE    0xFFFF8000
+
+/* SCI0 Registers */
+#define SCI_SMR0   (REG_BASE + 0x01a0) /*char: Serial mode     ch 0 */
+#define SCI_BRR0   (REG_BASE + 0x01a1) /*char: Bit rate        ch 0 */
+#define SCI_SCR0   (REG_BASE + 0x01a2) /*char: Serial control  ch 0 */
+#define SCI_TDR0   (REG_BASE + 0x01a3) /*char: Transmit data   ch 0 */
+#define SCI_SSR0   (REG_BASE + 0x01a4) /*char: Serial status   ch 0 */
+#define SCI_RDR0   (REG_BASE + 0x01a5) /*char: Receive data    ch 0 */
+
+#define SCI0_SMR   SCI_SMR0
+
+/* SCI1 Registers */
+#define SCI_SMR1   (REG_BASE + 0x01b0) /* char: Serial mode     ch 1 */
+#define SCI_BRR1   (REG_BASE + 0x01b1) /* char: Bit rate        ch 1 */
+#define SCI_SCR1   (REG_BASE + 0x01b2) /* char: Serial control  ch 1 */
+#define SCI_TDR1   (REG_BASE + 0x01b3) /* char: Transmit data   ch 1 */
+#define SCI_SSR1   (REG_BASE + 0x01b4) /* char: Serial status   ch 1 */
+#define SCI_RDR1   (REG_BASE + 0x01b5) /* char: Receive data    ch 1 */
+
+#define SCI1_SMR   SCI_SMR1
+
+/* ADI */
+/* High Speed A/D (Excluding A-Mask Part)*/
+#define ADDRA	   (REG_BASE + 0x03F0) /* short */
+#define ADDRB	   (REG_BASE + 0x03F2) /* short */
+#define ADDRC	   (REG_BASE + 0x03F4) /* short */
+#define ADDRD	   (REG_BASE + 0x03F6) /* short */
+#define ADDRE	   (REG_BASE + 0x03F8) /* short */
+#define ADDRF	   (REG_BASE + 0x03FA) /* short */
+#define ADDRG	   (REG_BASE + 0x03FC) /* short */
+#define ADDRH	   (REG_BASE + 0x03FE) /* short */
+#define ADCSR	   (REG_BASE + 0x03E0) /* char  */
+#define ADCR	   (REG_BASE + 0x03E1) /* char  */
+
+/* Mid-Speed A/D (A-Mask part)*/
+#define ADDRA0	   (REG_BASE + 0x0400) /* char, short */
+#define ADDRA0H	   (REG_BASE + 0x0400) /* char, short */
+#define ADDRA0L    (REG_BASE + 0x0401) /* char  */
+#define ADDRB0	   (REG_BASE + 0x0402) /* char, short */
+#define ADDRB0H	   (REG_BASE + 0x0402) /* char, short */
+#define ADDRB0L	   (REG_BASE + 0x0403) /* char  */
+#define ADDRC0	   (REG_BASE + 0x0404) /* char, short */
+#define ADDRC0H	   (REG_BASE + 0x0404) /* char, short */
+#define ADDRC0L	   (REG_BASE + 0x0405) /* char  */
+#define ADDRD0	   (REG_BASE + 0x0406) /* char, short */
+#define ADDRD0H	   (REG_BASE + 0x0406) /* char, short  */
+#define ADDRD0L	   (REG_BASE + 0x0407) /* char  */
+#define ADCSR0	   (REG_BASE + 0x0410) /* char  */
+#define ADCR0	   (REG_BASE + 0x0412) /* char  */
+#define ADDRA1	   (REG_BASE + 0x0408) /* char, short */
+#define ADDRA1H	   (REG_BASE + 0x0408) /* char, short */
+#define ADDRA1L	   (REG_BASE + 0x0409) /* char  */
+#define ADDRB1	   (REG_BASE + 0x040A) /* char, short */
+#define ADDRB1H	   (REG_BASE + 0x040A) /* char, short */
+#define ADDRB1L	   (REG_BASE + 0x040B) /* char  */
+#define ADDRC1	   (REG_BASE + 0x040C) /* char, short */
+#define ADDRC1H	   (REG_BASE + 0x040C) /* char, short */
+#define ADDRC1L	   (REG_BASE + 0x040D) /* char  */
+#define ADDRD1	   (REG_BASE + 0x040E) /* char, short */
+#define ADDRD1H	   (REG_BASE + 0x040E) /* char, short  */
+#define ADDRD1L	   (REG_BASE + 0x040F) /* char  */
+#define ADCSR1	   (REG_BASE + 0x0411) /* char  */
+#define ADCR1	   (REG_BASE + 0x0413) /* char  */
+
+/*MTU SHARED*/
+#define MTU_TSTR   (REG_BASE + 0x0240) /* char, short, word  */
+#define MTU_TSYR   (REG_BASE + 0x0241) /* char, short, word  */
+#define MTU_ICSR   (REG_BASE + 0x03C0) /* input lev. CSR */
+#define MTU_OCSR   (REG_BASE + 0x03C0) /* output lev. CSR */
+
+/*MTU CHANNEL 0*/
+#define MTU_TCR0   (REG_BASE + 0x0260) /* char, short, word  */
+#define MTU_TMDR0  (REG_BASE + 0x0261) /* char, short, word  */
+#define MTU_TIORH0 (REG_BASE + 0x0262) /* char, short, word  */
+#define MTU_TIORL0 (REG_BASE + 0x0263) /* char, short, word  */
+#define MTU_TIER0  (REG_BASE + 0x0264) /* char, short, word  */
+#define MTU_TSR0   (REG_BASE + 0x0265) /* char, short, word  */
+#define MTU_TCNT0  (REG_BASE + 0x0266) /* short, word */
+#define MTU_GR0A   (REG_BASE + 0x0268) /* short, word */
+#define MTU_GR0B   (REG_BASE + 0x026A) /* short, word */
+#define MTU_GR0C   (REG_BASE + 0x026C) /* short, word */
+#define MTU_GR0D   (REG_BASE + 0x026E) /* short, word */
+
+/*MTU CHANNEL 1*/
+#define MTU_TCR1   (REG_BASE + 0x0280) /* char, short, word  */
+#define MTU_TMDR1  (REG_BASE + 0x0281) /* char, short, word  */
+#define MTU_TIOR1  (REG_BASE + 0x0282) /* char, short, word  */
+#define MTU_TIER1  (REG_BASE + 0x0284) /* char, short, word  */
+#define MTU_TSR1   (REG_BASE + 0x0285) /* char, short, word  */
+#define MTU_TCNT1  (REG_BASE + 0x0286) /* short, word */
+#define MTU_GR1A   (REG_BASE + 0x0288) /* short, word */
+#define MTU_GR1B   (REG_BASE + 0x028A) /* short, word */
+
+/*MTU CHANNEL 2*/
+#define MTU_TCR2   (REG_BASE + 0x02A0) /* char, short, word  */
+#define MTU_TMDR2  (REG_BASE + 0x02A1) /* char, short, word  */
+#define MTU_TIOR2  (REG_BASE + 0x02A2) /* char, short, word  */
+#define MTU_TIER2  (REG_BASE + 0x02A4) /* char, short, word  */
+#define MTU_TSR2   (REG_BASE + 0x02A5) /* char, short, word  */
+#define MTU_TCNT2  (REG_BASE + 0x02A6) /* short, word */
+#define MTU_GR2A   (REG_BASE + 0x02A8) /* short, word */
+#define MTU_GR2B   (REG_BASE + 0x02AA) /* short, word */
+
+/*MTU CHANNELS 3-4 SHARED*/
+#define MTU_TOER   (REG_BASE + 0x020A) /* char, short, word  */
+#define MTU_TOCR   (REG_BASE + 0x020B) /* char, short, word  */
+#define MTU_TGCR   (REG_BASE + 0x020D) /* char, short, word  */
+#define MTU_TCDR   (REG_BASE + 0x0214) /* short, word  */
+#define MTU_TDDR   (REG_BASE + 0x0216) /* short, word  */
+#define MTU_TCNTS  (REG_BASE + 0x0220) /* short, word  */
+#define MTU_TCBR   (REG_BASE + 0x0222) /* short, word  */
+
+/*MTU CHANNEL 3*/
+#define MTU_TCR3   (REG_BASE + 0x0200) /* char, short, word  */
+#define MTU_TMDR3  (REG_BASE + 0x0202) /* char, short, word  */
+#define MTU_TIORH3 (REG_BASE + 0x0204) /* char, short, word  */
+#define MTU_TIORL3 (REG_BASE + 0x0205) /* char, short, word  */
+#define MTU_TIER3  (REG_BASE + 0x0208) /* char, short, word  */
+#define MTU_TSR3   (REG_BASE + 0x022C) /* char, short, word  */
+#define MTU_TCNT3  (REG_BASE + 0x0210) /* short, word */
+#define MTU_GR3A   (REG_BASE + 0x0218) /* short, word */
+#define MTU_GR3B   (REG_BASE + 0x021A) /* short, word */
+#define MTU_GR3C   (REG_BASE + 0x0224) /* short, word */
+#define MTU_GR3D   (REG_BASE + 0x0226) /* short, word */
+
+/*MTU CHANNEL 4*/
+#define MTU_TCR4   (REG_BASE + 0x0201) /* char, short, word  */
+#define MTU_TMDR4  (REG_BASE + 0x0203) /* char, short, word  */
+#define MTU_TIOR4  (REG_BASE + 0x0206) /* char, short, word  */
+#define MTU_TIORH4 (REG_BASE + 0x0206) /* char, short, word  */
+#define MTU_TIORL4 (REG_BASE + 0x0207) /* char, short, word  */
+#define MTU_TIER4  (REG_BASE + 0x0209) /* char, short, word  */
+#define MTU_TSR4   (REG_BASE + 0x022D) /* char, short, word  */
+#define MTU_TCNT4  (REG_BASE + 0x0212) /* short, word */
+#define MTU_GR4A   (REG_BASE + 0x021C) /* short, word */
+#define MTU_GR4B   (REG_BASE + 0x021E) /* short, word */
+#define MTU_GR4C   (REG_BASE + 0x0228) /* short, word */
+#define MTU_GR4D   (REG_BASE + 0x022A) /* short, word */
+
+/*DMAC CHANNELS 0-3 SHARED*/
+#define DMAOR      (REG_BASE + 0x06B0) /* short */
+
+/*DMAC CHANNEL 0*/
+#define DMA_SAR0    (REG_BASE + 0x06C0) /* short, word */
+#define DMA_DAR0    (REG_BASE + 0x06C4) /* short, word */
+#define DMA_DMATCR0 (REG_BASE + 0x06C8) /* short, word */
+#define DMA_CHCR0   (REG_BASE + 0x06CC) /* short, word */
+
+/*DMAC CHANNEL 1*/
+#define DMA_SAR1    (REG_BASE + 0x06D0) /* short, word */
+#define DMA_DAR1    (REG_BASE + 0x06D4) /* short, word */
+#define DMA_DMATCR1 (REG_BASE + 0x06D8) /* short, wordt */
+#define DMA_CHCR1   (REG_BASE + 0x06DC) /* short, word */
+
+/*DMAC CHANNEL 3*/
+#define DMA_SAR3    (REG_BASE + 0x06E0) /* short, word */
+#define DMA_DAR3    (REG_BASE + 0x06E4) /* short, word */
+#define DMA_DMATCR3 (REG_BASE + 0x06E8) /* short, word */
+#define DMA_CHCR3   (REG_BASE + 0x06EC) /* short, word */
+
+/*DMAC CHANNEL 4*/
+#define DMA_SAR4    (REG_BASE + 0x06F0) /* short, word */
+#define DMA_DAR4    (REG_BASE + 0x06F4) /* short, word */
+#define DMA_DMATCR4 (REG_BASE + 0x06F8) /* short, word */
+#define DMA_CHCR4   (REG_BASE + 0x06FC) /* short, word */
+
+/*Data Transfer Controller*/
+#define DTC_DTEA   (REG_BASE + 0x0700) /* char, short, word */
+#define DTC_DTEB   (REG_BASE + 0x0701) /* char, short(?), word(?) */
+#define DTC_DTEC   (REG_BASE + 0x0702) /* char, short(?), word(?) */
+#define DTC_DTED   (REG_BASE + 0x0703) /* char, short(?), word(?) */
+#define DTC_DTEE   (REG_BASE + 0x0704) /* char, short(?), word(?) */
+#define DTC_DTCSR  (REG_BASE + 0x0706) /* char, short, word */
+#define DTC_DTBR   (REG_BASE + 0x0708) /* short, word */
+
+/*Cache Memory*/
+#define CAC_CCR	   (REG_BASE + 0x0740) /* char, short, word */
+
+/*INTC*/
+#define INTC_IPRA  (REG_BASE + 0x0348) /* char, short, word */
+#define INTC_IPRB  (REG_BASE + 0x034A) /* char, short, word */
+#define INTC_IPRC  (REG_BASE + 0x034C) /* char, short, word */
+#define INTC_IPRD  (REG_BASE + 0x034E) /* char, short, word */
+#define INTC_IPRE  (REG_BASE + 0x0350) /* char, short, word */
+#define INTC_IPRF  (REG_BASE + 0x0352) /* char, short, word */
+#define INTC_IPRG  (REG_BASE + 0x0354) /* char, short, word */
+#define INTC_IPRH  (REG_BASE + 0x0356) /* char, short, word */
+#define INTC_ICR   (REG_BASE + 0x0358) /* char, short, word */
+#define INTC_ISR   (REG_BASE + 0x035A) /* char, short, word */
+
+/*Flash (F-ZTAT)*/
+#define FL_FLMCR1  (REG_BASE + 0x0580) /* Fl.Mem.Contr.Reg 1: char */
+#define FL_FLMCR2  (REG_BASE + 0x0581) /* Fl.Mem.Contr.Reg 2: char */
+#define FL_EBR1	   (REG_BASE + 0x0582) /* Fl.Mem.Erase Blk.1: char */
+#define FL_EBR2	   (REG_BASE + 0x0584) /* Fl.Mem.Erase Blk.2: char */
+#define FL_RAMER   (REG_BASE + 0x0628) /* Ram Emul.Reg.- char,short,word */
+
+/*UBC*/
+#define UBC_BARH   (REG_BASE + 0x0600) /* char, short, word  */
+#define UBC_BARL   (REG_BASE + 0x0602) /* char, short, word  */
+#define UBC_BAMRH  (REG_BASE + 0x0604) /* char, short, word  */
+#define UBC_BAMRL  (REG_BASE + 0x0606) /* char, short, word  */
+#define UBC_BBR    (REG_BASE + 0x0608) /* char, short, word  */
+/*BSC*/
+#define BSC_BCR1   (REG_BASE + 0x0620) /* short */
+#define BSC_BCR2   (REG_BASE + 0x0622) /* short */
+#define BSC_WCR1   (REG_BASE + 0x0624) /* short */
+#define BSC_WCR2   (REG_BASE + 0x0626) /* short */
+#define BSC_DCR    (REG_BASE + 0x062A) /* short */
+#define BSC_RTCSR  (REG_BASE + 0x062C) /* short */
+#define BSC_RTCNT  (REG_BASE + 0x062E) /* short */
+#define BSC_RTCOR  (REG_BASE + 0x0630) /* short */
+
+/*WDT*/
+#define WDT_R_TCSR   (REG_BASE + 0x0610) /* rd: char */
+#define WDT_R_TCNT   (REG_BASE + 0x0611) /* rd: char */
+#define WDT_R_RSTCSR (REG_BASE + 0x0613) /* rd: char */
+#define WDT_W_TCSR   (REG_BASE + 0x0610) /* wrt: short */
+#define WDT_W_TCNT   (REG_BASE + 0x0610) /* wrt: short */
+#define WDT_W_RSTCSR (REG_BASE + 0x0612) /* wrt: short */
+
+/*POWER DOWN STATE*/
+#define PDT_SBYCR  (REG_BASE + 0x0614) /* char  */
+
+/* Port I/O  Control Registers */
+#define IO_PADRH   (REG_BASE + 0x0380) /* Port A Data Register */
+#define IO_PADRL   (REG_BASE + 0x0382) /* Port A Data Register */
+#define IO_PBDR    (REG_BASE + 0x0390) /* Port B Data Register */
+#define IO_PCDR    (REG_BASE + 0x0392) /* Port C Data Register */
+#define IO_PDDRH   (REG_BASE + 0x03A0) /* Port D Data Register */
+#define IO_PDDRL   (REG_BASE + 0x03A2) /* Port D Data Register */
+#define IO_PEDR    (REG_BASE + 0x03B0) /* Port E Data Register */
+#define IO_PFDR    (REG_BASE + 0x03B2) /* Port F Data Register */
+
+/*Pin Function Control Register*/
+#define PFC_PAIORH (REG_BASE + 0x0384) /* Port A I/O Reg. H */
+#define PFC_PAIORL (REG_BASE + 0x0386) /* Port A I/O Reg. L */
+#define PFC_PACRH  (REG_BASE + 0x0388) /* Port A Ctr. Reg. H  */
+#define PFC_PACRL1 (REG_BASE + 0x038C) /* Port A Ctr. Reg. L1 */
+#define PFC_PACRL2 (REG_BASE + 0x038E) /* Port A Ctr. Reg. L2 */
+#define PFC_PBIOR  (REG_BASE + 0x0394) /* Port B I/O Register */
+#define PFC_PBCR1  (REG_BASE + 0x0398) /* Port B Ctr. Reg. R1 */
+#define PFC_PBCR2  (REG_BASE + 0x039A) /* Port B Ctr. Reg. R2 */
+#define PFC_PCIOR  (REG_BASE + 0x0396) /* Port C I/O Register */
+#define PFC_PCCR   (REG_BASE + 0x039C) /* Port C Ctr. Reg. */
+#define PFC_PDIORH (REG_BASE + 0x03A4) /* Port D I/O Reg. H */
+#define PFC_PDIORL (REG_BASE + 0x03A6) /* Port D I/O Reg. L */
+#define PFC_PDCRH1 (REG_BASE + 0x03A8) /* Port D Ctr. Reg. H1 */
+#define PFC_PDCRH2 (REG_BASE + 0x03AA) /* Port D Ctr. Reg. H2 */
+#define PFC_PDCRL  (REG_BASE + 0x03AC) /* Port D Ctr. Reg. L  */
+#define PFC_PEIOR  (REG_BASE + 0x03B4) /* Port E I/O Register */
+#define PFC_PECR1  (REG_BASE + 0x03B8) /* Port E Ctr. Reg. 1 */
+#define PFC_PECR2  (REG_BASE + 0x03BA) /* Port E Ctr. Reg. 2 */
+#define PFC_IFCR   (REG_BASE + 0x03C8) /* short */
+
+/*Compare/Match Timer*/
+#define CMT_CMSTR  (REG_BASE + 0x3D0) /* Start Reg. char, short, word */
+#define CMT_CMCSR0 (REG_BASE + 0x3D2) /* C0 SCR short, word */
+#define CMT_CMCNT0 (REG_BASE + 0x3D4) /* C0 Counter char, short, word */
+#define CMT_CMCOR0 (REG_BASE + 0x3D6) /* C0 Const.Reg. char, short, word */
+#define CMT_CMCSR1 (REG_BASE + 0x3D8) /* C1 SCR short, word */
+#define CMT_CMCNT1 (REG_BASE + 0x3DA) /* C1 Counter char, short, word */
+#define CMT_CMCOR1 (REG_BASE + 0x3DC) /* C1 Const.Reg. char, short, word */
+
+#endif
diff --git a/c/src/lib/libbsp/sh/gensh2/include/rtems/score/ispsh7045.h b/c/src/lib/libbsp/sh/gensh2/include/rtems/score/ispsh7045.h
new file mode 100644
index 0000000000..fb9f5297ae
--- /dev/null
+++ b/c/src/lib/libbsp/sh/gensh2/include/rtems/score/ispsh7045.h
@@ -0,0 +1,208 @@
+/*
+ *  This include file contains information pertaining to the Hitachi SH
+ *  processor.
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ *
+ *  Modified to reflect isp entries for sh7045 processor:
+ *  John M. Mills (jmills@tga.com)
+ *  TGA Technologies, Inc.
+ *  100 Pinnacle Way, Suite 140
+ *  Norcross, GA 30071 U.S.A.
+ *
+ *
+ *  This modified file may be copied and distributed in accordance
+ *  the above-referenced license. It is provided for critique and
+ *  developmental purposes without any warranty nor representation
+ *  by the authors or by TGA Technologies.
+ */
+
+#ifndef __CPU_ISPS_H
+#define __CPU_ISPS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rtems/score/types.h>
+
+extern void __ISR_Handler( uint32_t   vector );
+
+
+/*
+ * interrupt vector table offsets
+ */
+#define NMI_ISP_V 11
+#define USB_ISP_V 12
+#define IRQ0_ISP_V 64
+#define IRQ1_ISP_V 65
+#define IRQ2_ISP_V 66
+#define IRQ3_ISP_V 67
+#define IRQ4_ISP_V 68
+#define IRQ5_ISP_V 69
+#define IRQ6_ISP_V 70
+#define IRQ7_ISP_V 71
+#define DMA0_ISP_V 72
+#define DMA1_ISP_V 76
+#define DMA2_ISP_V 80
+#define DMA3_ISP_V 84
+
+#define MTUA0_ISP_V 88
+#define MTUB0_ISP_V 89
+#define MTUC0_ISP_V 90
+#define MTUD0_ISP_V 91
+#define MTUV0_ISP_V 92
+
+#define MTUA1_ISP_V 96
+#define MTUB1_ISP_V 97
+#define MTUV1_ISP_V 100
+#define MTUU1_ISP_V 101
+
+#define MTUA2_ISP_V 104
+#define MTUB2_ISP_V 105
+#define MTUV2_ISP_V 108
+#define MTUU2_ISP_V 109
+
+#define MTUA3_ISP_V 112
+#define MTUB3_ISP_V 113
+#define MTUC3_ISP_V 114
+#define MTUD3_ISP_V 115
+#define MTUV3_ISP_V 116
+
+#define MTUA4_ISP_V 120
+#define MTUB4_ISP_V 121
+#define MTUC4_ISP_V 122
+#define MTUD4_ISP_V 123
+#define MTUV4_ISP_V 124
+
+#define ERI0_ISP_V 128
+#define RXI0_ISP_V 129
+#define TXI0_ISP_V 130
+#define TEI0_ISP_V 131
+
+#define ERI1_ISP_V 132
+#define RXI1_ISP_V 133
+#define TXI1_ISP_V 134
+#define TEI1_ISP_V 135
+
+#define ADI0_ISP_V 136
+#define ADI1_ISP_V 137
+#define DTC_ISP_V 140  /* Data Transfer Controller */
+#define CMT0_ISP_V 144 /* Compare Match Timer */
+#define CMT1_ISP_V 148
+#define WDT_ISP_V 152  /* Wtachdog Timer */
+#define CMI_ISP_V 153  /* BSC RAS interrupt */
+#define OEI_ISP_V 156  /* I/O Port */
+#define DREF_ISP_V CMI_ISP_V /* DRAM Refresh from BSC */
+#if 0
+#define PRT_ISP_V /* parity error - no equivalent */
+#endif
+
+/* dummy ISP */
+extern void _dummy_isp( void );
+
+/* Non Maskable Interrupt */
+extern void _nmi_isp( void );
+
+/* User Break Controller */
+extern void _usb_isp( void );
+
+/* External interrupts 0-7 */
+extern void _irq0_isp( void );
+extern void _irq1_isp( void );
+extern void _irq2_isp( void );
+extern void _irq3_isp( void );
+extern void _irq4_isp( void );
+extern void _irq5_isp( void );
+extern void _irq6_isp( void );
+extern void _irq7_isp( void );
+
+/* DMA - Controller */
+extern void _dma0_isp( void );
+extern void _dma1_isp( void );
+extern void _dma2_isp( void );
+extern void _dma3_isp( void );
+
+/* Interrupt Timer Unit */
+/* Timer 0 */
+extern void _mtua0_isp( void );
+extern void _mtub0_isp( void );
+extern void _mtuc0_isp( void );
+extern void _mtud0_isp( void );
+extern void _mtuv0_isp( void );
+/* Timer 1 */
+extern void _mtua1_isp( void );
+extern void _mtub1_isp( void );
+extern void _mtuv1_isp( void );
+extern void _mtuu1_isp( void );
+/* Timer 2 */
+extern void _mtua2_isp( void );
+extern void _mtub2_isp( void );
+extern void _mtuv2_isp( void );
+extern void _mtuu2_isp( void );
+/* Timer 3 */
+extern void _mtua3_isp( void );
+extern void _mtub3_isp( void );
+extern void _mtuc3_isp( void );
+extern void _mtud3_isp( void );
+extern void _mtuv3_isp( void );
+/* Timer 4 */
+extern void _mtua4_isp( void );
+extern void _mtub4_isp( void );
+extern void _mtuc4_isp( void );
+extern void _mtud4_isp( void );
+extern void _mtuv4_isp( void );
+
+/* serial interfaces */
+extern void _eri0_isp( void );
+extern void _rxi0_isp( void );
+extern void _txi0_isp( void );
+extern void _tei0_isp( void );
+extern void _eri1_isp( void );
+extern void _rxi1_isp( void );
+extern void _txi1_isp( void );
+extern void _tei1_isp( void );
+
+/* ADC */
+extern void _adi0_isp( void );
+extern void _adi1_isp( void );
+
+/* Data Transfer Controller */
+extern void _dtci_isp( void );
+
+/* Compare Match Timer */
+extern void _cmt0_isp( void );
+extern void _cmt1_isp( void );
+
+/* Watchdog Timer */
+extern void _wdt_isp( void );
+
+/* DRAM refresh control unit of bus state controller */
+extern void _bsc_isp( void );
+
+/* I/O Port */
+extern void _oei_isp( void );
+
+/* Parity Control Unit of the Bus State Controllers */
+/* extern void _prt_isp( void ); */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/c/src/lib/libbsp/sh/gensh2/include/sh/io_types.h b/c/src/lib/libbsp/sh/gensh2/include/sh/io_types.h
new file mode 100644
index 0000000000..1dab885672
--- /dev/null
+++ b/c/src/lib/libbsp/sh/gensh2/include/sh/io_types.h
@@ -0,0 +1,84 @@
+/************************************************************************
+ *
+ *  Data types and constants for Hitachi SH704X on-chip peripherals
+ *
+ *  Author: John M.Mills (jmills@tga.com)
+ *
+ *  COPYRIGHT (c) 1999, TGA Technologies, Norcross, GA, USA
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *  This file may be distributed as part of the RTEMS software item.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ *
+ *      John M. Mills (jmills@tga.com)
+ *      TGA Technologies, Inc.
+ *      100 Pinnacle Way, Suite 140
+ *      Norcross, GA 30071 U.S.A.
+ *
+ *      This modified file may be copied and distributed in accordance
+ *      the above-referenced license. It is provided for critique and
+ *      developmental purposes without any warranty nor representation
+ *      by the authors or by TGA Technologies.
+ *
+ *
+ ************************************************************************/
+
+#ifndef _sh_io_types_h
+#define _sh_io_types_h
+
+#include <rtems/score/iosh7045.h>
+#include <termios.h>
+
+typedef enum {SCI0, SCI1} portNo;
+typedef enum {eight, seven} dataBits;
+typedef enum {one, two} stopBits;
+typedef enum {even, odd} parity;
+
+typedef struct {
+  portNo   line;
+  int      speed_ix;
+  dataBits dBits;
+  int      parEn;
+  parity   par;
+  int      mulPro;
+  stopBits sBits;
+} sci_setup_t;
+
+typedef union{
+	unsigned char Reg;         /* By Register */
+	struct {                   /* By  Field */
+		 unsigned char Sync  :1; /* Async/Sync */
+		 unsigned char DBts  :1; /* Char.Length */
+		 unsigned char ParEn :1; /* Parity En.*/
+		 unsigned char Odd   :1; /* Even/Odd */
+		 unsigned char SBts  :1; /* No.Stop Bits */
+		 unsigned char MulP  :1; /* Multi-Proc. */
+		 unsigned char Dvsr  :2; /* Clock Sel. */
+	} Fld;
+} sci_smr_t;
+
+typedef union {
+	unsigned char Reg;          /*  By Register */
+	struct {                    /*  By Field */
+		 unsigned char TIE :1;    /*  Tx.Int.En. */
+		 unsigned char RIE :1;    /*  Rx.Int.En. */
+		 unsigned char TE  :1;    /*  Tx.En. */
+		 unsigned char RE  :1;    /*  Rx.En. */
+		 unsigned char MPIE:1;    /*  Mult.Pro.Int.En. */
+		 unsigned char TEIE:1;    /*  Tx.End Int.En. */
+		 unsigned char CkSrc :2;   /*  Clock Src. */
+	} Fld;
+} sci_scr_t;
+
+typedef struct {
+  unsigned char n ;
+  unsigned char N ;
+} sci_bitrate_t;
+
+#endif /* _sh_io_types_h */
diff --git a/c/src/lib/libbsp/sh/gensh2/include/sh/sci.h b/c/src/lib/libbsp/sh/gensh2/include/sh/sci.h
new file mode 100644
index 0000000000..dc34371d48
--- /dev/null
+++ b/c/src/lib/libbsp/sh/gensh2/include/sh/sci.h
@@ -0,0 +1,89 @@
+/*
+ *  Driver for the sh2 704x on-chip serial devices (sci)
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef _sh_sci_h
+#define _sh_sci_h
+
+#include <rtems/libio.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Devices are set to 9600 bps, 8 databits, 1 stopbit, no
+ * parity and asynchronous mode by default.
+ *
+ * NOTE:
+ *       The onboard serial devices of the SH do not support hardware
+ *       handshake.
+ */
+
+#define DEVSCI_DRIVER_TABLE_ENTRY \
+  { sh_sci_initialize, sh_sci_open, sh_sci_close, sh_sci_read, \
+      sh_sci_write, sh_sci_control }
+
+extern rtems_device_driver sh_sci_initialize(
+  rtems_device_major_number,
+  rtems_device_minor_number,
+  void *
+);
+
+extern rtems_device_driver sh_sci_open(
+  rtems_device_major_number,
+  rtems_device_minor_number,
+  void *
+);
+
+extern rtems_device_driver sh_sci_close(
+  rtems_device_major_number,
+  rtems_device_minor_number,
+  void *
+);
+
+extern rtems_device_driver sh_sci_read(
+  rtems_device_major_number,
+  rtems_device_minor_number,
+  void *
+);
+
+extern rtems_device_driver sh_sci_write(
+  rtems_device_major_number,
+  rtems_device_minor_number,
+  void *
+);
+
+extern rtems_device_driver sh_sci_control(
+  rtems_device_major_number,
+  rtems_device_minor_number,
+  void *
+);
+
+extern const rtems_termios_callbacks * sh_sci_get_termios_handlers(
+  bool poll
+);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/c/src/lib/libbsp/sh/gensh2/include/sh/sci_termios.h b/c/src/lib/libbsp/sh/gensh2/include/sh/sci_termios.h
new file mode 100644
index 0000000000..63750c9461
--- /dev/null
+++ b/c/src/lib/libbsp/sh/gensh2/include/sh/sci_termios.h
@@ -0,0 +1,65 @@
+/*
+ *  COPYRIGHT (c) 1989-2001.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ *
+ */
+
+#ifndef _SH_SCI_TERMIOS_H_
+#define _SH_SCI_TERMIOS_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+
+int sh_sci_set_attributes(
+  int minor,
+  const struct termios *t
+);
+
+void sh_sci_initialize_interrupts(int minor);
+
+void sh_sci_init(int minor);
+
+ssize_t sh_sci_write_support_int(
+    int         minor,
+    const char *buf,
+    size_t      len
+);
+
+ssize_t sh_sci_write_support_polled(
+  int         minor,
+  const char *buf,
+  size_t      len
+);
+
+void sh_sci_write_polled(
+    int minor,
+    char c
+);
+
+int sh_sci_inbyte_nonblocking_polled(int minor);
+
+
+int sh_sci_first_open(
+  int major,
+  int minor,
+  void *arg
+);
+
+int sh_sci_last_close(
+  int major,
+  int minor,
+  void *arg
+);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _SH_SCI_TERMIOS_H_ */
diff --git a/c/src/lib/libbsp/sh/gensh2/include/sh/sh7_pfc.h b/c/src/lib/libbsp/sh/gensh2/include/sh/sh7_pfc.h
new file mode 100644
index 0000000000..b56433a9e2
--- /dev/null
+++ b/c/src/lib/libbsp/sh/gensh2/include/sh/sh7_pfc.h
@@ -0,0 +1,202 @@
+/*
+ * Bit values for the pin function controller of the Hitachi SH704x
+ *
+ * From Hitachi tutorials
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef _sh7_pfc_h
+#define _sh7_pfc_h
+
+#include <rtems/score/iosh7045.h>
+
+/*
+ * Port A IO Registers (PAIORH, PAIORL)
+ *    1 => OUTPUT
+ *    0 => INPUT
+ */
+#define PAIORH     PFC_PAIORH
+#define PAIORL     PFC_PAIORL
+
+/* PAIORH */
+#define PA23IOR    0x0080
+#define PA22IOR    0x0040
+#define PA21IOR    0x0020
+#define PA20IOR    0x0010
+#define PA19IOR    0x0008
+#define PA18IOR    0x0004
+#define PA17IOR    0x0002
+#define PA16IOR    0x0001
+
+/* PAIORL */
+#define PA15IOR    0x8000
+#define PA14IOR    0x4000
+#define PA13IOR    0x2000
+#define PA12IOR    0x1000
+#define PA11IOR    0x0800
+#define PA10IOR    0x0400
+#define PA9IOR     0x0200
+#define PA8IOR     0x0100
+#define PA7IOR     0x0080
+#define PA6IOR     0x0040
+#define PA5IOR     0x0020
+#define PA4IOR     0x0010
+#define PA3IOR     0x0008
+#define PA2IOR     0x0004
+#define PA1IOR     0x0002
+#define PA0IOR     0x0001
+
+/*
+ * Port A Control Registers (PACRH, PACRL1, PACRL2)
+ * and mode bits
+ */
+#define PACRH      PFC_PACRH
+#define PACRL1     PFC_PACRL1
+#define PACRL2     PFC_PACRL2
+
+/* PACRH */
+#define PA23MD0    0x4000
+#define PA22MD0    0x1000
+#define PA21MD0    0x0400
+#define PA20MD0    0x0100
+#define PA19MD1    0x0080
+#define PA19MD0    0x0040
+#define PA18MD1    0x0020
+#define PA18MD0    0x0010
+#define PA17MD0    0x0004
+#define PA16MD0    0x0001
+
+/* PACRL1 */
+#define PA15MD0    0x4000
+#define PA14MD0    0x1000
+#define PA13MD0    0x0400
+#define PA12MD0    0x0100
+#define PA11MD0    0x0040
+#define PA10MD0    0x0010
+#define PA9MD1     0x0008
+#define PA9MD0     0x0004
+#define PA8MD1     0x0002
+#define PA8MD0     0x0001
+
+/* PACRL2 */
+#define PA7MD1     0x8000
+#define PA7MD0     0x4000
+#define PA6MD1     0x2000
+#define PA6MD0     0x1000
+#define PA5MD1     0x0800
+#define PA5MD0     0x0400
+#define PA4MD0     0x0100
+#define PA3MD0     0x0040
+#define PA2MD1     0x0020
+#define PA2MD0     0x0010
+#define PA1MD0     0x0004
+#define PA0MD0     0x0001
+
+#define PA_TXD1    PA4MD0
+#define PA_RXD1    PA3MD0
+#define PA_TXD0    PA1MD0
+#define PA_RXD0    PA0MD0
+
+/*
+ * Port B IO Register (PBIOR)
+ */
+#define PBIOR      PFC_PBIOR
+#define PB15IOR    0x8000
+#define PB14IOR    0x4000
+#define PB13IOR    0x2000
+#define PB12IOR    0x1000
+#define PB11IOR    0x0800
+#define PB10IOR    0x0400
+#define PB9IOR     0x0200
+#define PB8IOR     0x0100
+#define PB7IOR     0x0080
+#define PB6IOR     0x0040
+#define PB5IOR     0x0020
+#define PB4IOR     0x0010
+#define PB3IOR     0x0008
+#define PB2IOR     0x0004
+#define PB1IOR     0x0002
+#define PB0IOR     0x0001
+
+/*
+ * Port B Control Register (PBCR1)
+ */
+#define PBCR1      PFC_PBCR1
+#define PB15MD1    0x8000
+#define PB15MD0    0x4000
+#define PB14MD1    0x2000
+#define PB14MD0    0x1000
+#define PB13MD1    0x0800
+#define PB13MD0    0x0400
+#define PB12MD1    0x0200
+#define PB12MD0    0x0100
+#define PB11MD1    0x0080
+#define PB11MD0    0x0040
+#define PB10MD1    0x0020
+#define PB10MD0    0x0010
+#define PB9MD1     0x0008
+#define PB9MD0     0x0004
+#define PB8MD1     0x0002
+#define PB8MD0     0x0001
+
+#define PB15MD     PB15MD1|PB14MD0
+#define PB14MD     PB14MD1|PB14MD0
+#define PB13MD     PB13MD1|PB13MD0
+#define PB12MD     PB12MD1|PB12MD0
+#define PB11MD     PB11MD1|PB11MD0
+#define PB10MD     PB10MD1|PB10MD0
+#define PB9MD      PB9MD1|PB9MD0
+#define PB8MD      PB8MD1|PB8MD0
+
+#define PB_TXD1    PB11MD1
+#define PB_RXD1    PB10MD1
+#define PB_TXD0    PB9MD1
+#define PB_RXD0    PB8MD1
+
+/*
+ * Port B Control Register (PBCR2)
+ */
+#define PBCR2      PFC_PBCR2
+#define PB7MD1     0x8000
+#define PB7MD0     0x4000
+#define PB6MD1     0x2000
+#define PB6MD0     0x1000
+#define PB5MD1     0x0800
+#define PB5MD0     0x0400
+#define PB4MD1     0x0200
+#define PB4MD0     0x0100
+#define PB3MD1     0x0080
+#define PB3MD0     0x0040
+#define PB2MD1     0x0020
+#define PB2MD0     0x0010
+#define PB1MD1     0x0008
+#define PB1MD0     0x0004
+#define PB0MD1     0x0002
+#define PB0MD0     0x0001
+
+#define PB7MD      PB7MD1|PB7MD0
+#define PB6MD      PB6MD1|PB6MD0
+#define PB5MD      PB5MD1|PB5MD0
+#define PB4MD      PB4MD1|PB4MD0
+#define PB3MD      PB3MD1|PB3MD0
+#define PB2MD      PB2MD1|PB2MD0
+#define PB1MD      PB1MD1|PB1MD0
+#define PB0MD      PB0MD1|PB0MD0
+
+#endif /* _sh7_pfc_h */
diff --git a/c/src/lib/libbsp/sh/gensh2/include/sh/sh7_sci.h b/c/src/lib/libbsp/sh/gensh2/include/sh/sh7_sci.h
new file mode 100644
index 0000000000..7218313704
--- /dev/null
+++ b/c/src/lib/libbsp/sh/gensh2/include/sh/sh7_sci.h
@@ -0,0 +1,88 @@
+/*
+ * Bit values for the serial control registers of the Hitachi SH704X
+ *
+ * From Hitachi tutorials
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef _sh7_sci_h
+#define _sh7_sci_h
+
+#include <rtems/score/iosh7045.h>
+
+/*
+ * Serial mode register bits
+ */
+
+#define SCI_SYNC_MODE               0x80
+#define SCI_SEVEN_BIT_DATA          0x40
+#define SCI_PARITY_ON               0x20
+#define SCI_ODD_PARITY              0x10
+#define SCI_STOP_BITS_2             0x08
+#define SCI_ENABLE_MULTIP           0x04
+#define SCI_PHI_64                  0x03
+#define SCI_PHI_16                  0x02
+#define SCI_PHI_4                   0x01
+#define SCI_PHI_0                   0x00
+
+/*
+ * Serial register offsets, relative to SCI0_SMR or SCI1_SMR
+ */
+
+#define SCI_SMR			0x00
+#define SCI_BRR			0x01
+#define SCI_SCR			0x02
+#define SCI_TDR			0x03
+#define SCI_SSR			0x04
+#define SCI_RDR			0x05
+
+/*
+ * Serial control register bits
+ */
+#define SCI_TIE                 0x80    /* Transmit interrupt enable */
+#define SCI_RIE                 0x40    /* Receive interrupt enable */
+#define SCI_TE                  0x20    /* Transmit enable */
+#define SCI_RE                  0x10    /* Receive enable */
+#define SCI_MPIE                0x08    /* Multiprocessor interrupt enable */
+#define SCI_TEIE                0x04    /* Transmit end interrupt enable */
+#define SCI_CKE1                0x02    /* Clock enable 1 */
+#define SCI_CKE0                0x01    /* Clock enable 0 */
+
+/*
+ * Serial status register bits
+ */
+#define SCI_TDRE                0x80    /* Transmit data register empty */
+#define SCI_RDRF                0x40    /* Receive data register full */
+#define SCI_ORER                0x20    /* Overrun error */
+#define SCI_FER                 0x10    /* Framing error */
+#define SCI_PER                 0x08    /* Parity error */
+#define SCI_TEND                0x04    /* Transmit end */
+#define SCI_MPB                 0x02    /* Multiprocessor bit */
+#define SCI_MPBT                0x01    /* Multiprocessor bit transfer */
+
+/*
+ * INTC Priority Settings
+ */
+
+#define SCI0_IPMSK	0x00F0
+#define SCI0_LOWIP	0x0010
+#define SCI1_IPMSK	0x000F
+#define SCI1_LOWIP	0x0001
+
+#endif /* _sh7_sci_h */
diff --git a/c/src/lib/libbsp/sh/gensh2/make/custom/gensh2.cfg b/c/src/lib/libbsp/sh/gensh2/make/custom/gensh2.cfg
index 40038e6b9b..49cf0850d2 100644
--- a/c/src/lib/libbsp/sh/gensh2/make/custom/gensh2.cfg
+++ b/c/src/lib/libbsp/sh/gensh2/make/custom/gensh2.cfg
@@ -9,7 +9,6 @@
 include $(RTEMS_ROOT)/make/custom/default.cfg
 
 RTEMS_CPU=sh
-RTEMS_CPU_MODEL=sh7045
 
 #  This contains the compiler options necessary to select the CPU model
 #  and (hopefully) optimize for it.
diff --git a/c/src/lib/libbsp/sh/gensh2/preinstall.am b/c/src/lib/libbsp/sh/gensh2/preinstall.am
index 2570e1a313..742998fee3 100644
--- a/c/src/lib/libbsp/sh/gensh2/preinstall.am
+++ b/c/src/lib/libbsp/sh/gensh2/preinstall.am
@@ -28,6 +28,16 @@ $(PROJECT_INCLUDE)/$(dirstamp):
 	@: > $(PROJECT_INCLUDE)/$(dirstamp)
 PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
 
+$(PROJECT_INCLUDE)/sh/$(dirstamp):
+	@$(MKDIR_P) $(PROJECT_INCLUDE)/sh
+	@: > $(PROJECT_INCLUDE)/sh/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/sh/$(dirstamp)
+
+$(PROJECT_INCLUDE)/rtems/score/$(dirstamp):
+	@$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score
+	@: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+
 $(PROJECT_INCLUDE)/bsp/$(dirstamp):
 	@$(MKDIR_P) $(PROJECT_INCLUDE)/bsp
 	@: > $(PROJECT_INCLUDE)/bsp/$(dirstamp)
@@ -45,6 +55,34 @@ $(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
 
+$(PROJECT_INCLUDE)/sh/io_types.h: include/sh/io_types.h $(PROJECT_INCLUDE)/sh/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/sh/io_types.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/sh/io_types.h
+
+$(PROJECT_INCLUDE)/sh/sci.h: include/sh/sci.h $(PROJECT_INCLUDE)/sh/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/sh/sci.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/sh/sci.h
+
+$(PROJECT_INCLUDE)/sh/sh7_pfc.h: include/sh/sh7_pfc.h $(PROJECT_INCLUDE)/sh/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/sh/sh7_pfc.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/sh/sh7_pfc.h
+
+$(PROJECT_INCLUDE)/sh/sh7_sci.h: include/sh/sh7_sci.h $(PROJECT_INCLUDE)/sh/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/sh/sh7_sci.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/sh/sh7_sci.h
+
+$(PROJECT_INCLUDE)/sh/sci_termios.h: include/sh/sci_termios.h $(PROJECT_INCLUDE)/sh/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/sh/sci_termios.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/sh/sci_termios.h
+
+$(PROJECT_INCLUDE)/rtems/score/ispsh7045.h: include/rtems/score/ispsh7045.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/ispsh7045.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/ispsh7045.h
+
+$(PROJECT_INCLUDE)/rtems/score/iosh7045.h: include/rtems/score/iosh7045.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/iosh7045.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/iosh7045.h
+
 $(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h
diff --git a/c/src/lib/libbsp/sh/gensh2/startup/cpu_asm.c b/c/src/lib/libbsp/sh/gensh2/startup/cpu_asm.c
new file mode 100644
index 0000000000..47bc859dbd
--- /dev/null
+++ b/c/src/lib/libbsp/sh/gensh2/startup/cpu_asm.c
@@ -0,0 +1,182 @@
+/*
+ *  This file contains the basic algorithms for all assembly code used
+ *  in an specific CPU port of RTEMS.  These algorithms must be implemented
+ *  in assembly language
+ *
+ *  NOTE:  This port uses a C file with inline assembler instructions
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+/*
+ *  This is supposed to be an assembly file.  This means that system.h
+ *  and cpu.h should not be included in a "real" cpu_asm file.  An
+ *  implementation in assembly should include "cpu_asm.h"
+ */
+
+#include <rtems/system.h>
+#include <rtems/score/cpu.h>
+#include <rtems/score/isr.h>
+#include <rtems/score/threaddispatch.h>
+#include <rtems/score/sh.h>
+
+#include <rtems/score/ispsh7045.h>
+#include <rtems/score/iosh7045.h>
+#include <rtems/score/sh_io.h>
+
+/* from cpu_isps.c */
+extern proc_ptr         _Hardware_isr_Table[];
+
+#if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+  unsigned long    *_old_stack_ptr;
+#endif
+
+register unsigned long  *stack_ptr __asm__ ("r15");
+
+/*
+ * sh_set_irq_priority
+ *
+ * this function sets the interrupt level of the specified interrupt
+ *
+ * parameters:
+ *             - irq : interrupt number
+ *             - prio: priority to set for this interrupt number
+ *
+ * returns:    0 if ok
+ *             -1 on error
+ */
+
+unsigned int sh_set_irq_priority(
+  unsigned int irq,
+  unsigned int prio )
+{
+  uint32_t   shiftcount;
+  uint32_t   prioreg;
+  uint16_t   temp16;
+  ISR_Level  level;
+
+  /*
+   * first check for valid interrupt
+   */
+  if (( irq > 156) || (irq < 64) || (_Hardware_isr_Table[irq] == _dummy_isp))
+    return -1;
+  /*
+   * check for valid irq priority
+   */
+  if ( prio > 15 )
+    return -1;
+
+  /*
+   * look up appropriate interrupt priority register
+   */
+  if ( irq > 71)
+    {
+      irq = irq - 72;
+      shiftcount = 12 - ((irq & ~0x03) % 16);
+
+      switch( irq / 16)
+	{
+	case 0: { prioreg = INTC_IPRC; break;}
+	case 1: { prioreg = INTC_IPRD; break;}
+	case 2: { prioreg = INTC_IPRE; break;}
+	case 3: { prioreg = INTC_IPRF; break;}
+	case 4: { prioreg = INTC_IPRG; break;}
+	case 5: { prioreg = INTC_IPRH; break;}
+	default: return -1;
+	}
+    }
+  else
+    {
+      shiftcount = 12 - 4 * ( irq % 4);
+      if ( irq > 67)
+	prioreg = INTC_IPRB;
+      else
+	prioreg = INTC_IPRA;
+    }
+
+  /*
+   * Set the interrupt priority register
+   */
+  _ISR_Local_disable( level );
+
+    temp16 = read16( prioreg);
+    temp16 &= ~( 15 << shiftcount);
+    temp16 |= prio << shiftcount;
+    write16( temp16, prioreg);
+
+  _ISR_Local_enable( level );
+
+  return 0;
+}
+
+/*
+ *  This routine provides the RTEMS interrupt management.
+ */
+
+void __ISR_Handler( uint32_t   vector)
+{
+  ISR_Level level;
+
+  _ISR_Local_disable( level );
+
+  _Thread_Dispatch_disable();
+
+#if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+  if ( _ISR_Nest_level == 0 )
+    {
+      /* Install irq stack */
+      _old_stack_ptr = stack_ptr;
+      stack_ptr = _CPU_Interrupt_stack_high;
+    }
+
+#endif
+
+  _ISR_Nest_level++;
+
+  _ISR_Local_enable( level );
+
+  /* call isp */
+  if ( _ISR_Vector_table[ vector])
+    (*_ISR_Vector_table[ vector ])( vector );
+
+  _ISR_Local_disable( level );
+
+  _Thread_Dispatch_unnest( _Per_CPU_Get() );
+
+  _ISR_Nest_level--;
+
+#if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+
+  if ( _ISR_Nest_level == 0 )
+    /* restore old stack pointer */
+    stack_ptr = _old_stack_ptr;
+#endif
+
+  _ISR_Local_enable( level );
+
+  if ( _ISR_Nest_level )
+    return;
+
+  if ( !_Thread_Dispatch_is_enabled() ) {
+    return;
+  }
+
+  if ( _Thread_Dispatch_necessary ) {
+    _Thread_Dispatch();
+  }
+}
diff --git a/c/src/lib/libbsp/sh/gensh2/startup/ispsh7045.c b/c/src/lib/libbsp/sh/gensh2/startup/ispsh7045.c
new file mode 100644
index 0000000000..bb0f9dc666
--- /dev/null
+++ b/c/src/lib/libbsp/sh/gensh2/startup/ispsh7045.c
@@ -0,0 +1,311 @@
+/*
+ * This file contains the isp frames for the user interrupts.
+ * From these procedures __ISR_Handler is called with the vector number
+ * as argument.
+ *
+ * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in
+ * some releases of gcc doesn't properly handle #pragma interrupt, if a
+ * file contains both isrs and normal functions.
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
+ *
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ *
+ *	Modified to reflect isp entries for sh7045 processor:
+ *	John M. Mills (jmills@tga.com)
+ *	TGA Technologies, Inc.
+ *      100 Pinnacle Way, Suite 140
+ *	Norcross, GA 30071 U.S.A.
+ *	August, 1999
+ *
+ *	This modified file may be copied and distributed in accordance
+ *	the above-referenced license. It is provided for critique and
+ *	developmental purposes without any warranty nor representation
+ *	by the authors or by TGA Technologies.
+ */
+
+#include <rtems/system.h>
+#include <rtems/score/types.h>
+
+/*
+ * This is a exception vector table
+ *
+ * It has the same structure as the actual vector table (vectab)
+ */
+
+
+/* SH-2 ISR Table */
+#include <rtems/score/ispsh7045.h>
+
+proc_ptr _Hardware_isr_Table[256]={
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,		/* PWRon Reset, Maual Reset,...*/
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp,
+_nmi_isp, _usb_isp,                               /* irq 11, 12*/
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp,
+/* trapa 0 -31 */
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp,   /* external H/W: irq 64-71 */
+_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp,
+_dma0_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* DMAC: irq 72-87*/
+_dma1_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dma2_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dma3_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_mtua0_isp, _mtub0_isp, _mtuc0_isp, _mtud0_isp, /* MTUs: irq 88-127 */
+_mtuv0_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_mtua1_isp, _mtub1_isp, _dummy_isp, _dummy_isp,
+_mtuv1_isp, _mtuu1_isp, _dummy_isp, _dummy_isp,
+_mtua2_isp, _mtub2_isp, _dummy_isp, _dummy_isp,
+_mtuv2_isp, _mtuu2_isp, _dummy_isp, _dummy_isp,
+_mtua3_isp, _mtub3_isp, _mtuc3_isp, _mtud3_isp,
+_mtuv3_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_mtua4_isp, _mtub4_isp, _mtuc4_isp, _mtud4_isp,
+_mtuv4_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp, /* SCI0-1: irq 128-135*/
+_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp,
+_adi0_isp, _adi1_isp, _dummy_isp, _dummy_isp, /* ADC0-1: irq 136-139*/
+_dtci_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* DTU: irq 140-143 */
+_cmt0_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* CMT0-1: irq 144-151 */
+_cmt1_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_wdt_isp, /* WDT: irq 152*/
+_bsc_isp, _dummy_isp, _dummy_isp, /* BSC: irq 153-155*/
+_oei_isp, /* I/O Port: irq 156*/
+};
+
+#define Str(a)#a
+
+/*
+ * Some versions of gcc and all version of egcs at least until egcs-1.1b
+ * are not able to handle #pragma interrupt correctly if more than 1 isr is
+ * contained in a file and when optimizing.
+ * We try to work around this problem by using the macro below.
+ */
+#define isp( name, number, func)\
+__asm__ (".global _"Str(name)"\n\t"\
+     "_"Str(name)":       \n\t"\
+     "    mov.l r0,@-r15   \n\t"\
+     "    mov.l r1,@-r15   \n\t"\
+     "    mov.l r2,@-r15   \n\t"\
+     "    mov.l r3,@-r15   \n\t"\
+     "    mov.l r4,@-r15   \n\t"\
+     "    mov.l r5,@-r15   \n\t"\
+     "    mov.l r6,@-r15   \n\t"\
+     "    mov.l r7,@-r15   \n\t"\
+     "    mov.l r14,@-r15  \n\t"\
+     "    sts.l pr,@-r15   \n\t"\
+     "    sts.l mach,@-r15 \n\t"\
+     "    sts.l macl,@-r15 \n\t"\
+     "    mov r15,r14      \n\t"\
+     "    mov.l "Str(name)"_v, r2 \n\t"\
+     "    mov.l "Str(name)"_k, r1\n\t"\
+     "    jsr @r1           \n\t"\
+     "    mov   r2,r4      \n\t"\
+     "    mov   r14,r15    \n\t"\
+     "    lds.l @r15+,macl \n\t"\
+     "    lds.l @r15+,mach \n\t"\
+     "    lds.l @r15+,pr   \n\t"\
+     "    mov.l @r15+,r14  \n\t"\
+     "    mov.l @r15+,r7   \n\t"\
+     "    mov.l @r15+,r6   \n\t"\
+     "    mov.l @r15+,r5   \n\t"\
+     "    mov.l @r15+,r4   \n\t"\
+     "    mov.l @r15+,r3   \n\t"\
+     "    mov.l @r15+,r2   \n\t"\
+     "    mov.l @r15+,r1   \n\t"\
+     "    mov.l @r15+,r0   \n\t"\
+     "    rte              \n\t"\
+     "    nop              \n\t"\
+     "    .align 2         \n\t"\
+     #name"_k: \n\t"\
+     ".long "Str(func)"\n\t"\
+     #name"_v: \n\t"\
+     ".long "Str(number));
+
+/************************************************
+ * Dummy interrupt service procedure for
+ * interrupts being not allowed --> Trap 34
+ ************************************************/
+__asm__ (" .section .text\n\
+.global __dummy_isp\n\
+__dummy_isp:\n\
+      mov.l r14,@-r15\n\
+      mov   r15, r14\n\
+      trapa #34\n\
+      mov.l @r15+,r14\n\
+      rte\n\
+      nop");
+
+/*******************************************************************
+ *     ISP Vector Table for sh7045 family of processors            *
+ *******************************************************************/
+
+
+/*****************************
+ * Non maskable interrupt
+ *****************************/
+isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * User break controller
+ *****************************/
+isp( _usb_isp, USB_ISP_V, ___ISR_Handler);
+
+/*****************************
+ *  External interrupts 0-7
+ *****************************/
+isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler);
+isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler);
+isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler);
+isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler);
+isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler);
+isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler);
+isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler);
+isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * DMA - controller
+ *****************************/
+isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler);
+isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler);
+isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler);
+isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler);
+
+
+/*****************************
+ * Match timer unit
+ *****************************/
+
+/*****************************
+ * Timer 0
+ *****************************/
+isp( _mtua0_isp, MTUA0_ISP_V, ___ISR_Handler);
+isp( _mtub0_isp, MTUB0_ISP_V, ___ISR_Handler);
+isp( _mtuc0_isp, MTUC0_ISP_V, ___ISR_Handler);
+isp( _mtud0_isp, MTUD0_ISP_V, ___ISR_Handler);
+isp( _mtuv0_isp, MTUV0_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Timer 1
+ *****************************/
+isp( _mtua1_isp, MTUA1_ISP_V, ___ISR_Handler);
+isp( _mtub1_isp, MTUB1_ISP_V, ___ISR_Handler);
+isp( _mtuv1_isp, MTUV1_ISP_V, ___ISR_Handler);
+isp( _mtuu1_isp, MTUU1_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Timer 2
+ *****************************/
+isp( _mtua2_isp, MTUA2_ISP_V, ___ISR_Handler);
+isp( _mtub2_isp, MTUB2_ISP_V, ___ISR_Handler);
+isp( _mtuv2_isp, MTUV2_ISP_V, ___ISR_Handler);
+isp( _mtuu2_isp, MTUU2_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Timer 3
+ *****************************/
+isp( _mtua3_isp, MTUA3_ISP_V, ___ISR_Handler);
+isp( _mtub3_isp, MTUB3_ISP_V, ___ISR_Handler);
+isp( _mtuc3_isp, MTUC3_ISP_V, ___ISR_Handler);
+isp( _mtud3_isp, MTUD3_ISP_V, ___ISR_Handler);
+isp( _mtuv3_isp, MTUV3_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Timer 4
+ *****************************/
+isp( _mtua4_isp, MTUA4_ISP_V, ___ISR_Handler);
+isp( _mtub4_isp, MTUB4_ISP_V, ___ISR_Handler);
+isp( _mtuc4_isp, MTUC4_ISP_V, ___ISR_Handler);
+isp( _mtud4_isp, MTUD4_ISP_V, ___ISR_Handler);
+isp( _mtuv4_isp, MTUV4_ISP_V, ___ISR_Handler);
+
+
+/*****************************
+ * Serial interfaces
+ *****************************/
+
+/*****************************
+ * Serial interface 0
+ *****************************/
+isp( _eri0_isp,  ERI0_ISP_V, ___ISR_Handler);
+isp( _rxi0_isp,  RXI0_ISP_V, ___ISR_Handler);
+isp( _txi0_isp,  TXI0_ISP_V, ___ISR_Handler);
+isp( _tei0_isp,  TEI0_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Serial interface 1
+ *****************************/
+isp( _eri1_isp,  ERI1_ISP_V, ___ISR_Handler);
+isp( _rxi1_isp,  RXI1_ISP_V, ___ISR_Handler);
+isp( _txi1_isp,  TXI1_ISP_V, ___ISR_Handler);
+isp( _tei1_isp,  TEI1_ISP_V, ___ISR_Handler);
+
+
+/******************************
+ * A/D converters
+ * ADC0-1
+ ******************************/
+isp( _adi0_isp,  ADI0_ISP_V, ___ISR_Handler);
+isp( _adi1_isp,  ADI1_ISP_V, ___ISR_Handler);
+
+
+/******************************
+ *  Data transfer controller
+ ******************************/
+isp( _dtci_isp,  DTC_ISP_V, ___ISR_Handler);
+
+
+/******************************
+ *  Counter match timer
+ ******************************/
+isp( _cmt0_isp,  CMT0_ISP_V, ___ISR_Handler);
+isp( _cmt1_isp,  CMT1_ISP_V, ___ISR_Handler);
+
+
+/******************************
+ *  Watchdog timer
+ ******************************/
+isp( _wdt_isp,  WDT_ISP_V, ___ISR_Handler);
+
+
+/******************************
+ * DRAM refresh control unit
+ * of bus state controller
+ ******************************/
+isp( _bsc_isp,  CMI_ISP_V, ___ISR_Handler);
+
+/******************************
+ *  I/O port
+ ******************************/
+isp( _oei_isp,  OEI_ISP_V, ___ISR_Handler);
+
+
+/*****************************
+ * Parity control unit of
+ * the bus state controller
+ * NOT PROVIDED IN SH-2
+ *****************************/
+/* isp( _prt_isp,  PRT_ISP_V, ___ISR_Handler); */
diff --git a/c/src/lib/libbsp/sh/gensh2/timer/timer.c b/c/src/lib/libbsp/sh/gensh2/timer/timer.c
new file mode 100644
index 0000000000..152c99b1aa
--- /dev/null
+++ b/c/src/lib/libbsp/sh/gensh2/timer/timer.c
@@ -0,0 +1,191 @@
+/**
+ *  @file
+ *  @brief Timer for the Hitachi SH 704X
+ */
+
+/*
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+#include <rtems/btimer.h>
+
+#include <rtems/score/sh_io.h>
+#include <rtems/score/iosh7045.h>
+
+extern uint32_t bsp_clicks_per_second;
+
+/*
+ *  We use a Phi/4 timer
+ */
+#define SCALE (Timer_MHZ/4)
+
+#define MTU1_STARTMASK 	0xfd
+#define MTU1_SYNCMASK 	0xfd
+#define MTU1_MODEMASK 	0xc0
+#define MTU1_TCRMASK 	0x01
+#define MTU1_TIORMASK 	0x88
+#define MTU1_STAT_MASK 	0xf8
+#define MTU1_TIERMASK 	0xfc
+#define IPRC_MTU1_MASK	0xfff0
+
+#ifndef MTU1_PRIO
+#define MTU1_PRIO 15
+#endif
+
+#define MTU1_VECTOR 86
+
+extern rtems_isr timerisr(void);
+
+static uint32_t   Timer_interrupts;
+
+bool benchmark_timer_find_average_overhead;
+
+static uint32_t   Timer_MHZ ;
+
+void benchmark_timer_initialize( void )
+{
+  uint8_t                temp8;
+  uint16_t               temp16;
+  rtems_interrupt_level  level;
+  rtems_isr	        *ignored;
+
+  Timer_MHZ = bsp_clicks_per_second / 1000000 ;
+
+  /*
+   *  Timer has never overflowed.  This may not be necessary on some
+   *  implemenations of timer but ....
+   */
+
+  Timer_interrupts /* .i */ = 0;
+  rtems_interrupt_disable( level );
+
+  /*
+   *  Somehow start the timer
+   */
+  /* stop Timer 1  */
+  temp8 = read8(MTU_TSTR) & MTU1_STARTMASK;
+  write8( temp8, MTU_TSTR );
+
+  /* initialize counter 1 */
+  write16( 0, MTU_TCNT1);
+
+  /* Timer 1 is independent of other timers */
+  temp8 = read8(MTU_TSYR) & MTU1_SYNCMASK;
+  write8( temp8, MTU_TSYR );
+
+  /* Timer 1, normal mode */
+  temp8 = read8(MTU_TMDR1) & MTU1_MODEMASK;
+  write8( temp8, MTU_TMDR1 );
+
+  /* x0000000
+   * |||||+++--- Internal Clock
+   * |||++------ Count on rising edge
+   * |++-------- disable TCNT clear
+   * +---------- don`t care
+   */
+  write8( MTU1_TCRMASK, MTU_TCR1 );
+
+  /* gra and grb are not used */
+  write8( MTU1_TIORMASK, MTU_TIOR1 );
+
+  /* reset all status flags */
+  temp8 = read8(MTU_TSR1) & MTU1_STAT_MASK;
+  write8( temp8, MTU_TSR1 );
+
+  /* enable overflow interrupt */
+  write8( MTU1_TIERMASK, MTU_TIER1 );
+
+  /* set interrupt priority */
+  temp16 = read16(INTC_IPRC) & IPRC_MTU1_MASK;
+  temp16 |= MTU1_PRIO;
+  write16( temp16, INTC_IPRC);
+
+  /* initialize ISR */
+  _CPU_ISR_install_raw_handler( MTU1_VECTOR, timerisr, &ignored );
+  rtems_interrupt_enable( level );
+
+  /* start timer 1 */
+  temp8 = read8(MTU_TSTR) | ~MTU1_STARTMASK;
+  write8( temp8, MTU_TSTR );
+}
+
+/*
+ *  The following controls the behavior of benchmark_timer_read().
+ *
+ *  AVG_OVERHEAD is the overhead for starting and stopping the timer.  It
+ *  is usually deducted from the number returned.
+ *
+ *  LEAST_VALID is the lowest number this routine should trust.  Numbers
+ *  below this are "noise" and zero is returned.
+ */
+
+#define AVG_OVERHEAD      1  /* It typically takes X.X microseconds */
+                             /* (Y countdowns) to start/stop the timer. */
+                             /* This value is in microseconds. */
+#define LEAST_VALID       0 /* 20 */ /* Don't trust a clicks value lower than this */
+
+benchmark_timer_t benchmark_timer_read( void )
+{
+  uint32_t   clicks;
+  uint32_t   total ;
+  /*
+   *  Read the timer and see how many clicks it has been since we started.
+   */
+
+
+  clicks = read16( MTU_TCNT1 );   /* XXX: read some HW here */
+
+  /*
+   *  Total is calculated by taking into account the number of timer overflow
+   *  interrupts since the timer was initialized and clicks since the last
+   *  interrupts.
+   */
+
+  total = clicks + Timer_interrupts * 65536;
+
+  if ( benchmark_timer_find_average_overhead )
+    return total / SCALE;          /* in XXX microsecond units */
+  else
+  {
+    if ( total < LEAST_VALID )
+      return 0;            /* below timer resolution */
+  /*
+   *  Somehow convert total into microseconds
+   */
+    return (total / SCALE - AVG_OVERHEAD) ;
+  }
+}
+
+void benchmark_timer_disable_subtracting_average_overhead(bool find_flag)
+{
+  benchmark_timer_find_average_overhead = find_flag;
+}
+
+/* Timer 1 is used */
+
+#pragma interrupt
+void timerisr( void )
+{
+  uint8_t   temp8;
+
+  /* reset the flags of the status register */
+  temp8 = read8(MTU_TSR1) & MTU1_STAT_MASK;
+  write8( temp8, MTU_TSR1 );
+
+  Timer_interrupts += 1;
+}