diff options
author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2001-10-11 19:04:12 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2001-10-11 19:04:12 +0000 |
commit | 96462044ce9a80c6caed1ce06466cbc2ae911780 (patch) | |
tree | 87d3d5b5547f9fcece8f49403b9ab1e2a6c6f56d /c/src/lib/libbsp/sh/gensh4/include/sdram.h | |
parent | 2001-10-11 Alexandra Kossovsky <sasha@oktet.ru> (diff) | |
download | rtems-96462044ce9a80c6caed1ce06466cbc2ae911780.tar.bz2 |
2001-10-11 Alexandra Kossovsky <sasha@oktet.ru>
* Makefile.am, README, bsp_specs, .cvsignore, include/Makefile.am,
include/bsp.h, include/coverhd.h, include/sdram.h, include/.cvsignore,
start/Makefile.am, start/start.S, start/.cvsignore, startup/Makefile.am,
startup/bspstart.c, startup/linkcmds, startup/linkcmds.rom,
startup/linkcmds.rom2ram, startup/.cvsignore, wrapup/Makefile.am,
wrapup/.cvsignore, hw_init/Makefile.am, hw_init/hw_init.c,
hw_init/.cvsignore, times, configure.ac: New files.
Reviewed and updated to latest automake and autoconf standards
by Ralf Corsepius <corsepiu@faw.uni-ulm.de>.
Diffstat (limited to 'c/src/lib/libbsp/sh/gensh4/include/sdram.h')
-rw-r--r-- | c/src/lib/libbsp/sh/gensh4/include/sdram.h | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/sh/gensh4/include/sdram.h b/c/src/lib/libbsp/sh/gensh4/include/sdram.h new file mode 100644 index 0000000000..ae9d7f2f99 --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh4/include/sdram.h @@ -0,0 +1,42 @@ +/* + * SDRAM Mode Register + * Based on Fujitsu MB81F643242B data sheet. + * + * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia + * Author: Victor V. Vengerov <vvv@oktet.ru> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * @(#) $Id$ + */ + +#ifndef __SDRAM_H__ +#define __SDRAM_H__ + +/* SDRAM Mode Register */ +#define SDRAM_MODE_BL 0x0007 /* Burst Length: */ +#define SDRAM_MODE_BL_1 0x0000 /* 0 */ +#define SDRAM_MODE_BL_2 0x0001 /* 2 */ +#define SDRAM_MODE_BL_4 0x0002 /* 4 */ +#define SDRAM_MODE_BL_8 0x0003 /* 8 */ +#define SDRAM_MODE_BL_16 0x0004 /* 16 */ +#define SDRAM_MODE_BL_32 0x0005 /* 32 */ +#define SDRAM_MODE_BL_64 0x0006 /* 64 */ +#define SDRAM_MODE_BL_FULL 0x0007 /* Full column */ + +#define SDRAM_MODE_BT 0x0008 /* Burst Type: */ +#define SDRAM_MODE_BT_SEQ 0x0000 /* Sequential */ +#define SDRAM_MODE_BT_ILV 0x0008 /* Interleave */ + +#define SDRAM_MODE_CL 0x0070 /* CAS Latency: */ +#define SDRAM_MODE_CL_1 0x0010 /* 1 */ +#define SDRAM_MODE_CL_2 0x0020 /* 2 */ +#define SDRAM_MODE_CL_3 0x0030 /* 3 */ + +#define SDRAM_MODE_OPC 0x0200 /* Opcode: */ +#define SDRAM_MODE_OPC_BRBW 0x0000 /* Burst read & Burst write */ +#define SDRAM_MODE_OPC_BRSW 0x0200 /* Burst read & Single write */ + +#endif |