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authorHesham Almatary <hesham@alumni.york.ac.uk>2017-10-21 18:06:44 +1100
committerHesham Almatary <heshamelmatary@gmail.com>2017-10-28 18:41:42 +1100
commit6d85e0514409aaed17711bd2bff04f1a0b0bbc83 (patch)
treeeb782ca584c80783d39ee4afbc58c19821b82440 /c/src/lib/libbsp/riscv32/riscv_generic/include/bsp.h
parentcpukit: Add basic riscv32 architecture port v3 (diff)
downloadrtems-6d85e0514409aaed17711bd2bff04f1a0b0bbc83.tar.bz2
bsp: Add new riscv_generic bsp v3
* Only runs/tested on simulator/spike. * Ticker, hello, capture work proprely * Tested via RTEMS Tester, Passed: 525/565 (92%) Update #3109
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+/*
+ *
+ * Copyright (c) 2015 University of York.
+ * Hesham Almatary <hesham@alumni.york.ac.uk>
+ *
+ * COPYRIGHT (c) 1989-1999.
+ * On-Line Applications Research Corporation (OAR).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_RISCV_GENERIC_H
+#define LIBBSP_RISCV_GENERIC_H
+
+#include <rtems.h>
+#include <rtems/clockdrv.h>
+#include <rtems/console.h>
+
+#include <bspopts.h>
+#include <bsp/default-initial-extension.h>
+
+#include <rtems/devnull.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup riscv_generic Register Definitions
+ *
+ * @ingroup riscv_generic
+ *
+ * @brief Shared register definitions for RISC-V systems.
+ *
+ * @{
+ */
+
+/**
+ * @name Register Macros
+ *
+ * @{
+ */
+
+#define REG(x) (*((volatile uint32_t *) (x)))
+#define BIT(n) (1 << (n))
+
+#define MTIME_MM 0x0200bff8
+#define MTIMECMP_MM 0x02004000
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LIBBSP_RISCV_GENERIC_H */