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author | Joel Sherrill <joel.sherrill@OARcorp.com> | 1998-08-14 15:23:33 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 1998-08-14 15:23:33 +0000 |
commit | db8e8a8bef387995463877994896b8bd8a9c8f2a (patch) | |
tree | e38536510a4a8f84339dd3b003e6a8cb43cc10fc /c/src/lib/libbsp/powerpc | |
parent | Updated. (diff) | |
download | rtems-db8e8a8bef387995463877994896b8bd8a9c8f2a.tar.bz2 |
Added information on caching.
Diffstat (limited to 'c/src/lib/libbsp/powerpc')
-rw-r--r-- | c/src/lib/libbsp/powerpc/dmv177/QUIRKS | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/powerpc/dmv177/QUIRKS b/c/src/lib/libbsp/powerpc/dmv177/QUIRKS index ecba090340..e1d95e6427 100644 --- a/c/src/lib/libbsp/powerpc/dmv177/QUIRKS +++ b/c/src/lib/libbsp/powerpc/dmv177/QUIRKS @@ -4,6 +4,19 @@ # $Id$ # +JTAG and Caching +================ +If data or code caching is enabled on certain revisions of the PPC603e, +then the JTAG emulator interface become disfunctional. You can not +debug using the emulator on these chip revisions. On certain revisions, +it is so bad that when code caching is enabled, you can not even +download code reliably to the board. + +Caching and Peripherals +======================= +When caching is enabled, care must be exercised to insure that all +peripheral addresses are still uncached. + Exar 88681 Clock ================ This board uses a different clock for the Exar 88681 DUART than is |