BSP for Vista Score603e added.

6 files changed, 1393 insertions, 0 deletions

diff --git a/c/src/lib/libbsp/powerpc/score603e/console/85c30.c b/c/src/lib/libbsp/powerpc/score603e/console/85c30.c
new file mode 100644
index 0000000000..d95246c074
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/score603e/console/85c30.c
@@ -0,0 +1,434 @@
+/*
+ *  This file contains the console driver chip level routines for the 
+ *  z85c30 chip.
+ *
+ *  Currently only polled mode is supported.
+ *
+ *  COPYRIGHT (c) 1989-1997.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id: 
+ */
+
+#include <rtems.h>
+#include <bsp.h>
+#include <rtems/libio.h>
+#include <assert.h>
+
+#include "85c30.h"
+#include "consolebsp.h"
+
+#define STATUS_REGISTER     0x00
+#define DATA_REGISTER       0x08
+
+
+#define Z8530_Status_Is_RX_character_available( _status ) \
+  ( (_status) & 0x01 )
+
+#define Z8530_Status_Is_TX_buffer_empty( _status ) \
+  ( (_status) & 0x04 )
+
+#define Z8530_Status_Is_break_abort( _status ) \
+  ( (_status) & 0x80 )
+
+typedef struct {
+  unsigned char read_setup;
+  unsigned char write_setup;
+  unsigned char mask_value;
+} char_size_info;
+
+static const char_size_info Char_size_85c30[] = {
+  { Z8530_READ_CHARACTER_BITS_8, Z8530_WRITE_CHARACTER_BITS_8, 0xFF }, 
+  { Z8530_READ_CHARACTER_BITS_7, Z8530_WRITE_CHARACTER_BITS_7, 0x7F }, 
+  { Z8530_READ_CHARACTER_BITS_6, Z8530_WRITE_CHARACTER_BITS_6, 0x3F }, 
+  { Z8530_READ_CHARACTER_BITS_5, Z8530_WRITE_CHARACTER_BITS_5, 0x1F }
+};
+
+static const unsigned char Clock_speed_85c30[] = { 
+  Z8530_x1_CLOCK, Z8530_x16_CLOCK, Z8530_x32_CLOCK,  Z8530_x64_CLOCK };
+
+static const unsigned char Stop_bit_85c30[] = { 
+  Z8530_STOP_BITS_1, Z8530_STOP_BITS_1_AND_A_HALF, Z8530_STOP_BITS_2 };
+
+static const unsigned char Parity_85c30[] = { 
+  Z8530_PARITY_NONE, Z8530_PARITY_ODD, Z8530_PARITY_EVEN };
+
+
+/* PAGE
+ *
+ * Read_85c30_register
+ *
+ * Read a Z85c30 register
+ */
+static unsigned char Read_85c30_register( 
+  volatile unsigned char *csr,                        /* IN  */
+  unsigned char  register_number                      /* IN  */
+)
+{
+  unsigned char Data;
+ 
+  *csr = register_number; 
+
+  delay_in_bus_cycles( 40 );
+
+  Data = *csr;
+  
+  delay_in_bus_cycles( 40 );
+
+  return Data;
+}
+
+/*
+ * Write_85c30_register
+ *
+ *  Write a Z85c30 register
+ */
+static void  Write_85c30_register(
+  volatile unsigned char  *csr,                     /* IN  */
+  unsigned char  register_number,                   /* IN  */
+  unsigned char  data                               /* IN  */
+)
+{
+  *csr = register_number;
+
+  delay_in_bus_cycles( 40 );
+
+  *csr = data;
+
+  delay_in_bus_cycles( 40 );
+}
+
+
+/* PAGE
+ *
+ *  Reset_85c30_chip
+ *
+ *  Reset a 85c30 chip.  The pointers for the control registers for both
+ *  ports on the chip are used as input.
+ */
+void Reset_85c30_chip(
+  volatile unsigned char *ctrl_0,                     /* IN  */
+  volatile unsigned char *ctrl_1                      /* IN  */
+)
+{
+  Write_85c30_register( ctrl_0, 0x09, 0x80 );
+  Write_85c30_register( ctrl_1, 0x09, 0x40 );
+}
+ 
+
+/* PAGE
+ *
+ * initialize_85c30_port
+ *
+ * initialize a z85c30 Port
+ */
+void initialize_85c30_port(
+  const Port_85C30_info *Port
+)
+{
+  rtems_unsigned16        value;
+  volatile unsigned char *ctrl;
+  Console_Protocol        *Setup;
+  rtems_unsigned16        baud_constant;
+
+  Setup = Port->Protocol;
+  ctrl  = Port->ctrl;
+
+  baud_constant = _Score603e_Z8530_Baud( Port->Chip->clock_frequency, 
+    Port->Chip->clock_x, Setup->baud_rate );
+
+  /*
+   * Using register 4
+   * Set up the clock rate.
+   */
+  value = Clock_speed_85c30[ Port->Chip->clock_speed ] |
+          Stop_bit_85c30[ Setup->stop_bits ] |
+          Parity_85c30[ Setup->parity ];
+  Write_85c30_register( ctrl, 0x04, value );
+
+  /*
+   *  Set Write Register 1 to disable all interrupts
+   */
+  Write_85c30_register( ctrl, 1, 0 );
+
+#if CONSOLE_USE_INTERRUPTS
+  /*
+   *  Set Write Register 2 to contain the interrupt vector
+   */
+  Write_85c30_register( ctrl, 2, Port->Chip->vector );
+#endif
+
+  /*
+   *  Set Write Register 3 to disable the Receiver
+   */
+  Write_85c30_register( ctrl, 0x03, 0x00 );
+
+  /*
+   *  Set Write Register 5 to disable the Transmitter
+   */
+  Write_85c30_register( ctrl, 5, 0x00 );
+
+  /* WR 6 -- unneeded in asynchronous mode */
+
+  /* WR 7 -- unneeded in asynchronous mode */
+
+  /*
+   *  Set Write Register 9 to disable all interrupt sources
+   */
+  Write_85c30_register( ctrl, 9, 0x00 );
+
+  /*
+   *  Set Write Register 10 for simple Asynchronous operation
+   */
+  Write_85c30_register( ctrl, 0x0a, 0x00 );
+
+  /*
+   * Setup the source of the receive and xmit
+   * clock as BRG output and the transmit clock
+   * as the output source for TRxC pin via register 11
+   */
+  Write_85c30_register( ctrl, 0x0b, 0x56 );
+
+  value = baud_constant;
+
+  /*
+   * Setup the lower 8 bits time constants = 1E.
+   * If the time constans = 1E, then the desire
+   * baud rate will be equilvalent to 9600, via register 12.
+   */
+  Write_85c30_register( ctrl, 0x0c, value & 0xff );
+
+  /*
+   * using register 13
+   * Setup the upper 8 bits time constants = 0
+   */
+  Write_85c30_register( ctrl, 0x0d, value>>8 );
+
+  /*
+   * Set the DTR/REQ pin goes low when transmit
+   * buffer becomes empty and enable the baud
+   * rate generator enable with clock from the
+   * SCC's PCLK input via register 14.
+   */
+  Write_85c30_register( ctrl, 0x0e, 0x07 );
+
+  /*
+   *  Set Write Register 3 : Base Value is xx00_000x
+   *     D6 - D7 : Receive Character Length               (configured)
+   *     D5      : Auto Enable                            (forced value)
+   *     D4      : Enter Hunt Phase                       (forced value)
+   *     D3      : Receive CRC Enable                     (forced value)
+   *     D2      : Address Search Mode (0 if not SDLC)    (forced value)
+   *     D1      : Sync Character Load Inhibit            (forced value)
+   *     D0      : Receiver Enable                        (configured)
+   */
+  value = 0x01;
+  value = value | Char_size_85c30[ Setup->read_char_bits ].read_setup;
+
+  Write_85c30_register( ctrl, 0x03, value );
+
+  /*
+   *  Set Write Register 5 : Base Value is 0xx0_x000
+   *     D7      : Data Terminal Ready (DTR)              (forced value)
+   *     D5 - D6 : Transmit Character Length              (configured)
+   *     D4      : Send Break                             (forced value)
+   *     D3      : Transmitter Enable                     (configured)
+   *     D2      : CRC Select                             (forced value)
+   *     D1      : Request to Send                        (forced value)
+   *     D0      : Transmit CRC Enable                    (forced value)
+   */
+  value = 0x8a;
+  value = value |  Char_size_85c30[ Setup->write_char_bits ].write_setup;
+  Write_85c30_register( ctrl, 0x05, value );
+ 
+  /*
+   * Reset Tx UNDERRUN/EOM LATCH and ERROR
+   * via register 0 
+   */
+   Write_85c30_register( ctrl, 0x00, 0xf0 );
+ 
+#if CONSOLE_USE_INTERRUPTS
+  /*
+   *  Set Write Register 1 to interrupt on Rx characters or special condition.
+   */
+  Write_85c30_register( ctrl, 1, 0x10 );
+#endif
+
+  /*
+   *  Set Write Register 15 to disable extended functions.
+   */
+
+  Write_85c30_register( ctrl, 15, 0x00 );
+
+  /*
+   *  Set the Command Register to Reset Ext/STATUS.
+   */
+  Write_85c30_register( ctrl, 0x00, 0x10 );
+
+#if CONSOLE_USE_INTERRUPTS
+
+  /*
+   *  Set Write Register 1 : Base Value is 0001_0110
+   *    Enables Rx interrupt on all characters and special conditions.
+   *    Enables parity as a special condition.
+   *    Enables Tx interrupt.
+   */
+  Write_85c30_register( ctrl, 1, 0x16 );
+
+  /*
+   *  Set Write Register 9 to enable all interrupt sources
+   *  Changed from 0 to a
+   */
+  Write_85c30_register( ctrl, 9, 0x0A );
+
+
+  /* XXX */
+
+  /*
+   *  Issue reset highest Interrupt Under Service (IUS) command.
+   */
+  Write_85c30_register( Port->ctrl, STATUS_REGISTER, 0x38 );
+
+#endif
+
+}
+
+/* PAGE
+ *
+ *  outbyte_polled_85c30
+ *
+ *  This routine transmits a character using polling.
+ */
+
+void outbyte_polled_85c30(
+  volatile unsigned char  *csr,                     /* IN  */
+  char ch                                           /* IN  */
+)
+{
+  unsigned char       z8530_status;
+  rtems_unsigned32    isrlevel;
+ 
+  rtems_interrupt_disable( isrlevel );
+
+  /*
+   * Wait for the Transmit buffer to indicate that it is empty.
+   */
+  do {
+    z8530_status = Read_85c30_register( csr, STATUS_REGISTER );
+  } while ( !Z8530_Status_Is_TX_buffer_empty( z8530_status ) );
+
+  /*
+   * Write the character.
+   */
+  Write_85c30_register( csr, DATA_REGISTER, (unsigned char) ch ); 
+
+  rtems_interrupt_enable( isrlevel );
+}
+
+/* PAGE
+ *
+ *  inbyte_nonblocking_85c30
+ *
+ *  This routine polls for a character.
+ */
+
+int inbyte_nonblocking_85c30(   
+  const Port_85C30_info      *Port
+)
+{
+  volatile unsigned char  *csr;
+  unsigned char   z8530_status;
+  rtems_unsigned8 data;
+
+  csr = Port->ctrl;
+
+  /*
+   * return -1 if a character is not available.
+   */
+  z8530_status = Read_85c30_register( csr, STATUS_REGISTER );
+  if ( !Z8530_Status_Is_RX_character_available( z8530_status ) )
+    return -1;
+  
+  /*
+   * Return the character read.
+   */
+  data = Read_85c30_register( csr, DATA_REGISTER );
+  data &= Char_size_85c30[ Port->Protocol->read_char_bits ].mask_value;
+
+  return data;
+}
+
+
+/*
+ *  Interrupt driven console IO
+ */
+
+#if CONSOLE_USE_INTERRUPTS
+
+/*PAGE
+ *
+ *  Z8530_Async_Channel_ISR
+ *
+ */
+/* RR0 */
+
+rtems_isr ISR_85c30_Async(
+   const Port_85C30_info   *Port
+)
+{
+  rtems_unsigned16           status;
+  volatile Console_Protocol *Protocol;
+  unsigned char              data;
+  rtems_boolean              did_something = FALSE;
+
+  Protocol = Port->Protocol;
+
+  status = Read_85c30_register( Port->ctrl, 0x00 );
+
+  /*
+   *  Was this a RX interrupt?  If so, then process it.
+   */
+
+  if ( Z8530_Status_Is_RX_character_available( status ) ) {
+    data = Read_85c30_register( Port->ctrl, DATA_REGISTER );
+    data &= Char_size_85c30[ Port->Protocol->read_char_bits ].mask_value;
+    
+    rtems_termios_enqueue_raw_characters( Port->Protocol->console_termios_data,
+       &data, 1 );
+    did_something = TRUE;
+  }
+
+  /*
+   *  Was this a TX empty interrupt?  If so, then process it.
+   */
+
+  if (Z8530_Status_Is_TX_buffer_empty( status ) ) {
+    if ( !Ring_buffer_Is_empty( &Protocol->TX_Buffer ) ) {
+      Ring_buffer_Remove_character( &Protocol->TX_Buffer, data );
+      Write_85c30_register( Port->ctrl, DATA_REGISTER, data );
+
+    } else {
+      Protocol->Is_TX_active = FALSE;
+      Write_85c30_register( Port->ctrl, STATUS_REGISTER, 0x28 );
+    }
+
+    did_something = TRUE;
+  }
+
+  /*
+   *  Issue reset highest Interrupt Under Service (IUS) command.
+   */
+
+  /*
+   if ( did_something )
+   */
+     Write_85c30_register( Port->ctrl, STATUS_REGISTER, 0x38 );
+}
+
+#endif
+
diff --git a/c/src/lib/libbsp/powerpc/score603e/console/85c30.h b/c/src/lib/libbsp/powerpc/score603e/console/85c30.h
new file mode 100644
index 0000000000..cacdfd0bb9
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/score603e/console/85c30.h
@@ -0,0 +1,56 @@
+/*  85c30.h
+ *
+ *  This include file contains z85c30 chip information. 
+ *
+ *  COPYRIGHT (c) 1989-1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may in
+ *  the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id: 
+ */
+
+#ifndef __85c30_H
+#define __85c30_H
+
+/*
+ * Clock Speed Definations
+ */
+ 
+#define Z8530_x1_CLOCK                        0x00
+#define Z8530_x16_CLOCK                       0x40
+#define Z8530_x32_CLOCK                       0x80
+#define Z8530_x64_CLOCK                       0xC0
+
+/*
+ * Number of Stop Bits.
+ */
+#define Z8530_STOP_BITS_1                     0x04
+#define Z8530_STOP_BITS_1_AND_A_HALF          0x08
+#define Z8530_STOP_BITS_2                     0x0C
+
+/*
+ * PARITY
+ */
+#define Z8530_PARITY_NONE                     0x00
+#define Z8530_PARITY_ODD                      0x01
+#define Z8530_PARITY_EVEN                     0x03
+
+/*
+ * Character Bits
+ */
+#define Z8530_READ_CHARACTER_BITS_8           0xC0
+#define Z8530_READ_CHARACTER_BITS_7           0x40
+#define Z8530_READ_CHARACTER_BITS_6           0x80
+#define Z8530_READ_CHARACTER_BITS_5           0x00
+
+#define Z8530_WRITE_CHARACTER_BITS_8          0x60
+#define Z8530_WRITE_CHARACTER_BITS_7          0x20
+#define Z8530_WRITE_CHARACTER_BITS_6          0x40
+#define Z8530_WRITE_CHARACTER_BITS_5          0x00
+
+#endif
+
diff --git a/c/src/lib/libbsp/powerpc/score603e/console/Makefile.in b/c/src/lib/libbsp/powerpc/score603e/console/Makefile.in
new file mode 100644
index 0000000000..f0a1233ce6
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/score603e/console/Makefile.in
@@ -0,0 +1,56 @@
+#
+#  $Id$
+#
+
+@SET_MAKE@
+srcdir = @srcdir@
+VPATH = @srcdir@
+RTEMS_ROOT = @top_srcdir@
+PROJECT_ROOT = @PROJECT_ROOT@
+
+INSTALL = @INSTALL@
+
+PGM=${ARCH}/console.rel
+
+# C source names, if any, go here -- minus the .c
+C_PIECES=85c30 console tbl85c30
+C_FILES=$(C_PIECES:%=%.c)
+C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
+
+H_FILES=
+
+SRCS=$(C_FILES) $(H_FILES)
+OBJS=$(C_O_FILES)
+
+include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
+include $(RTEMS_ROOT)/make/leaf.cfg
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+DEFINES  +=
+CPPFLAGS +=
+CFLAGS   +=
+
+LD_PATHS  +=
+LD_LIBS   +=
+LDFLAGS   +=
+
+#
+# Add your list of files to delete here.  The config files
+#  already know how to delete some stuff, so you may want
+#  to just run 'make clean' first to see what gets missed.
+#  'make clobber' already includes 'make clean'
+#
+
+CLEAN_ADDITIONS +=
+CLOBBER_ADDITIONS +=
+
+${PGM}: ${SRCS} ${OBJS}
+	$(make-rel)
+
+all:	${ARCH} $(SRCS) $(PGM)
+
+# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile
+install:  all
diff --git a/c/src/lib/libbsp/powerpc/score603e/console/console.c b/c/src/lib/libbsp/powerpc/score603e/console/console.c
new file mode 100644
index 0000000000..a3836bd6a8
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/score603e/console/console.c
@@ -0,0 +1,497 @@
+/*
+ *  This file contains the TTY driver for the serial ports on the SCORE603e.
+ *
+ *  This driver uses the termios pseudo driver.
+ *
+ *  Currently only polled mode is supported.
+ *
+ *  COPYRIGHT (c) 1989-1997.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#include <bsp.h>
+#include <rtems/libio.h>
+#include <stdlib.h>
+#include <assert.h>
+
+#include "consolebsp.h"
+
+#if (1)
+/*
+ * The Port Used for the Console interface is based upon which 
+ * debugger is being used.  The SDS debugger uses a binary 
+ * interface on port 0 as part of the debugger.  Thus port 0 can
+ * not be used as the console port for the SDS debugger.
+ */
+
+#if (SCORE603E_USE_SDS)
+#define USE_FOR_CONSOLE_DEF  1
+
+#elif (SCORE603E_USE_OPEN_FIRMWARE)
+#define USE_FOR_CONSOLE_DEF  0
+
+#elif (SCORE603E_USE_NONE)
+#define USE_FOR_CONSOLE_DEF  0
+
+#elif (SCORE603E_USE_DINK)
+#define USE_FOR_CONSOLE_DEF  0
+
+#else
+#error "SCORE603E CONSOLE.C -- what ROM monitor are you using"
+#endif
+
+#endif
+
+#if (0)
+extern int USE_FOR_CONSOLE;
+#endif
+
+int USE_FOR_CONSOLE = USE_FOR_CONSOLE_DEF;
+
+/*
+ *
+ *  Console Device Driver Entry Points
+ */
+ 
+/* PAGE
+ *
+ *  DEBUG_puts
+ *
+ *  This should be safe in the event of an error.  It attempts to insure
+ *  that no TX empty interrupts occur while it is doing polled IO.  Then
+ *  it restores the state of that external interrupt.
+ *
+ *  Input parameters:
+ *    string  - pointer to debug output string
+ *
+ *  Output parameters:  NONE
+ *
+ *  Return values:      NONE
+ */
+
+void DEBUG_puts(
+  char *string
+)
+{
+  char *s;
+  int   console;
+  volatile rtems_unsigned8 *csr;
+
+  console = USE_FOR_CONSOLE;
+
+  csr = Ports_85C30[ console ].ctrl;
+
+  /* should disable interrupts here */
+
+  for ( s = string ; *s ; s++ ) 
+    outbyte_polled_85c30( csr, *s );
+
+  outbyte_polled_85c30( csr, '\r' );
+  outbyte_polled_85c30( csr, '\n' );
+
+  /* should enable interrupts here */
+}
+
+/* PAGE
+ *
+ *  console_inbyte_nonblocking 
+ *
+ *  Console Termios polling input entry point.
+ */
+
+int console_inbyte_nonblocking( 
+  int minor 
+)
+{
+  int                       port = minor;
+
+  /* 
+   * verify port Number 
+   */
+  assert ( port < NUM_Z85C30_PORTS );
+ 
+  /*
+   * return a character from the 85c30 port.
+   */
+  return inbyte_nonblocking_85c30( &Ports_85C30[ port ] );
+}
+
+ 
+void console_reserve_resources(
+  rtems_configuration_table *configuration
+)
+{
+  rtems_termios_reserve_resources( configuration, NUM_Z85C30_PORTS );
+}
+
+
+rtems_device_driver console_close(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void                    * arg
+)
+{
+  return rtems_termios_close (arg);
+}
+ 
+rtems_device_driver console_read(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void                    * arg
+)
+{
+  return rtems_termios_read (arg);
+}
+ 
+rtems_device_driver console_write(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void                    * arg
+)
+{
+  return rtems_termios_write (arg);
+}
+ 
+rtems_device_driver console_control(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void                    * arg
+)
+{
+  return rtems_termios_ioctl (arg);
+}
+
+
+
+/*
+ *  Interrupt driven console IO
+ */
+
+#if CONSOLE_USE_INTERRUPTS
+
+rtems_isr console_isr(
+  rtems_vector_number vector
+)
+{
+  int  i;
+  
+  for (i=0; i < NUM_Z85C30_PORTS; i++){
+      ISR_85c30_Async( &Ports_85C30[i] );
+
+#if (0) /* XXX - TO TEST LOOP BACKS comment this out. */
+    if ( Ports_85C30[i].Chip->vector == vector ) {
+      ISR_85c30_Async( &Ports_85C30[i] );
+    }
+#endif
+  }  
+}
+
+void console_exit()
+{
+  int i;
+  volatile Ring_buffer_t *buffer;
+  rtems_unsigned32 ch;
+
+  for ( i=0 ; i < NUM_Z85C30_PORTS ; i++ ) {
+    
+    buffer = &( Ports_85C30[i].Protocol->TX_Buffer);
+
+    while ( !Ring_buffer_Is_empty( buffer ) ) {
+      Ring_buffer_Remove_character( buffer, ch );
+      outbyte_polled_85c30( Ports_85C30[i].ctrl, ch ); 
+    }
+  }
+}
+
+void console_initialize_interrupts( void )
+{
+  volatile Ring_buffer_t     *buffer;
+  Console_Protocol  *protocol;
+  int               i;
+  
+  for ( i=0 ; i < NUM_Z85C30_PORTS ; i++ ) {
+    protocol = Ports_85C30[i].Protocol;
+
+    /*
+     * Initialize the ring buffer and set to not transmitting.
+     */
+    buffer = &protocol->TX_Buffer;
+    Ring_buffer_Initialize( buffer );
+    protocol->Is_TX_active = FALSE;
+  }
+
+  /* 
+   * Connect each vector to the interupt service routine.
+   */
+  for (i=0; i < NUM_Z85C30_CHIPS; i++)
+    set_vector( console_isr, Chips_85C30[i].vector, 1 );
+  
+
+  atexit( console_exit );
+   
+}
+void console_outbyte_interrupts(
+  const Port_85C30_info *Port,
+  char ch
+);
+
+/* XXXXXX */
+#endif
+
+
+/* PAGE
+ *
+ *  console_initialize
+ *
+ *  Routine called to initialize the console device driver.
+ */
+rtems_device_driver console_initialize(
+  rtems_device_major_number  major,
+  rtems_device_minor_number  minor,
+  void                      *arg
+)
+{
+  rtems_status_code          status;
+  rtems_device_minor_number  console;
+  int                        port, chip, p0,p1;
+
+  /*
+   * initialize the termio interface.
+   */
+  rtems_termios_initialize();
+
+  /*
+   *  Register Device Names
+   */
+  console = USE_FOR_CONSOLE;
+  status = rtems_io_register_name( "/dev/console", major, console );
+  if (status != RTEMS_SUCCESSFUL)
+    rtems_fatal_error_occurred(status);
+
+  /*
+   *  Initialize Hardware
+   */
+
+
+/*
+ * INITIALIZE_COM_PORTS is defined in the linker script.  If it is
+ * true all serial chips on the board are to be reset at startup
+ * otherwise the reset is assumed to occur elsewhere (ie. in the
+ * debugger...)
+ */
+#if ( INITIALIZE_COM_PORTS )
+
+  /*
+   * Force to perform a hardware reset w/o
+   * Master interrupt enable via register 9
+   */
+  
+  for (port=0; port<NUM_Z85C30_PORTS; port++){
+    p0 = port;
+    port++;
+    p1 = port;
+    Reset_85c30_chip( Ports_85C30[p0].ctrl, Ports_85C30[p1].ctrl );
+  }
+#else
+  /* TEMP - To see if this makes a diff with the new ports. 
+   *        Never reset chip 1 when using the chip as a monitor
+   */
+  for (port=2; port<NUM_Z85C30_PORTS; port++){
+    p0 = port;
+    port++;
+    p1 = port;
+    Reset_85c30_chip( Ports_85C30[p0].ctrl, Ports_85C30[p1].ctrl );
+  }
+#endif
+
+  /* 
+   * Initialize each port.
+   * Note:  the ports are numbered such that 0,1 are on the first chip
+   *        2,3 are on the second ....
+   */
+
+  for (port=0; port<NUM_Z85C30_PORTS; port++) {
+    chip = port >> 1;
+    initialize_85c30_port( &Ports_85C30[port] );
+  }
+
+#if CONSOLE_USE_INTERRUPTS
+  console_initialize_interrupts();
+#endif
+
+  return RTEMS_SUCCESSFUL;
+}
+
+/* PAGE
+ *
+ *  console_write_support
+ *
+ *  Console Termios output entry point.
+ *
+ */
+int console_write_support(
+  int   minor, 
+  const char *buf, 
+  int   len)
+{
+  int nwrite = 0;
+  volatile rtems_unsigned8 *csr;
+  int                       port = minor;
+
+  /* 
+   * verify port Number 
+   */
+  assert ( port < NUM_Z85C30_PORTS );
+
+  /*
+   * Set the csr based upon the port number.
+   */
+  csr = Ports_85C30[ port ].ctrl;
+
+  /*
+   * poll each byte in the string out of the port.
+   */
+  while (nwrite < len) {
+#if (CONSOLE_USE_INTERRUPTS)
+    console_outbyte_interrupts( &Ports_85C30[ port ], *buf++ );
+#else
+    outbyte_polled_85c30( csr, *buf++ );
+#endif
+   nwrite++;
+  }
+
+  /*
+   * return the number of bytes written.
+   */
+  return nwrite;
+}
+
+/* PAGE
+ *
+ *  console_open
+ *
+ *  open a port as a termios console.
+ *
+ */
+rtems_device_driver console_open(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void                    * arg
+)
+{
+  rtems_status_code sc;
+  int               port = minor;
+#if (CONSOLE_USE_INTERRUPTS)
+  rtems_libio_open_close_args_t *args = arg;
+  static const rtems_termios_callbacks intrCallbacks = {
+    NULL,                       /* firstOpen */
+    NULL,                       /* lastClose */
+    NULL,                       /* pollRead */
+    console_write_support,      /* write */
+    NULL,                       /* setAttributes */
+    NULL,                       /* stopRemoteTx */
+    NULL,                       /* startRemoteTx */
+    1                           /* outputUsesInterrupts */
+  };
+#else
+  static const rtems_termios_callbacks pollCallbacks = {
+    NULL,                       /* firstOpen */
+    NULL,                       /* lastClose */
+    console_inbyte_nonblocking, /* pollRead */
+    console_write_support,      /* write */
+    NULL,                       /* setAttributes */
+    NULL,                       /* stopRemoteTx */
+    NULL,                       /* startRemoteTx */
+    0                           /* outputUsesInterrupts */
+  };
+#endif
+
+
+  /*
+   * Verify the minor number is valid.
+   */
+  if (minor < 0)
+    return RTEMS_INVALID_NUMBER;
+
+  if ( port > NUM_Z85C30_PORTS )
+     return RTEMS_INVALID_NUMBER;
+
+  /*
+   *  open the port as a termios console driver.
+   */
+
+#if (CONSOLE_USE_INTERRUPTS)
+   sc = rtems_termios_open( major, minor, arg, &intrCallbacks );
+
+   Ports_85C30[ minor ].Protocol->console_termios_data = args->iop->data1;
+#else
+   sc = rtems_termios_open( major, minor, arg, &pollCallbacks );
+#endif
+
+  return sc;
+}
+
+
+#if (CONSOLE_USE_INTERRUPTS)
+
+/*
+ *  console_outbyte_interrupts
+ *
+ *  This routine transmits a character out.
+ *
+ *  Input parameters:
+ *    port - port to transmit character to
+ *    ch  - character to be transmitted
+ *
+ *  Output parameters:  NONE
+ *
+ *  Return values:      NONE
+ */
+void console_outbyte_interrupts(
+  const Port_85C30_info *Port,
+  char ch
+)
+{
+  Console_Protocol   *protocol;
+  rtems_unsigned32    isrlevel;
+
+  protocol = Port->Protocol;
+  
+  /*
+   *  If this is the first character then we need to prime the pump
+   */
+
+  if ( protocol->Is_TX_active == FALSE ) {
+
+    rtems_interrupt_disable( isrlevel );
+    protocol->Is_TX_active = TRUE;
+    outbyte_polled_85c30( Port->ctrl, ch );
+    rtems_interrupt_enable( isrlevel );
+
+    return;
+  }
+
+  while ( Ring_buffer_Is_full( &protocol->TX_Buffer ) );
+ 
+  Ring_buffer_Add_character( &protocol->TX_Buffer, ch );
+}
+
+#endif
+
+
+
+
+
+
+
+
+
+
+
diff --git a/c/src/lib/libbsp/powerpc/score603e/console/consolebsp.h b/c/src/lib/libbsp/powerpc/score603e/console/consolebsp.h
new file mode 100644
index 0000000000..2c5016890c
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/score603e/console/consolebsp.h
@@ -0,0 +1,152 @@
+/*  consolebsp.h
+ *
+ *  This include file contains all console driver definations
+ *
+ *  COPYRIGHT (c) 1989-1997.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may in
+ *  the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id: 
+ */
+
+#ifndef __CONSOLEBSP_H
+#define __CONSOLEBSP_H
+
+#include <rtems.h>
+#include <ringbuf.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*
+ *
+ * Note:  The Ports are numbered 0..NUM_Z85C30_CHIPS with port 0 and 1 
+ *        being on the first chip, and ports 2 and 3 being on the 
+ *        second chip...
+ */
+
+ 
+/*
+ * Z85c30 configuration informaiton.
+ */
+
+#if (HAS_PMC_PSC8)
+#define NUM_Z85C30_CHIPS_ON_MEZZANINE  4
+#else
+#define NUM_Z85C30_CHIPS_ON_MEZZANINE  0
+#endif
+
+#define NUM_Z85C30_CHIPS       (2 + NUM_Z85C30_CHIPS_ON_MEZZANINE)
+#define NUM_Z85C30_PORTS       (NUM_Z85C30_CHIPS * 2)
+
+typedef enum {
+  CONSOLE_x1_CLOCK,
+  CONSOLE_x16_CLOCK,
+  CONSOLE_x32_CLOCK,
+  CONSOLE_x64_CLOCK,
+} CONSOLE_Clock_speed;
+
+typedef enum {
+  CONSOLE_STOP_BITS_1,
+  CONSOLE_STOP_BITS_1_AND_A_HALF,
+  CONSOLE_STOP_BITS_2,
+} CONSOLE_Stop_bits;
+
+typedef enum {
+  CONSOLE_PARITY_NONE,
+  CONSOLE_PARITY_ODD,
+  CONSOLE_PARITY_EVEN,  
+} CONSOLE_Parity;
+
+typedef enum {
+  CONSOLE_CHARACTER_BITS_8,
+  CONSOLE_CHARACTER_BITS_7,
+  CONSOLE_CHARACTER_BITS_6,
+  CONSOLE_CHARACTER_BITS_5,
+} CONSOLE_Character_bits;
+
+typedef struct {
+  rtems_unsigned32        baud_rate;         /* baud rate value */
+  CONSOLE_Stop_bits        stop_bits;         
+  CONSOLE_Parity           parity;
+  CONSOLE_Character_bits   read_char_bits;
+  CONSOLE_Character_bits   write_char_bits;
+
+#if CONSOLE_USE_INTERRUPTS
+  volatile Ring_buffer_t  TX_Buffer;         /* Transmit Buffer    */
+  volatile rtems_boolean  Is_TX_active;      /* Transmitting       */
+  void          *console_termios_data;
+#endif
+
+} Console_Protocol; 
+
+
+/*
+ * Structure used for chip level information.
+ */
+typedef struct {
+  rtems_unsigned32       vector;
+  rtems_unsigned32       clock_frequency;
+  rtems_unsigned16       clock_x;
+  CONSOLE_Clock_speed     clock_speed;
+} Chip_85C30_info;
+
+/*
+ * Structure used for port level informaiton.
+ */
+typedef struct {
+
+  volatile unsigned char    *ctrl;           /* Port Ctrl byte     */
+  volatile unsigned char    *data;           /* Port data byte     */
+
+  unsigned char              port;          /* Port-id / minor #  */
+
+  Console_Protocol          *Protocol;
+  Chip_85C30_info           *Chip;           /* Chip specific info */
+
+} Port_85C30_info;
+
+/*
+ * Console port chip configuration tables. 
+ */
+extern Chip_85C30_info Chips_85C30 [ NUM_Z85C30_CHIPS ];
+extern const Port_85C30_info Ports_85C30 [ NUM_Z85C30_PORTS ];
+
+
+/*
+ *  85c30.c prototypes.
+ */
+void initialize_85c30_port(
+  const Port_85C30_info *Port
+);
+
+void outbyte_polled_85c30(
+  volatile unsigned char  *csr,                     /* IN  */
+  char ch
+);
+
+int inbyte_nonblocking_85c30(   
+  const Port_85C30_info      *Port
+);
+
+void Reset_85c30_chip(
+  volatile unsigned char *ctrl_0,
+  volatile unsigned char *ctrl_1
+);
+
+#if CONSOLE_USE_INTERRUPTS
+rtems_isr ISR_85c30_Async(
+   const Port_85C30_info   *Port
+);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/c/src/lib/libbsp/powerpc/score603e/console/tbl85c30.c b/c/src/lib/libbsp/powerpc/score603e/console/tbl85c30.c
new file mode 100644
index 0000000000..349f669fc8
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/score603e/console/tbl85c30.c
@@ -0,0 +1,198 @@
+ /*
+ *  This file contains the table for the z85c30 port 
+ *  used by the console driver.
+ *
+ *  COPYRIGHT (c) 1989-1997.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id: 
+ */
+
+#include "consolebsp.h"
+#include <bsp.h>
+
+#define CONSOLE_DEFAULT_BAUD_RATE            9600
+#define CONSOLE_DEFAULT_BAUD_CONSTANT        Score603e_Z8530_Chip0_Baud(9600)
+                                             
+#define CONSOLE_DEFAULT_STOP_BITS            CONSOLE_STOP_BITS_1    
+#define CONSOLE_DEFAULT_PARITY               CONSOLE_PARITY_NONE          
+#define CONSOLE_DEFAULT_READ_CHARACTER_BITS  CONSOLE_CHARACTER_BITS_8
+#define CONSOLE_DEFAULT_WRITE_CHARACTER_BITS CONSOLE_CHARACTER_BITS_8
+#define CONSOLE_DEFAULT_CONSOLE_CLOCK        CONSOLE_x16_CLOCK
+
+
+#define DEFAULT_PROTOCOL  { CONSOLE_DEFAULT_BAUD_RATE,              \
+                            CONSOLE_DEFAULT_STOP_BITS,              \
+                            CONSOLE_DEFAULT_PARITY,                 \
+                            CONSOLE_DEFAULT_READ_CHARACTER_BITS,    \
+                            CONSOLE_DEFAULT_WRITE_CHARACTER_BITS }
+
+/*
+ * Tables of information necessary to use the console 85c30 routines.
+ */
+Console_Protocol Protocols_85c30 [ NUM_Z85C30_PORTS ] = 
+{
+  DEFAULT_PROTOCOL,
+  DEFAULT_PROTOCOL,
+  DEFAULT_PROTOCOL,
+  DEFAULT_PROTOCOL,
+
+#if (HAS_PMC_PSC8)
+  DEFAULT_PROTOCOL,
+  DEFAULT_PROTOCOL,
+  DEFAULT_PROTOCOL,
+  DEFAULT_PROTOCOL,
+  DEFAULT_PROTOCOL,
+  DEFAULT_PROTOCOL,
+  DEFAULT_PROTOCOL,
+  DEFAULT_PROTOCOL,
+#endif
+};
+
+/*
+ * Table of chip unique information for each chip.
+ * See consolebsp.h for the Chip_85C30_info structure defination.
+ */
+Chip_85C30_info Chips_85C30 [ NUM_Z85C30_CHIPS ] =
+{
+  {
+    SCORE603E_85C30_0_IRQ,
+    SCORE603E_85C30_0_CLOCK,
+    SCORE603E_85C30_0_CLOCK_X,
+    CONSOLE_DEFAULT_CONSOLE_CLOCK
+  }, 
+  { 
+    SCORE603E_85C30_1_IRQ,
+    SCORE603E_85C30_1_CLOCK,
+    SCORE603E_85C30_1_CLOCK_X,
+    CONSOLE_DEFAULT_CONSOLE_CLOCK
+  },
+
+#if (HAS_PMC_PSC8)
+  { 
+    SCORE603E_85C30_2_IRQ,
+    SCORE603E_85C30_2_CLOCK,
+    SCORE603E_85C30_2_CLOCK_X,
+    CONSOLE_DEFAULT_CONSOLE_CLOCK
+  },
+  { 
+    SCORE603E_85C30_3_IRQ,
+    SCORE603E_85C30_3_CLOCK,
+    SCORE603E_85C30_3_CLOCK_X,
+    CONSOLE_DEFAULT_CONSOLE_CLOCK
+  },
+  { 
+    SCORE603E_85C30_4_IRQ,
+    SCORE603E_85C30_4_CLOCK,
+    SCORE603E_85C30_4_CLOCK_X,
+    CONSOLE_DEFAULT_CONSOLE_CLOCK
+  },
+  { 
+    SCORE603E_85C30_5_IRQ,
+    SCORE603E_85C30_5_CLOCK,
+    SCORE603E_85C30_5_CLOCK_X,
+    CONSOLE_DEFAULT_CONSOLE_CLOCK
+  },
+#endif
+
+};
+
+/*
+ * Table of port unique information for each port.
+ * See consolebsp.h for the Port_85C30_info structure defination.
+ */
+const Port_85C30_info Ports_85C30 [ NUM_Z85C30_PORTS ] = {
+  { 
+    (volatile unsigned char *) SCORE603E_85C30_CTRL_0,  
+    (volatile unsigned char *) SCORE603E_85C30_DATA_0,
+    0x00,
+    &Protocols_85c30[0],
+    &Chips_85C30[0], 
+  },
+  {  
+    (volatile unsigned char *) SCORE603E_85C30_CTRL_1,  
+    (volatile unsigned char *) SCORE603E_85C30_DATA_1, 
+    0x01,
+    &Protocols_85c30[1],
+    &Chips_85C30[0], 
+  },
+  {  
+    (volatile unsigned char *) SCORE603E_85C30_CTRL_2,  
+    (volatile unsigned char *) SCORE603E_85C30_DATA_2,
+    0x02,
+    &Protocols_85c30[2],
+    &Chips_85C30[1], 
+  },
+  {  
+    (volatile unsigned char *) SCORE603E_85C30_CTRL_3, 
+    (volatile unsigned char *) SCORE603E_85C30_DATA_3,
+    0x03,
+    &Protocols_85c30[3],
+    &Chips_85C30[1], 
+ },
+
+#if defined(HAS_PMC_PSC8)
+  {  
+    (volatile unsigned char *) SCORE603E_85C30_CTRL_4, 
+    (volatile unsigned char *) SCORE603E_85C30_DATA_4,
+    0x04,
+    &Protocols_85c30[4],
+    &Chips_85C30[2], 
+ },
+ {  
+    (volatile unsigned char *) SCORE603E_85C30_CTRL_5, 
+    (volatile unsigned char *) SCORE603E_85C30_DATA_5,
+    0x05,
+    &Protocols_85c30[5],
+    &Chips_85C30[2], 
+ },
+ {  
+    (volatile unsigned char *) SCORE603E_85C30_CTRL_6, 
+    (volatile unsigned char *) SCORE603E_85C30_DATA_6,
+    0x06,
+    &Protocols_85c30[6],
+    &Chips_85C30[3], 
+ },
+ {  
+    (volatile unsigned char *) SCORE603E_85C30_CTRL_7, 
+    (volatile unsigned char *) SCORE603E_85C30_DATA_7,
+    0x07,
+    &Protocols_85c30[7],
+    &Chips_85C30[3], 
+ },
+ {  
+    (volatile unsigned char *) SCORE603E_85C30_CTRL_8, 
+    (volatile unsigned char *) SCORE603E_85C30_DATA_8,
+    0x08,
+    &Protocols_85c30[8],
+    &Chips_85C30[4], 
+ },
+ {  
+    (volatile unsigned char *) SCORE603E_85C30_CTRL_9, 
+    (volatile unsigned char *) SCORE603E_85C30_DATA_9,
+    0x09,
+    &Protocols_85c30[9],
+    &Chips_85C30[4], 
+ },
+ {  
+    (volatile unsigned char *) SCORE603E_85C30_CTRL_10, 
+    (volatile unsigned char *) SCORE603E_85C30_DATA_10,
+    0x0a,
+    &Protocols_85c30[10],
+    &Chips_85C30[5], 
+ },
+ {  
+    (volatile unsigned char *) SCORE603E_85C30_CTRL_11, 
+    (volatile unsigned char *) SCORE603E_85C30_DATA_11,
+    0x0b,
+    &Protocols_85c30[11],
+    &Chips_85C30[5], 
+ },
+#endif
+};
+