2004-11-22 Jennifer Averett <jennifer@OARcorp.com>

	PR 581/bsps
	* Makefile.am, bsp_specs, configure.ac, include/bsp.h, include/tm27.h,
	start/start.S, startup/bspstart.c, startup/linkcmds,
	tools/Makefile.am, tools/psim, vectors/vectors.S, wrapup/Makefile.am:
	Convert PSIM to new exception model.
	* irq/irq.c, irq/irq.h, irq/irq_asm.S, irq/irq_init.c: New files.
	* startup/setvec.c, timer/timer.c: Removed.

1 files changed, 153 insertions, 115 deletions

diff --git a/c/src/lib/libbsp/powerpc/psim/vectors/vectors.S b/c/src/lib/libbsp/powerpc/psim/vectors/vectors.S
index 0d58bd38e4..65f65d30bb 100644
--- a/c/src/lib/libbsp/powerpc/psim/vectors/vectors.S
+++ b/c/src/lib/libbsp/powerpc/psim/vectors/vectors.S
@@ -1,122 +1,160 @@
-/*  vectors.s	1.1 - 95/12/04
- *
- *  This file contains the assembly code for the PowerPC
- *  interrupt vectors for RTEMS.
- *
- *  COPYRIGHT (c) 1989-1999.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in found in the file LICENSE in this distribution or at
- *  http://www.rtems.com/license/LICENSE.
- *
- *  $Id$
- */
-
 /*
- *  The issue with this file is getting it loaded at the right place.
- *  The first vector MUST be at address 0x????0100.
- *  How this is achieved is dependant on the tool chain.
+ * (c) 1999, Eric Valette valette@crf.canon.fr
  *
- *  However the basic mechanism for ELF assemblers is to create a
- *  section called ".vectors", which will be loaded to an address
- *  between 0x????0000 and 0x????0100 (inclusive) via a link script.
  *
- *  The basic mechanism for XCOFF assemblers is to place it in the
- *  normal text section, and arrange for this file to be located
- *  at an appropriate position on the linker command line.
+ *  This file contains the assembly code for the PowerPC 
+ *  exception veneers for RTEMS.
  *
- *  The variable 'PPC_VECTOR_FILE_BASE' must be defined to be the
- *  offset from 0x????0000 to the first location in the file.  This
- *  will usually be 0x0000 or 0x0100.
+ * vectors.S,v 1.3.4.1 2003/02/20 21:48:25 joel Exp
  */
+	
 
-#include <bsp.h>
-#include <rtems/asm.h>
-
-#ifndef PPC_VECTOR_FILE_BASE
-#error "PPC_VECTOR_FILE_BASE is not defined."
-#endif
-
-	/* Where this file will be loaded */
-	.set	file_base, PPC_VECTOR_FILE_BASE
-
-	/* Offset to store reg 0 */
-
-	.set	IP_LINK, 0
-#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
-	.set	IP_0, (IP_LINK + 56)
-#else
-	.set	IP_0, (IP_LINK + 8)
-#endif
-	.set	IP_2, (IP_0 + 4)
-
-	.set	IP_3, (IP_2 + 4)
-	.set	IP_4, (IP_3 + 4)
-	.set	IP_5, (IP_4 + 4)
-	.set	IP_6, (IP_5 + 4)
-
-	.set	IP_7, (IP_6 + 4)
-	.set	IP_8, (IP_7 + 4)
-	.set	IP_9, (IP_8 + 4)
-	.set	IP_10, (IP_9 + 4)
 
-	.set	IP_11, (IP_10 + 4)
-	.set	IP_12, (IP_11 + 4)
-	.set	IP_13, (IP_12 + 4)
-	.set	IP_28, (IP_13 + 4)
-
-	.set	IP_29, (IP_28 + 4)
-	.set	IP_30, (IP_29 + 4)
-	.set	IP_31, (IP_30 + 4)
-	.set	IP_CR, (IP_31 + 4)
-
-	.set	IP_CTR, (IP_CR + 4)
-	.set	IP_XER, (IP_CTR + 4)
-	.set	IP_LR, (IP_XER + 4)
-	.set	IP_PC, (IP_LR + 4)
-
-	.set	IP_MSR, (IP_PC + 4)
-
-	.set	IP_END, (IP_MSR + 16)
-
-	/* Vector offsets			 */
-	.set    begin_vector,0xFFF00000
-	.set    crit_vector,0xFFF00100
-	.set    mach_vector,0xFFF00200
-	.set    prot_vector,0xFFF00300
-	.set    ext_vector,0xFFF00500
-	.set    align_vector,0xFFF00600
-	.set    prog_vector,0xFFF00700
-	.set    dec_vector,0xFFF00900
-	.set    sys_vector,0xFFF00C00
-	.set    pit_vector,0xFFF01000
-	.set    fit_vector,0xFFF01010
-	.set    wadt_vector,0xFFF01020
-	.set    debug_vector,0xFFF02000
-
-/* Go to the right section */
-#if PPC_ASM == PPC_ASM_ELF
-	.section .vectors,"awx",@progbits
-#elif PPC_ASM == PPC_ASM_XCOFF
-	.csect	.text[PR]
-#endif
-
-	PUBLIC_VAR (__vectors)
-SYM (__vectors):
-
-/* Decrementer interrupt */
-	.org	dec_vector - file_base
-#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
-#if (PPC_HAS_FPU)
-	stwu	r1, -(20*4 + 18*8 + IP_END)(r1)
-#else
-	stwu	r1, -(20*4 + IP_END)(r1)
-#endif
-#else
-	stwu	r1, -(IP_END)(r1)
-#endif
-	stw	r0, IP_0(r1)
-
-	li      r0, PPC_IRQ_DECREMENTER
-	b       PROC (_ISR_Handler)
+#include <rtems/asm.h>
+#include <rtems/score/cpu.h>
+#include <bsp/vectors.h>
+	
+
+#define SYNC \
+	sync; \
+	isync
+	
+	PUBLIC_VAR (__rtems_start)
+	.section .entry_point_section,"awx",@progbits
+/*
+ * Entry point information used by bootloader code
+ */
+SYM (__rtems_start):		
+	.long   __rtems_entry_point
+
+	/*
+	 * end of special Entry point section
+	 */	
+	.text
+	.p2align 5	
+		
+PUBLIC_VAR(default_exception_vector_code_prolog)
+SYM (default_exception_vector_code_prolog):
+	/*
+	 * let room for exception frame
+	 */
+	stwu    r1, - (EXCEPTION_FRAME_END)(r1)
+	stw	r3, GPR3_OFFSET(r1)
+	/* R2 should never change (EABI: pointer to .sdata2) - we
+     * save it nevertheless..
+	 */
+	stw	r2, GPR2_OFFSET(r1)
+	mflr	r3
+	stw	r3, EXC_LR_OFFSET(r1)
+	bl	0f
+0:	/*
+	 * r3 = exception vector entry point 
+	 * (256 * vector number) + few instructions
+	 */
+	mflr	r3
+	/*
+	 * r3 = r3 >> 8 = vector
+	 */
+	srwi	r3,r3,8
+	ba	push_normalized_frame
+	
+	PUBLIC_VAR (default_exception_vector_code_prolog_size)
+	
+	default_exception_vector_code_prolog_size= . - default_exception_vector_code_prolog
+	
+	.p2align 5
+PUBLIC_VAR (push_normalized_frame)	
+SYM (push_normalized_frame):
+	stw	r3, EXCEPTION_NUMBER_OFFSET(r1)
+	stw	r0, GPR0_OFFSET(r1)
+	mfsrr0  r3
+	stw	r3, SRR0_FRAME_OFFSET(r1)
+	mfsrr1  r3
+	stw	r3, SRR1_FRAME_OFFSET(r1)
+	/*
+	 * Save general purpose registers
+	 * Already saved in prolog : R1, R2, R3, LR.
+	 * Saved a few line above  : R0
+	 *
+	 * Manual says that "stmw" instruction may be slower than
+	 * series of individual "stw" but who cares about performance 
+	 * for the DEFAULT exception handler?
+	 */
+	stmw	r4, GPR4_OFFSET(r1)	/* save R4->R31 */
+
+	mfcr	r31
+	stw	r31,  EXC_CR_OFFSET(r1)
+	mfctr	r30
+	stw	r30,  EXC_CTR_OFFSET(r1)
+	mfxer	r28
+	stw	r28,  EXC_XER_OFFSET(r1)
+	mfmsr	r28
+	stw	r28,  EXC_MSR_OFFSET(r1)
+	mfdar	r28
+	stw	r28,  EXC_DAR_OFFSET(r1)
+	/*
+	 * compute SP at exception entry
+	 */
+	addi    r3, r1, EXCEPTION_FRAME_END
+	/*
+	 * store it at the right place
+	 */
+	stw     r3, GPR1_OFFSET(r1)
+	/*
+	 * Enable data and instruction address translation, exception nesting
+	 */
+	mfmsr	r3
+	ori     r3,r3, MSR_RI /* | MSR_IR | MSR_DR */
+	mtmsr   r3
+	SYNC
+	
+	/*
+	 * Call C exception handler
+	 */
+	/*
+	 * store the execption frame address in r3 (first param)
+	 */
+	addi	r3, r1, 0x8
+	/*
+	 * globalExceptHdl(r3)
+	 */
+	addis	r4, 0, globalExceptHdl@ha
+	lwz	r5, globalExceptHdl@l(r4)
+	mtlr	r5
+	blrl
+	/*
+	 * Restore registers status
+	 */
+	lwz	r31,  EXC_CR_OFFSET(r1)
+	mtcr	r31
+	lwz	r30,  EXC_CTR_OFFSET(r1)
+	mtctr	r30
+	lwz	r29,  EXC_LR_OFFSET(r1)
+	mtlr	r29
+	lwz	r28,  EXC_XER_OFFSET(r1)
+	mtxer	r28
+
+	lmw	r4, GPR4_OFFSET(r1)
+	lwz	r2, GPR2_OFFSET(r1)
+	lwz	r0, GPR0_OFFSET(r1)
+
+	/*
+	 * Disable data and instruction translation. Make path non recoverable...
+	 */
+	mfmsr	r3
+	xori	r3, r3, MSR_RI | MSR_IR | MSR_DR
+	mtmsr   r3
+	SYNC
+	/*
+	 * Restore rfi related settings
+	 */
+		 
+	lwz	r3, SRR1_FRAME_OFFSET(r1)
+	mtsrr1	r3
+	lwz	r3, SRR0_FRAME_OFFSET(r1)
+	mtsrr0	r3
+	
+	lwz	r3, GPR3_OFFSET(r1)
+	addi 	r1,r1, EXCEPTION_FRAME_END
+	SYNC
+	rfi