./clock/Makefile.in,v

./clock/clock.c,v
./console/Makefile.in,v
./console/config.c,v
./console/console.c,v
./console/console.h,v
./console/debugio.c,v
./console/i8042.c,v
./console/i8042_p.h,v
./console/i8042vga.c,v
./console/i8042vga.h,v
./console/ns16550.c,v
./console/ns16550.h,v
./console/ns16550_p.h,v
./console/ns16550cfg.c,v
./console/ns16550cfg.h,v
./console/vga.c,v
./console/vga_p.h,v
./console/z85c30.c,v
./console/z85c30.h,v
./console/z85c30_p.h,v
./console/z85c30cfg.c,v
./console/z85c30cfg.h,v
./include/Makefile.in,v
./include/bsp.h,v
./include/chain.h,v
./include/coverhd.h,v
./include/extisrdrv.h,v
./include/nvram.h,v
./include/pci.h,v
./include/tod.h,v
./network/Makefile.in,v
./network/amd79c970.c,v
./network/amd79c970.h,v
./nvram/Makefile.in,v
./nvram/ds1385.h,v
./nvram/mk48t18.h,v
./nvram/nvram.c,v
./nvram/prepnvr.h,v
./nvram/stk11c68.h,v
./pci/Makefile.in,v
./pci/pci.c,v
./start/Makefile.in,v
./start/start.s,v
./startup/Makefile.in,v
./startup/bspclean.c,v
./startup/bspstart.c,v
./startup/bsptrap.s,v
./startup/device-tree,v
./startup/genpvec.c,v
./startup/linkcmds,v
./startup/rtems-ctor.cc,v
./startup/sbrk.c,v
./startup/setvec.c,v
./startup/spurious.c,v
./startup/swap.c,v
./timer/Makefile.in,v
./timer/timer.c,v
./tod/Makefile.in,v
./tod/cmos.h,v
./tod/tod.c,v
./universe/Makefile.in,v
./universe/universe.c,v
./vectors/Makefile.in,v
./vectors/README,v
./vectors/align_h.s,v
./vectors/vectors.s,v
./wrapup/Makefile.in,v
./Makefile.in,v
./README,v
./STATUS,v
./bsp_specs,v

6 files changed, 870 insertions, 0 deletions

diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/Makefile.in b/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/Makefile.in
new file mode 100644
index 0000000000..5cf4e06e0e
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/Makefile.in
@@ -0,0 +1,56 @@
+#
+#  $Id$
+#
+
+@SET_MAKE@
+srcdir = @srcdir@
+VPATH = @srcdir@
+RTEMS_ROOT = @top_srcdir@
+PROJECT_ROOT = @PROJECT_ROOT@
+
+PGM=${ARCH}/nvram.rel
+
+# C source names, if any, go here -- minus the .c
+C_PIECES=$(NVRAM_PIECES)
+C_FILES=$(C_PIECES:%=%.c)
+C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
+
+H_FILES=
+
+SRCS=$(C_FILES) $(H_FILES)
+OBJS=$(C_O_FILES)
+
+include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
+include $(RTEMS_ROOT)/make/leaf.cfg
+
+NVRAM_PIECES=nvram
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+DEFINES  +=
+CPPFLAGS +=
+CFLAGS   +=
+
+LD_PATHS  +=
+LD_LIBS   +=
+LDFLAGS   +=
+
+#
+# Add your list of files to delete here.  The config files
+#  already know how to delete some stuff, so you may want
+#  to just run 'make clean' first to see what gets missed.
+#  'make clobber' already includes 'make clean'
+#
+
+CLEAN_ADDITIONS +=
+CLOBBER_ADDITIONS +=
+
+${PGM}: ${SRCS} ${OBJS}
+	$(make-rel)
+
+all:	${ARCH} $(SRCS) $(PGM)
+
+# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile
+install:  all
diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/ds1385.h b/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/ds1385.h
new file mode 100644
index 0000000000..c4861d9c80
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/ds1385.h
@@ -0,0 +1,39 @@
+/*
+ *  COPYRIGHT (c) 1998 by Radstone Technology
+ *
+ *
+ * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
+ * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
+ * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
+ *
+ * You are hereby granted permission to use, copy, modify, and distribute
+ * this file, provided that this notice, plus the above copyright notice
+ * and disclaimer, appears in all copies. Radstone Technology will provide
+ * no support for this code.
+ *
+ */
+
+/*
+ * Definitions for the ds1385 NvRAM
+ */
+
+#ifndef _DS1385_H
+#define _DS1385_H
+
+#include "prepnvr.h"
+
+#define DS1385_NVSIZE 4096       /* size of NVRAM */
+#define DS1385_GESIZE (DS1385_NVSIZE-CONFSIZE-OSAREASIZE-sizeof(HEADER))
+#define DS1385_PORT_BASE 0x74
+
+/* Here is the whole map of the DS1385 NVRAM */
+typedef struct _DS1385_NVRAM_MAP {
+  HEADER Header;
+  unsigned char GEArea[DS1385_GESIZE];
+  unsigned char OSArea[OSAREASIZE];
+  unsigned char ConfigArea[CONFSIZE];
+  } DS1385_NVRAM_MAP, *PDS1385_NVRAM_MAP;
+
+#endif /* _DS1385_H */
+
diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/mk48t18.h b/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/mk48t18.h
new file mode 100644
index 0000000000..f4aa3be106
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/mk48t18.h
@@ -0,0 +1,87 @@
+/*
+ *  COPYRIGHT (c) 1998 by Radstone Technology
+ *
+ *
+ * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
+ * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
+ * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
+ *
+ * You are hereby granted permission to use, copy, modify, and distribute
+ * this file, provided that this notice, plus the above copyright notice
+ * and disclaimer, appears in all copies. Radstone Technology will provide
+ * no support for this code.
+ *
+ */
+
+/*
+ * Definitions for the mk48t18 RTC/NvRAM
+ */
+
+#ifndef _MK48T18_H
+#define _MK48T18_H
+
+#include "prepnvr.h"
+
+/*
+ * This structure maps to the top of the NvRAM. It is based on the standard
+ * CMOS.h file for the ds1385. Feature and system dependant areas are preserved
+ * for potential compatibility issues.
+ *
+ * The CRC's are computed with x**16+x**12+x**5 + 1 polynomial
+ * The clock is kept in 24 hour BCD mode and should be set to UT(GMT)
+ */
+ 
+typedef struct _MK48T18_CMOS_MAP {
+    unsigned8 SystemDependentArea2[8];
+    unsigned8 FeatureByte0[1];
+    unsigned8 FeatureByte1[1];
+    unsigned8 Century;	     /* century byte in BCD */
+    unsigned8 FeatureByte3[1];
+    unsigned8 FeatureByte4[1];
+    unsigned8 FeatureByte5[1];
+    unsigned8 FeatureByte6[1];
+    unsigned8 FeatureByte7[1];
+    unsigned8 BootPW[14];
+    rtems_unsigned16 BootCrc; /* CRC on BootPW */
+    unsigned8 ConfigPW[14];
+    rtems_unsigned16 ConfigCrc; /* CRC on ConfigPW */
+    unsigned8 SystemDependentArea1[8];
+    /*
+     * The following are the RTC registers
+     */
+    volatile unsigned8 Control;
+    volatile unsigned8 Second:7;	/* 0-59 */
+    volatile unsigned8 Stop:1;
+    volatile unsigned8 Minute;	/* 0-59 */
+    volatile unsigned8 Hour;	/* 0-23 */
+    volatile unsigned8 Day:3;	/* 1-7 */
+    volatile unsigned8 Resvd1:3;	/* 0 */
+    volatile unsigned8 FT:1;	/* Frequency test bit - must be 0 */
+    volatile unsigned8 Resvd2:1;	/* 0 */
+    volatile unsigned8 Date;	/* 1-31 */
+    volatile unsigned8 Month;	/* 1-12 */
+    volatile unsigned8 Year;	/* 0-99 */
+} MK48T18_CMOS_MAP, *PMK48T18_CMOS_MAP;
+
+/*
+ * Control register definitions
+ */
+#define MK48T18_CTRL_WRITE	0x80
+#define MK48T18_CTRL_READ	0x40
+#define MK48T18_CTRL_SIGN	0x20
+
+#define MK48T18_NVSIZE 8192-sizeof(MK48T18_CMOS_MAP)
+#define MK48T18_GESIZE (MK48T18_NVSIZE-CONFSIZE-OSAREASIZE-sizeof(HEADER))
+#define MK48T18_BASE (PMK48T18_NVRAM_MAP)((unsigned8 *)PCI_MEM_BASE+0x00800000)
+
+/* Here is the whole map of the MK48T18 NVRAM */
+typedef struct _MK48T18_NVRAM_MAP {
+    HEADER	Header;
+    unsigned8	GEArea[MK48T18_GESIZE];
+    unsigned8	OSArea[OSAREASIZE];
+    unsigned8	ConfigArea[CONFSIZE];
+    MK48T18_CMOS_MAP	CMOS;
+} MK48T18_NVRAM_MAP, *PMK48T18_NVRAM_MAP;
+
+#endif /* _MK48T18_H */
diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/nvram.c b/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/nvram.c
new file mode 100644
index 0000000000..bf085c968b
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/nvram.c
@@ -0,0 +1,515 @@
+/*
+ *  This file contains the NvRAM driver for the PPCn_60x
+ *
+ *  COPYRIGHT (c) 1998 by Radstone Technology
+ *
+ *
+ * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
+ * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
+ * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
+ *
+ * You are hereby granted permission to use, copy, modify, and distribute
+ * this file, provided that this notice, plus the above copyright notice
+ * and disclaimer, appears in all copies. Radstone Technology will provide
+ * no support for this code.
+ *
+ */
+
+#include <bsp.h>
+#include "ds1385.h"
+#include "mk48t18.h"
+#include "stk11c68.h"
+
+/*
+ * Private types
+ */
+typedef
+void
+(*PNVRAMWRITE)
+(
+	unsigned32 ulOffset,
+	unsigned8 ucByte
+);
+
+typedef
+unsigned8
+(*PNVRAMREAD)
+(
+	unsigned32 ulOffset
+);
+
+typedef
+void
+(*PNVRAMCOMMIT)
+(
+);
+
+typedef struct _NVRAM_ENTRY_TABLE
+{
+	PNVRAMWRITE	nvramWrite;
+	PNVRAMREAD	nvramRead;
+	PNVRAMCOMMIT	nvramCommit;
+	unsigned32	nvramSize;
+} NVRAM_ENTRY_TABLE, *PNVRAM_ENTRY_TABLE;
+
+/*
+ * Private routines
+ */
+
+/*
+ * This routine provides a stub for NvRAM devices which
+ * do not require a commit operation
+ */
+static void nvramCommitStub();
+
+/*
+ * DS1385 specific routines
+ */
+static void nvramDsWrite(unsigned32 ulOffset, unsigned8 ucByte);
+static unsigned8 nvramDsRead(unsigned32 ulOffset);
+
+/*
+ * MK48T18 specific routines
+ */
+static void nvramMkWrite(unsigned32 ulOffset, unsigned8 ucByte);
+static unsigned8 nvramMkRead(unsigned32 ulOffset);
+
+/*
+ * STK11C68 specific routines
+ */
+static void nvramStk11C68Commit();
+/*
+ * STK11C88 specific routines
+ */
+static void nvramStk11C88Commit();
+
+/*
+ * NvRAM hook tables
+ */
+NVRAM_ENTRY_TABLE nvramDsTable =
+{
+	nvramDsWrite,
+	nvramDsRead,
+	nvramCommitStub,
+	DS1385_NVSIZE
+};
+
+NVRAM_ENTRY_TABLE nvramMkTable =
+{
+	nvramMkWrite,
+	nvramMkRead,
+	nvramCommitStub,
+	MK48T18_NVSIZE
+};
+
+/*
+ * As the STK devicxe is at the same address as the MK device,
+ * the MK read/write routines may be used
+ */
+NVRAM_ENTRY_TABLE nvramStkTable =
+{
+	nvramMkWrite,
+	nvramMkRead,
+	nvramStk11C68Commit,
+	STK11C68_NVSIZE
+};
+
+NVRAM_ENTRY_TABLE nvramStk88Table =
+{
+	nvramMkWrite,
+	nvramMkRead,
+	nvramStk11C88Commit,
+	STK11C88_NVSIZE
+};
+
+/*
+ * Private variables
+ */
+static PNVRAM_ENTRY_TABLE pNvRAMFunc;
+static boolean		bNvRAMChanged=FALSE;
+static unsigned32	ulPRePOSAreaLength;
+static unsigned32	ulPRePOSAreaOffset;
+
+/*
+ * Mutual-exclusion semaphore
+ */
+static rtems_id semNvRAM;
+
+/*
+ * These routines support the ds1385
+ */
+static unsigned8 nvramDsRead(unsigned32 ulOffset)
+{
+	unsigned8 ucTemp;
+
+	ucTemp = ulOffset & 0xff;
+	outport_byte(DS1385_PORT_BASE, ucTemp);
+
+	ucTemp = (ulOffset >> 8) & 0xf;
+	outport_byte((DS1385_PORT_BASE + 1) , ucTemp);
+
+	inport_byte(DS1385_PORT_BASE+3, ucTemp);
+	return(ucTemp);
+}
+
+static void nvramDsWrite(unsigned32 ulOffset, unsigned8 ucData)
+{
+	unsigned8 ucTemp;
+
+	ucTemp = (unsigned8)(ulOffset & 0xff);
+	outport_byte(DS1385_PORT_BASE, (unsigned8) ucTemp);
+
+	ucTemp = (unsigned8)((ulOffset >> 8) & 0xf);
+	outport_byte((DS1385_PORT_BASE + 1) , (unsigned8)ucTemp);
+
+	outport_byte((DS1385_PORT_BASE+3), ucData);
+}
+
+/*
+ * These routines support the MK48T18 and STK11C68
+ */
+static unsigned8 nvramMkRead(unsigned32 ulOffset)
+{
+	unsigned8 *pNvRAM = (unsigned8 *)MK48T18_BASE;
+
+	return(pNvRAM[ulOffset]);
+}
+
+static void nvramMkWrite(unsigned32 ulOffset, unsigned8 ucData)
+{
+	unsigned8 *pNvRAM = (unsigned8 *)MK48T18_BASE;
+
+	pNvRAM[ulOffset]=ucData;
+}
+
+/*
+ * This routine provides a stub for NvRAM devices which
+ * do not require a commit operation
+ */
+static void nvramCommitStub()
+{
+}
+
+/*
+ * This routine triggers a transfer from the NvRAM to the
+ * EE array in the STK11C68 device
+ */
+static void nvramStk11C68Commit()
+{
+#if 0
+	rtems_interval		ticks_per_second;
+	rtems_status_code	status;
+#endif
+
+	rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
+	/*
+	 * Issue Store command
+	 */
+	EIEIO;
+	(void)pNvRAMFunc->nvramRead(0x0000);
+	EIEIO;
+	(void)pNvRAMFunc->nvramRead(0x1555);
+	EIEIO;
+	(void)pNvRAMFunc->nvramRead(0x0aaa);
+	EIEIO;
+	(void)pNvRAMFunc->nvramRead(0x1fff);
+	EIEIO;
+	(void)pNvRAMFunc->nvramRead(0x10f0);
+	EIEIO;
+	(void)pNvRAMFunc->nvramRead(0x0f0f);
+	EIEIO;
+	/*
+	 * Delay for 10mS to allow store to
+	 * complete
+	 */
+#if 0
+	status = rtems_clock_get(
+		RTEMS_CLOCK_GET_TICKS_PER_SECOND,
+		&ticks_per_second
+	);
+
+	status = rtems_task_wake_after(ticks_per_second/100);
+#endif
+	bNvRAMChanged=FALSE;
+
+	rtems_semaphore_release(semNvRAM);
+}
+
+/*
+ * This routine triggers a transfer from the NvRAM to the
+ * EE array in the STK11C88 device
+ */
+static void nvramStk11C88Commit()
+{
+#if 0
+	rtems_interval		ticks_per_second;
+	rtems_status_code	status;
+#endif
+
+	rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
+	/*
+	 * Issue Store command
+	 */
+	EIEIO;
+	(void)pNvRAMFunc->nvramRead(0x0e38);
+	EIEIO;
+	(void)pNvRAMFunc->nvramRead(0x31c7);
+	EIEIO;
+	(void)pNvRAMFunc->nvramRead(0x03e0);
+	EIEIO;
+	(void)pNvRAMFunc->nvramRead(0x3c1f);
+	EIEIO;
+	(void)pNvRAMFunc->nvramRead(0x303f);
+	EIEIO;
+	(void)pNvRAMFunc->nvramRead(0x0fc0);
+	EIEIO;
+	/*
+	 * Delay for 10mS to allow store to
+	 * complete
+	 */
+#if 0
+	status = rtems_clock_get(
+		RTEMS_CLOCK_GET_TICKS_PER_SECOND,
+		&ticks_per_second
+	);
+
+	status = rtems_task_wake_after(ticks_per_second/100);
+#endif
+	bNvRAMChanged=FALSE;
+
+	rtems_semaphore_release(semNvRAM);
+}
+
+/*
+ * These are the publically accessable routines
+ */
+/*
+ * This routine returns the size of the NvRAM
+ */
+unsigned32 SizeNvRAM()
+{
+	return(ulPRePOSAreaLength);
+}
+
+/*
+ * This routine commits changes to the NvRAM
+ */
+void CommitNvRAM()
+{
+	if(bNvRAMChanged)
+	{
+		(pNvRAMFunc->nvramCommit)();
+	}
+}
+
+/*
+ * This routine reads a byte from the NvRAM
+ */
+rtems_status_code ReadNvRAM8(unsigned32 ulOffset, unsigned8 *pucData)
+{
+	if(ulOffset>ulPRePOSAreaLength)
+	{
+		return RTEMS_INVALID_ADDRESS;
+	}
+	rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
+	*pucData=pNvRAMFunc->nvramRead(ulPRePOSAreaOffset+ulOffset);
+	rtems_semaphore_release(semNvRAM);
+	return(RTEMS_SUCCESSFUL);
+}
+
+/*
+ * This routine writes a byte to the NvRAM
+ */
+rtems_status_code WriteNvRAM8(unsigned32 ulOffset, unsigned8 ucValue)
+{
+	if(ulOffset>ulPRePOSAreaLength)
+	{
+		return RTEMS_INVALID_ADDRESS;
+	}
+	rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
+	pNvRAMFunc->nvramWrite(ulPRePOSAreaOffset+ulOffset, ucValue);
+	bNvRAMChanged=TRUE;
+	rtems_semaphore_release(semNvRAM);
+	return(RTEMS_SUCCESSFUL);
+}
+
+/*
+ * This routine reads a block of bytes from the NvRAM
+ */
+rtems_status_code ReadNvRAMBlock(
+  unsigned32 ulOffset, unsigned8 *pucData, unsigned32 length)
+{
+	unsigned32 i;
+
+	if((ulOffset + length) > ulPRePOSAreaLength)
+	{
+		return RTEMS_INVALID_ADDRESS;
+	}
+	rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
+	for ( i=0 ; i<length ; i++ )
+		pucData[i] =
+			pNvRAMFunc->nvramRead(ulPRePOSAreaOffset+ulOffset+i);
+	rtems_semaphore_release(semNvRAM);
+	return(RTEMS_SUCCESSFUL);
+}
+
+/*
+ * This routine writes a block of bytes to the NvRAM
+ */
+rtems_status_code WriteNvRAMBlock(
+  unsigned32 ulOffset, unsigned8 *ucValue, unsigned32 length)
+{
+	unsigned32 i;
+
+	if((ulOffset + length) > ulPRePOSAreaLength)
+	{
+		return RTEMS_INVALID_ADDRESS;
+	}
+	rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
+
+	for ( i=0 ; i<length ; i++ )
+		pNvRAMFunc->nvramWrite(
+			ulPRePOSAreaOffset+ulOffset+i, ucValue[i]);
+	bNvRAMChanged=TRUE;
+	rtems_semaphore_release(semNvRAM);
+	return(RTEMS_SUCCESSFUL);
+}
+
+/*
+ * The NVRAM holds data in Big-Endian format
+ */
+rtems_status_code ReadNvRAM16 (unsigned32 ulOffset, unsigned16 *pusData)
+{
+	unsigned32 ulTrueOffset=ulPRePOSAreaOffset+ulOffset;
+
+	if(ulOffset>ulPRePOSAreaLength)
+	{
+		return RTEMS_INVALID_ADDRESS;
+	}
+	rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
+        *pusData=(pNvRAMFunc->nvramRead(ulTrueOffset) << 8) +
+		 (pNvRAMFunc->nvramRead(ulTrueOffset + 1));
+	rtems_semaphore_release(semNvRAM);
+	return(RTEMS_SUCCESSFUL);
+}
+
+rtems_status_code WriteNvRAM16 (unsigned32 ulOffset, unsigned16 usValue)
+{
+	unsigned32 ulTrueOffset=ulPRePOSAreaOffset+ulOffset;
+
+	if(ulOffset>ulPRePOSAreaLength)
+	{
+		return RTEMS_INVALID_ADDRESS;
+	}
+	rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
+        pNvRAMFunc->nvramWrite(ulTrueOffset, (unsigned8) (usValue >> 8));
+        pNvRAMFunc->nvramWrite(ulTrueOffset + 1, (unsigned8) usValue);
+	bNvRAMChanged=TRUE;
+	rtems_semaphore_release(semNvRAM);
+	return(RTEMS_SUCCESSFUL);
+}
+
+rtems_status_code ReadNvRAM32 (unsigned32 ulOffset, unsigned32 *pulData)
+{
+	unsigned32 ulTrueOffset=ulPRePOSAreaOffset+ulOffset;
+
+	if(ulOffset>ulPRePOSAreaLength)
+	{
+		return RTEMS_INVALID_ADDRESS;
+	}
+	rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
+        *pulData=(pNvRAMFunc->nvramRead(ulTrueOffset) << 24) +
+		 (pNvRAMFunc->nvramRead(ulTrueOffset + 1) << 16) +
+		 (pNvRAMFunc->nvramRead(ulTrueOffset + 2) << 8) +
+		 (pNvRAMFunc->nvramRead(ulTrueOffset + 3));
+	rtems_semaphore_release(semNvRAM);
+	return(RTEMS_SUCCESSFUL);
+}
+
+rtems_status_code WriteNvRAM32 (unsigned32 ulOffset, unsigned32 ulValue)
+{
+	unsigned32 ulTrueOffset=ulPRePOSAreaOffset+ulOffset;
+
+	if(ulOffset>ulPRePOSAreaLength)
+	{
+		return RTEMS_INVALID_ADDRESS;
+	}
+	rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
+        pNvRAMFunc->nvramWrite(ulTrueOffset, (unsigned8) (ulValue >> 24));
+        pNvRAMFunc->nvramWrite(ulTrueOffset + 1, (unsigned8) (ulValue >> 16));
+        pNvRAMFunc->nvramWrite(ulTrueOffset + 2, (unsigned8) (ulValue >> 8));
+        pNvRAMFunc->nvramWrite(ulTrueOffset + 3, (unsigned8) ulValue);
+	bNvRAMChanged=TRUE;
+	rtems_semaphore_release(semNvRAM);
+	return(RTEMS_SUCCESSFUL);
+}
+
+void
+InitializeNvRAM(void)
+{
+	PHEADER pNvHeader = (PHEADER)0;
+	rtems_status_code sc;
+	unsigned32 ulLength, ulOffset;
+
+	if(ucSystemType==SYS_TYPE_PPC1)
+	{
+		if(ucBoardRevMaj<5)
+		{
+			pNvRAMFunc=&nvramDsTable;
+		}
+		else
+		{
+			pNvRAMFunc=&nvramMkTable;
+		}
+	}
+	else if(ucSystemType==SYS_TYPE_PPC1a)
+	{
+		pNvRAMFunc=&nvramMkTable;
+	}
+	else if(ucSystemType==SYS_TYPE_PPC4)
+	{
+		pNvRAMFunc=&nvramStk88Table;
+	}
+	else
+	{
+		pNvRAMFunc=&nvramStkTable;
+	}
+
+        /*
+         * Set up mutex semaphore
+         */
+        sc = rtems_semaphore_create (
+                rtems_build_name ('N', 'V', 'R', 's'),
+                1,
+                RTEMS_BINARY_SEMAPHORE |
+                RTEMS_INHERIT_PRIORITY |
+                RTEMS_PRIORITY,
+                RTEMS_NO_PRIORITY,
+                &semNvRAM);
+        if (sc != RTEMS_SUCCESSFUL)
+        {
+                rtems_fatal_error_occurred (sc);
+        }
+
+	/*
+	 * Initially access the whole of NvRAM until we determine where the
+	 * OS Area is located.
+	 */
+	ulPRePOSAreaLength=0xffffffff;
+	ulPRePOSAreaOffset=0;
+
+	/*
+	 * Access the header at the start of NvRAM
+	 */
+	ReadNvRAM32((unsigned32)(&pNvHeader->OSAreaLength), &ulLength);
+	ReadNvRAM32((unsigned32)(&pNvHeader->OSAreaAddress), &ulOffset);
+
+	/*
+	 * Now set limits for future accesses
+	 */
+	ulPRePOSAreaLength=ulLength;
+	ulPRePOSAreaOffset=ulOffset;
+}
+
+
diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/prepnvr.h b/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/prepnvr.h
new file mode 100644
index 0000000000..cf55a4525d
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/prepnvr.h
@@ -0,0 +1,127 @@
+/* Structure map for NVRAM on PowerPC Reference Platform */
+ 
+/* Revision 1 changes (8/25/94):
+        - Power Management (RESTART_BLOCK struct)
+        - Normal added to PM_MODE
+        - OSIRQMask (HEADER struct) */
+ 
+/* All fields are either character/byte strings which are valid either
+endian or they are big-endian numbers.
+ 
+There are a number of Date and Time fields which are in RTC format,
+big-endian. These are stored in UT (GMT).
+ 
+For enum's: if given in hex then they are bit significant, i.e. only
+one bit is on for each enum.
+*/
+ 
+#ifndef _NVRAM_
+#define _NVRAM_
+
+#define VERSION  1
+#define REVISION 0
+ 
+#define OSAREASIZE 1024   /* size of OSArea space */
+#define CONFSIZE 512      /* guess at size of Configuration space */
+ 
+typedef struct _SECURITY {
+  unsigned long BootErrCnt;         /* Count of boot password errors */
+  unsigned long ConfigErrCnt;       /* Count of config password errors */
+  unsigned long BootErrorDT[2];     /* Date&Time from RTC of last error in pw */
+  unsigned long ConfigErrorDT[2];   /* Date&Time from RTC of last error in pw */
+  unsigned long BootCorrectDT[2];   /* Date&Time from RTC of last correct pw */
+  unsigned long ConfigCorrectDT[2]; /* Date&Time from RTC of last correct pw */
+  unsigned long BootSetDT[2];       /* Date&Time from RTC of last set of pw */
+  unsigned long ConfigSetDT[2];     /* Date&Time from RTC of last set of pw */
+  unsigned char Serial[16];         /* Box serial number */
+  } SECURITY;
+ 
+typedef enum _OS_ID {
+  Unknown = 0,
+  Firmware = 1,
+  AIX = 2,
+  NT = 3,
+  WPOS2 = 4,
+  WPAIX = 5,
+  Taligent = 6,
+  Solaris = 7,
+  Netware = 8,
+  USL = 9,
+  Low_End_Client = 10,
+  SCO = 11
+  } OS_ID;
+ 
+typedef struct _ERROR_LOG {
+  unsigned char ErrorLogEntry[40]; /* To be architected */
+  } ERROR_LOG;
+ 
+/*---Revision 1: Change the following struct:---*/
+typedef struct _RESUME_BLOCK {
+                                        /* Hibernation Resume Device will be an
+                                           environment variable */
+    unsigned long CheckSum;             /* Checksum of RESUME_BLOCK */
+    volatile unsigned long BootStatus;
+ 
+    void * ResumeAddr;                  /* For Suspend Resume */
+    void * SaveAreaAddr;                /* For Suspend Resume */
+    unsigned long SaveAreaLength;       /* For Suspend Resume */
+ 
+    unsigned long HibResumeImageRBA;    /* RBA (512B blocks) of compressed OS
+                                           memory image to be loaded by FW
+                                           on Resume from hibernation */
+    unsigned long HibResumeImageRBACount; /* Size of image in 512B blocks*/
+    unsigned long Reserved;
+  } RESUME_BLOCK;
+ 
+typedef enum _OSAREA_USAGE {
+  Empty = 0,
+  Used = 1
+  } OSAREA_USAGE;
+ 
+typedef enum _PM_MODE {
+  Suspend = 0x80,     /* Part of state is in memory */
+  Hibernate = 0x40,   /* Nothing in memory - state saved elsewhere */
+/* Revision 1: Normal added (actually was already here) */
+  Normal = 0x00       /* No power management in effect */
+  } PMMode;
+ 
+typedef struct _HEADER {
+  unsigned short Size;    /* NVRAM size in K(1024) */
+  unsigned char Version;  /* Structure map different */
+  unsigned char Revision; /* Structure map the same -
+                             may be new values in old fields
+                             in other words old code still works */
+  unsigned short Crc1;    /* check sum from beginning of nvram to OSArea */
+  unsigned short Crc2;    /* check sum of config */
+  unsigned char LastOS;   /* OS_ID */
+  unsigned char Endian;   /* B if big endian, L if little endian */
+  unsigned char OSAreaUsage; /* OSAREA_USAGE */
+  unsigned char PMMode;   /* Shutdown mode */
+  RESUME_BLOCK ResumeBlock;
+  SECURITY Security;
+  ERROR_LOG ErrorLog[2];
+ 
+/* Global Environment information */
+  void * GEAddress;
+  unsigned long GELength;
+  /* Date&Time from RTC of last change to Global Environment */
+  unsigned long GELastWriteDT[2];
+ 
+/* Configuration information */
+  void * ConfigAddress;
+  unsigned long ConfigLength;
+  /* Date&Time from RTC of last change to Configuration */
+  unsigned long ConfigLastWriteDT[2];
+  unsigned long ConfigCount; /* Count of entries in Configuration */
+ 
+/* OS dependent temp area */
+  void * OSAreaAddress;
+  unsigned long OSAreaLength;
+  /* Date&Time from RTC of last change to OSAreaArea */
+  unsigned long OSAreaLastWriteDT[2];
+ 
+/* Revision 1: add this mask - function tbd */
+  /*unsigned short OSIRQMask;  OS to FW IRQ Mask - "I've used this one" */
+  } HEADER, *PHEADER;
+ 
+ #endif  /* ndef _NVRAM_ */
diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/stk11c68.h b/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/stk11c68.h
new file mode 100644
index 0000000000..118662905b
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/stk11c68.h
@@ -0,0 +1,46 @@
+/*

+ *  COPYRIGHT (c) 1998 by Radstone Technology

+ *

+ *

+ * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY

+ * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE

+ * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK

+ * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.

+ *

+ * You are hereby granted permission to use, copy, modify, and distribute

+ * this file, provided that this notice, plus the above copyright notice

+ * and disclaimer, appears in all copies. Radstone Technology will provide

+ * no support for this code.

+ *

+ */

+

+/*

+ * Definitions for the stk11C68 NvRAM

+ */

+

+#ifndef _STK11C68_H

+#define _STK11C68_H

+

+#include "prepnvr.h"

+

+/*

+ * STK11C68 definitions

+ */

+#define STK11C68_NVSIZE 8192

+#define STK11C68_GESIZE (STK11C68_NVSIZE-CONFSIZE-OSAREASIZE-sizeof(HEADER))

+#define STK11C68_BASE (PSTK11C68_NVRAM_MAP)((unsigned8 *)PCI_MEM_BASE+0x00800000)

+

+/*

+ * STK11C88 definitions

+ */

+#define STK11C88_NVSIZE 0x8000-sizeof(MK48T18_CMOS_MAP)

+

+/* Here is the whole map of the STK11C68 NVRAM */

+typedef struct _STK11C68_NVRAM_MAP {

+	HEADER		Header;

+	unsigned8	GEArea[STK11C68_GESIZE];

+	unsigned8	OSArea[OSAREASIZE];

+	unsigned8	ConfigArea[CONFSIZE];

+} STK11C68_NVRAM_MAP, *PSTK11C68_NVRAM_MAP;

+

+#endif /* _STK11C68_H */