./clock/Makefile.in,v

./clock/clock.c,v
./console/Makefile.in,v
./console/config.c,v
./console/console.c,v
./console/console.h,v
./console/debugio.c,v
./console/i8042.c,v
./console/i8042_p.h,v
./console/i8042vga.c,v
./console/i8042vga.h,v
./console/ns16550.c,v
./console/ns16550.h,v
./console/ns16550_p.h,v
./console/ns16550cfg.c,v
./console/ns16550cfg.h,v
./console/vga.c,v
./console/vga_p.h,v
./console/z85c30.c,v
./console/z85c30.h,v
./console/z85c30_p.h,v
./console/z85c30cfg.c,v
./console/z85c30cfg.h,v
./include/Makefile.in,v
./include/bsp.h,v
./include/chain.h,v
./include/coverhd.h,v
./include/extisrdrv.h,v
./include/nvram.h,v
./include/pci.h,v
./include/tod.h,v
./network/Makefile.in,v
./network/amd79c970.c,v
./network/amd79c970.h,v
./nvram/Makefile.in,v
./nvram/ds1385.h,v
./nvram/mk48t18.h,v
./nvram/nvram.c,v
./nvram/prepnvr.h,v
./nvram/stk11c68.h,v
./pci/Makefile.in,v
./pci/pci.c,v
./start/Makefile.in,v
./start/start.s,v
./startup/Makefile.in,v
./startup/bspclean.c,v
./startup/bspstart.c,v
./startup/bsptrap.s,v
./startup/device-tree,v
./startup/genpvec.c,v
./startup/linkcmds,v
./startup/rtems-ctor.cc,v
./startup/sbrk.c,v
./startup/setvec.c,v
./startup/spurious.c,v
./startup/swap.c,v
./timer/Makefile.in,v
./timer/timer.c,v
./tod/Makefile.in,v
./tod/cmos.h,v
./tod/tod.c,v
./universe/Makefile.in,v
./universe/universe.c,v
./vectors/Makefile.in,v
./vectors/README,v
./vectors/align_h.s,v
./vectors/vectors.s,v
./wrapup/Makefile.in,v
./Makefile.in,v
./README,v
./STATUS,v
./bsp_specs,v

8 files changed, 1443 insertions, 0 deletions

diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/include/Makefile.in b/c/src/lib/libbsp/powerpc/ppcn_60x/include/Makefile.in
new file mode 100644
index 0000000000..011a5629e2
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/ppcn_60x/include/Makefile.in
@@ -0,0 +1,36 @@
+#
+#  $Id$
+#
+
+@SET_MAKE@
+srcdir = @srcdir@
+VPATH = @srcdir@
+RTEMS_ROOT = @top_srcdir@
+PROJECT_ROOT = @PROJECT_ROOT@
+
+H_FILES = $(srcdir)/bsp.h $(srcdir)/coverhd.h $(srcdir)/chain.h \
+  $(srcdir)/tod.h $(srcdir)/nvram.h $(srcdir)/pci.h
+
+#
+#  Equate files are for including from assembly preprocessed by
+#  gm4 or gasp.  No examples are provided except for those for
+#  other CPUs.  The best way to generate them would be to
+#  provide a program which generates the constants used based
+#  on the C equivalents.
+#
+#  If you add equate files, don't forget to uncomment the install line
+#  below.
+#
+
+EQ_FILES =
+
+SRCS=$(H_FILES) $(EQ_FILES)
+
+include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
+include $(RTEMS_ROOT)/make/leaf.cfg
+
+CLEAN_ADDITIONS +=
+CLOBBER_ADDITIONS +=
+
+all:	$(SRCS)
+	$(INSTALL) -m 444 $(H_FILES) $(PROJECT_INCLUDE)
diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/include/bsp.h b/c/src/lib/libbsp/powerpc/ppcn_60x/include/bsp.h
new file mode 100644
index 0000000000..98fc0781bf
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/ppcn_60x/include/bsp.h
@@ -0,0 +1,465 @@
+/*  bsp.h
+ *
+ *  This include file contains all board IO definitions.
+ *
+ *  COPYRIGHT (c) 1998 by Radstone Technology
+ *
+ *
+ * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
+ * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
+ * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
+ *
+ * You are hereby granted permission to use, copy, modify, and distribute
+ * this file, provided that this notice, plus the above copyright notice
+ * and disclaimer, appears in all copies. Radstone Technology will provide
+ * no support for this code.
+ *
+ *  COPYRIGHT (c) 1989-1997.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may in
+ *  the file LICENSE in this distribution or at
+ *  http:www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#ifndef __BSP_h
+#define __BSP_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*  Define processor identification. */
+
+#define MPC601	1
+#define MPC603	3
+#define MPC604	4
+#define MPC603e 6
+#define MPC603ev 7
+#define MPC604e 9
+
+#ifdef ASM
+/* Definition of where to store registers in alignment handler */
+#define ALIGN_REGS 0x0140
+
+/*  BAT register definitions for the MPC603 and MPC604. */
+/*  Define bit fields for upper MPC603/4 BAT registers. */
+
+#define BEPI_FIELD_60X      0xFFFE0000
+#define VALID_SUPERVISOR    0x2
+#define VALID_PROBLEM       0x1
+#define KEY_USER_60X        0x1
+#define BL_128K        0x0
+#define BL_256K        (0x1<2)
+#define BL_512K        (0x3<2)
+#define BL_1M          (0x7<2)
+#define BL_2M          (0xF<2)
+#define BL_4M          (0x1F<2)
+#define BL_8M          (0x3F<2)
+#define BL_16M         (0x7F<2)
+#define BL_32M         (0xFF<2)
+#define BL_64M         (0x1FF<2)
+#define BL_128M        (0x3FF<2)
+#define BL_256M        (0x7FF<2)
+
+
+/*  Define bit fields for lower MPC603/4 BAT registers. */
+
+#define BRPN_FIELD_60X      0xFFFE0000
+
+/*  Common defines for BAT registers. */
+/*  Depending on the processor, the following may be in the upper */
+/*  and lower BAT register. */
+
+#define WRITE_THRU      0x40
+#define WRITE_BK        0x0
+#define COHERE_EN       0x10
+#define COHERE_DIS      0x0
+#define CACHE_DIS	0x20
+#define CACHE_EN	0x0
+#define GUARDED_EN      0x8
+#define GUARDED_DIS     0x0
+#define PP_00           0x0
+#define PP_01           0x1
+#define PP_10           0x2
+#define PP_11           0x3
+
+/*  HID0 definitions for MPC603 and MPC604 */
+#define HID0		0x3f0      /*  HID0 Special Purpose Register # */
+/*  HID1 definitions for MPC603e and MPC604e */
+#define HID1		0x3f1      /*  HID1 Special Purpose Register # */
+
+#define	H0_603_ICFI	0x0800     /*  HID0 I-Cache Flash Invalidate */
+#define	H0_603_DCI	0x0400     /*  HID0 D-Cache Flash Invalidate */
+
+#define	H0_60X_ICE	0x8000     /*  HID0 I-Cache Enable */
+#define	H0_60X_DCE	0x4000     /*  HID0 D-Cache Enable */
+
+#define	H0_604_BHTE	0x0004     /*  HID0 Branch History Table enable */
+#define	H0_604_SIED	0x0080     /*  HID0 Serial Instruction Execution */
+#define	H0_604_ICIA	0x0800     /*  HID0 I-Cache Invalidate All */
+#define	H0_604_DCIA	0x0400     /*  HID0 D-Cache Invalidate All */
+
+#define BAT0U           528
+#define BAT0L           529
+#define BAT1U           530
+#define BAT1L           531
+#define BAT2U           532
+#define BAT2L           533
+#define BAT3U           534
+#define BAT3L           535
+#define SPRG0           272
+#define SPRG1           273
+
+/* MSR bit settings */
+#define MSR_LE		0x0001
+#define MSR_RI		0x0002
+#define MSR_DR		0x0010
+#define MSR_IR		0x0020
+#define MSR_IP		0x0040
+#define MSR_FE1		0x0100
+#define MSR_BE		0x0200
+#define MSR_SE		0x0400
+#define MSR_FE0		0x0800
+#define MSR_ME		0x1000
+#define MSR_FP		0x2000
+#define MSR_PR		0x4000
+#define MSR_EE		0x8000
+#define MSR_ILE		0x0001	/* Upper 16 bits */
+#define MSR_POW		0x0004	/* Upper 16 bits */
+#else
+#include <rtems.h>
+#include <console.h>
+#include <clockdrv.h>
+#include <iosupp.h>
+#include <tod.h>
+#include <nvram.h>
+
+/*
+ *  PPCn_60x Interupt Definations.
+ */
+#define PPCN_60X_8259_IRQ_BASE ( PPC_IRQ_LAST +  1 )
+
+/*
+ * 8259 IRQ definations.
+ */
+#define PPCN_60X_IRQ_SYS_TIMER	(PPCN_60X_8259_IRQ_BASE +  0)  
+#define PPCN_60X_IRQ_KBD		(PPCN_60X_8259_IRQ_BASE +  1)  
+#define PPCN_60X_IRQ_COM2		(PPCN_60X_8259_IRQ_BASE +  3)
+#define PPCN_60X_IRQ_COM1		(PPCN_60X_8259_IRQ_BASE +  4)
+#define PPCN_60X_IRQ_CIO		(PPCN_60X_8259_IRQ_BASE +  5)
+#define PPCN_60X_IRQ_FDC		(PPCN_60X_8259_IRQ_BASE +  6)
+#define PPCN_60X_IRQ_LPT		(PPCN_60X_8259_IRQ_BASE +  7)
+#define PPCN_60X_IRQ_RTC		(PPCN_60X_8259_IRQ_BASE +  8)
+#define PPCN_60X_IRQ_COM3_4		(PPCN_60X_8259_IRQ_BASE + 10)
+#define PPCN_60X_IRQ_MSE		(PPCN_60X_8259_IRQ_BASE + 12)
+#define PPCN_60X_IRQ_SCSI		(PPCN_60X_8259_IRQ_BASE + 13)
+
+/*
+ * PCI interrupts as read from line register map directly to
+ * ISA interrupt lines 9, 11, 14 and 15.
+ */
+#define PPCN_60X_IRQ_PCI(n)		(PPCN_60X_8259_IRQ_BASE +  (n))
+
+#define MAX_BOARD_IRQS          (PPCN_60X_8259_IRQ_BASE + 15)
+
+#define ISA8259_M_CTRL 0x20
+#define ISA8259_S_CTRL 0xa0
+#define ISA8259_M_MASK 0x21
+#define ISA8259_S_MASK 0xa1
+#define ISA8259_M_ELCR 0x4d0
+#define ISA8259_S_ELCR 0x4d1
+
+#define ELCRS_INT15_LVL		0x80
+#define ELCRS_INT14_LVL		0x40
+#define ELCRS_INT12_LVL		0x10
+#define ELCRS_INT11_LVL		0x08
+#define ELCRS_INT10_LVL		0x04
+#define ELCRS_INT9_LVL		0x02
+#define ELCRS_INT8_LVL		0x01
+#define ELCRM_INT7_LVL		0x80
+#define ELCRM_INT5_LVL		0x20
+
+
+#define NONSPECIFIC_EOI 0x20
+
+extern void En_Ext_Interrupt(int level);
+extern void Dis_Ext_Interrupt(int level);
+
+#define IRQ_VECTOR_BASE	0xbffffff0
+
+/*
+ * i8042 addresses
+ */
+#define I8042_DATA	0x60
+#define I8042_CS	0x64
+
+/*
+ * ns16550 addresses
+ */
+#define NS16550_PORT_A	0x3f8
+#define NS16550_PORT_B	0x2f8
+
+/*
+ * z85c30 addresses
+ */
+#define Z85C30_CTRL_B	0x840
+#define Z85C30_DATA_B	0x841
+#define Z85C30_CTRL_A	0x842
+#define Z85C30_DATA_A	0x843
+
+/*
+ *  Z85C30 Definations for the 422 interface.
+ */
+#define Z85C30_CLOCK     14745600
+
+#define PCI_SYS_MEM_BASE	0x80000000
+#define PCI_MEM_BASE		0xc0000000
+#define PCI_IO_BASE		0x80000000
+
+#define EIEIO asm volatile("eieio")
+
+/*
+ * As ports are all little endian we will perform swaps here on 16 and 32
+ * bit transfers
+ */
+extern unsigned16 Swap16(unsigned16 usVal);
+extern unsigned32 Swap32(unsigned32 ulVal);
+
+#define outport_byte(port, val)			\
+	EIEIO;					\
+	*(volatile unsigned8 *)(PCI_IO_BASE+	\
+				(unsigned long)(port))=(val)
+
+#define outport_16(port, val) 			\
+	EIEIO;					\
+	*(volatile unsigned16 *)(PCI_IO_BASE+	\
+				 (unsigned long)(port))=Swap16(val)
+
+#define outport_32(port, val) 			\
+	EIEIO;					\
+	*(volatile unsigned32 *)(PCI_IO_BASE+	\
+				 (unsigned long)(port))=Swap32(val)
+
+#define inport_byte(port, val)				\
+	EIEIO;						\
+	(val)=*(volatile unsigned8 *)(PCI_IO_BASE+	\
+				      (unsigned long)(port))
+
+#define inport_16(port, val)					\
+	EIEIO;							\
+	(val)=Swap16(*(volatile unsigned16 *)(PCI_IO_BASE+	\
+					      (unsigned long)(port)))
+
+#define inport_32(port, val)					\
+	EIEIO;							\
+	(val)=Swap32(*(volatile unsigned32 *)(PCI_IO_BASE+	\
+					      (unsigned long)(port)))
+
+/*
+ *  System Planar Board Registers
+ */
+typedef volatile struct _PLANARREGISTERS{
+    unsigned8 Reserved0[0x803];     /* Offset 0x000 */
+    unsigned8 SimmId;               /* Offset 0x803 */
+    unsigned8 SimmPresent;          /* Offset 0x804 */
+    unsigned8 Reserved1[3];
+    unsigned8 HardfileLight;        /* Offset 0x808 */
+    unsigned8 Reserved2[3];
+    unsigned8 EquipmentPresent1;    /* Offset 0x80C */
+    unsigned8 Reserved3;
+    unsigned8 EquipmentPresent2;    /* Offset 0x80e */
+    unsigned8 Reserved4;
+    unsigned8 PasswordProtect1;     /* Offset 0x810 */
+    unsigned8 Reserved5;
+    unsigned8 PasswordProtect2;     /* Offset 0x812 */
+    unsigned8 Reserved6;
+    unsigned8 L2Flush;              /* Offset 0x814 */
+    unsigned8 Reserved7[3];
+    unsigned8 Keylock;              /* Offset 0x818 */
+    unsigned8 Reserved8[0x3c];
+    unsigned8 BoardRevision;		/* Offset 0x854 */
+    unsigned8 Reserved9[0xf];
+    unsigned8 BoardID;				/* Offset 0x864 */
+    unsigned8 Reserved10;
+    unsigned8 MotherboardMemoryType; /* Offset 0x866 */
+    unsigned8 Reserved11;
+    unsigned8 MezzanineMemoryType;  /* Offset 0x868 */
+} PLANARREGISTERS, *PPLANARREGISTERS;
+
+extern unsigned char ucSystemType;
+extern unsigned char ucBoardRevMaj;
+extern unsigned char ucBoardRevMin;
+extern unsigned long ulMemorySize;
+extern unsigned long ulCpuBusClock;
+
+#define SYS_TYPE_PPC1	0
+#define SYS_TYPE_PPC2	1
+#define SYS_TYPE_PPC1a	2
+#define SYS_TYPE_PPC2a	3
+#define SYS_TYPE_PPC4	4
+
+/*
+ * PCI initialisation
+ */
+void InitializePCI(void);
+
+/*
+ * VME initiaisation
+ */
+void InitializeUniverse();
+
+/*
+ * RTC initialisation
+ */
+void InitializeRTC(void);
+
+/*
+ * NvRAM initialisation
+ */
+void InitializeNvRAM(void);
+
+/*
+ *  BSP_TIMER_AVG_OVERHEAD and BSP_TIMER_LEAST_VALID for the shared timer
+ *  driver.
+ */
+
+#define BSP_TIMER_AVG_OVERHEAD   4  /* It typically takes xx clicks        */
+                                    /*     to start/stop the timer.        */
+#define BSP_TIMER_LEAST_VALID    1  /* Don't trust a value lower than this */
+
+/*
+ *  Convert decrement value to tenths of microsecnds (used by 
+ *  shared timer driver).
+ *
+ *    + There are 4 bus cycles per click
+ *    + We return value in 1/10 microsecond units.
+ *   Modified following equation to integer equation to remove
+ *   floating point math.
+ *   (int) ((float)(_value) / ((66.67 * 0.1) / 4.0))
+ */
+
+#define BSP_Convert_decrementer( _value ) \
+  (int) (((_value) * 4000) / (ulCpuBusClock/10000))
+
+/*
+ *  Define the time limits for RTEMS Test Suite test durations.
+ *  Long test and short test duration limits are provided.  These
+ *  values are in seconds and need to be converted to ticks for the
+ *  application.
+ *
+ */
+
+#define MAX_LONG_TEST_DURATION       300 /* 5 minutes = 300 seconds */
+#define MAX_SHORT_TEST_DURATION      3   /* 3 seconds */
+
+/*
+ *  Stuff for Time Test 27
+ */
+
+#define MUST_WAIT_FOR_INTERRUPT 1
+
+#define Install_tm27_vector( _handler ) \
+  set_vector( (_handler), PPC_IRQ_DECREMENTER, 1 )
+
+#define Cause_tm27_intr()  \
+  do { \
+    unsigned32 _clicks = 8; \
+    asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
+  } while (0)
+
+
+#define Clear_tm27_intr() \
+  do { \
+    unsigned32 _clicks = 0xffffffff; \
+    asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
+  } while (0)
+
+#define Lower_tm27_intr() \
+  do { \
+    unsigned32 _msr = 0; \
+    _ISR_Set_level( 0 ); \
+    asm volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
+    _msr |=  0x8002; \
+    asm volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
+  } while (0)
+
+
+/* Constants */
+
+/*
+ *  Device Driver Table Entries
+ */
+ 
+/*
+ * NOTE: Use the standard Console driver entry
+ */
+ 
+/*
+ * NOTE: Use the standard Clock driver entry
+ */
+ 
+/*
+ * How many libio files we want
+ */
+ 
+#define BSP_LIBIO_MAX_FDS       20
+
+/* functions */
+
+void bsp_start( void );
+
+void bsp_cleanup( void );
+
+rtems_isr_entry set_vector(                    /* returns old vector */
+  rtems_isr_entry     handler,                  /* isr routine        */
+  rtems_vector_number vector,                   /* vector number      */
+  int                 type                      /* RTEMS or RAW intr  */
+);
+
+/*
+ * spurious.c
+ */
+rtems_isr bsp_stub_handler(
+   rtems_vector_number trap
+); 
+rtems_isr bsp_spurious_handler(
+   rtems_vector_number trap
+);
+void bsp_spurious_initialize();
+
+/* 
+ * genvec.c
+ */
+void set_EE_vector(
+  rtems_isr_entry     handler,                  /* isr routine        */
+  rtems_vector_number vector                    /* vector number      */
+);
+void initialize_external_exception_vector();
+
+/*
+ * console.c
+ */
+void DEBUG_puts( char *string );
+void DEBUG_puth( unsigned32 ulHexNum );
+
+void BSP_fatal_return( void );
+
+extern rtems_configuration_table BSP_Configuration;     /* owned by BSP */
+
+extern rtems_cpu_table           Cpu_table;             /* owned by BSP */
+
+extern unsigned32          bsp_isr_level;
+
+#endif /* ASM */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/* end of include file */
diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/include/chain.h b/c/src/lib/libbsp/powerpc/ppcn_60x/include/chain.h
new file mode 100644
index 0000000000..98cf2b1a86
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/ppcn_60x/include/chain.h
@@ -0,0 +1,362 @@
+/*  chain.h
+ * 
+ *  This include file contains all the constants and structures associated
+ *  with doubly linked chains.  This file actually just provides an
+ *  interface to the chain object in rtems.
+ *
+ *  COPYRIGHT (c) 1989-1997.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may in
+ *  the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ * $ld:
+ */
+
+#ifndef __CHAIN_h
+#define __CHAIN_h
+
+#include <rtems.h>
+
+/* 
+ *  Chain_Initialize
+ *
+ *  This routine initializes the_chain structure to manage the
+ *  contiguous array of number_nodes nodes which starts at
+ *  starting_address.  Each node is of node_size bytes.
+ *
+ *  Chain_Control                    *the_chain,		 * IN  * 
+ *  void                             *starting_address,		 * IN  * 
+ *  rtems_unsigned32                  number_nodes,		 * IN  * 
+ *  rtems_unsigned32                  node_size			 * IN  * 
+ */
+
+#define Chain_Initialize( the_chain, starting_address, \
+                          number_nodes, node_size ) \
+       _Chain_Initialize( the_chain, starting_address, \
+                          number_nodes, node_size ) \
+
+
+/* 
+ *  Chain_Initialize_empty
+ *
+ *  This routine initializes the specified chain to contain zero nodes.
+ *
+ *  Chain_Control                    *the_chain			 * IN  * 
+ */
+
+#define Chain_Initialize_empty( the_chain ) \
+       _Chain_Initialize_empty( the_chain )
+ 
+
+/*
+ *  Chain_Are_nodes_equal
+ *
+ *  This function returns TRUE if LEFT and RIGHT are equal,
+ *  and FALSE otherwise.
+ *
+ *  Chain_Node                       *left,			 * IN  * 
+ *  Chain_Node                       *right			 * IN  * 
+ */
+ 
+#define Chain_Are_nodes_equal( left, right ) \
+       _Chain_Are_nodes_equal( left, right )
+
+
+/* 
+ *  Chain_Extract_unprotected
+ *
+ *  This routine extracts the_node from the chain on which it resides.
+ *  It does NOT disable interrupts to insure the atomicity of the
+ *  extract operation.
+ *
+ *  Chain_Node                       *the_node			 * IN  * 
+ */
+
+#define Chain_Extract_unprotected( the_node ) \
+       _Chain_Extract_unprotected( the_node )
+
+
+/* 
+ *  Chain_Extract
+ *
+ *  This routine extracts the_node from the chain on which it resides.
+ *  It disables interrupts to insure the atomicity of the
+ *  extract operation.
+ *
+ *  Chain_Node                       *the_node			 * IN  * 
+ */
+
+#define Chain_Extract( the_node ) \
+       _Chain_Extract( the_node )
+
+
+/* 
+ *  Chain_Get_unprotected
+ *
+ *  This function removes the first node from the_chain and returns
+ *  a pointer to that node.  If the_chain is empty, then NULL is returned.
+ *  It does NOT disable interrupts to insure the atomicity of the
+ *  get operation.
+ *
+ *  Chain_Control                    *the_chain			 * IN  * 
+ */
+
+#define Chain_Get_unprotected( the_chain ) \
+       _Chain_Get_unprotected( the_chain )
+
+
+/* 
+ *  Chain_Get
+ *
+ *  This function removes the first node from the_chain and returns
+ *  a pointer to that node.  If the_chain is empty, then NULL is returned.
+ *  It disables interrupts to insure the atomicity of the
+ *  get operation.
+ *
+ *  Chain_Control                    *the_chain			 * IN  * 
+ */
+
+#define Chain_Get( the_chain ) \
+       _Chain_Get( the_chain )
+
+
+/* 
+ *  Chain_Get_first_unprotected
+ *
+ *  This function removes the first node from the_chain and returns
+ *  a pointer to that node.  It does NOT disable interrupts to insure
+ *  the atomicity of the get operation.
+ *
+ *  Chain_Control                    *the_chain			 * IN  * 
+ */
+
+#define Chain_Get_first_unprotected( the_chain ) \
+       _Chain_Get_first_unprotected( the_chain )
+
+
+/* 
+ *  Chain_Insert_unprotected
+ *
+ *  This routine inserts the_node on a chain immediately following
+ *  after_node.  It does NOT disable interrupts to insure the atomicity
+ *  of the extract operation.
+ *
+ *  Chain_Node                       *after_node,		 * IN  * 
+ *  Chain_Node                       *the_node			 * IN  * 
+ */
+
+#define Chain_Insert_unprotected( after_node, the_node ) \
+       _Chain_Insert_unprotected( after_node, the_node )
+
+
+/* 
+ *  Chain_Insert
+ *
+ *  This routine inserts the_node on a chain immediately following
+ *  after_node.  It disables interrupts to insure the atomicity
+ *  of the extract operation.
+ *
+ *  Chain_Node                       *after_node,		 * IN  * 
+ *  Chain_Node                       *the_node			 * IN  * 
+ */
+
+#define Chain_Insert( after_node, the_node ) \
+       _Chain_Insert( after_node, the_node )
+
+
+/* 
+ *  Chain_Append_unprotected
+ *
+ *  This routine appends the_node onto the end of the_chain.
+ *  It does NOT disable interrupts to insure the atomicity of the
+ *  append operation.
+ *
+ *  Chain_Control                    *the_chain,		 * IN  * 
+ *  Chain_Node                       *the_node			 * IN  * 
+ */
+
+#define Chain_Append_unprotected( the_chain, the_node ) \
+       _Chain_Append_unprotected( the_chain, the_node )
+
+
+/* 
+ *  Chain_Append
+ *
+ *  This routine appends the_node onto the end of the_chain.
+ *  It disables interrupts to insure the atomicity of the
+ *  append operation.
+ *
+ *  Chain_Control                    *the_chain,		 * IN  * 
+ *  Chain_Node                       *the_node			 * IN  * 
+ */
+
+#define Chain_Append( the_chain, the_node ) \
+       _Chain_Append( the_chain, the_node )
+
+
+/* 
+ *  Chain_Prepend_unprotected
+ *
+ *  This routine prepends the_node onto the front of the_chain.
+ *  It does NOT disable interrupts to insure the atomicity of the
+ *  prepend operation.
+ *
+ *  Chain_Control                    *the_chain,		 * IN  * 
+ *  Chain_Node                       *the_node			 * IN  * 
+ */
+
+#define Chain_Prepend_unprotected( the_chain, the_node ) \
+       _Chain_Prepend_unprotected( the_chain, the_node )
+
+
+/* 
+ *  Chain_Prepend
+ *
+ *  This routine prepends the_node onto the front of the_chain.
+ *  It disables interrupts to insure the atomicity of the
+ *  prepend operation.
+ *
+ *  Chain_Control                    *the_chain,		 * IN  * 
+ *  Chain_Node                       *the_node			 * IN  * 
+ */
+
+#define Chain_Prepend( the_chain, the_node ) \
+       _Chain_Prepend( the_chain, the_node )
+
+
+/* 
+ *  Chain_Head
+ *
+ *  This function returns a pointer to the first node on the chain.
+ *
+ *  Chain_Control                    *the_chain			 * IN  * 
+ */
+
+#define Chain_Head( the_chain ) \
+       _Chain_Head( the_chain )
+
+
+/* 
+ *  Chain_Tail
+ *
+ *  This function returns a pointer to the last node on the chain.
+ *
+ *  Chain_Control                    *the_chain			 * IN  * 
+ */
+
+#define Chain_Tail( the_chain ) \
+       _Chain_Tail( the_chain )
+
+
+/* 
+ *  Chain_Is_head
+ *
+ *  This function returns TRUE if the_node is the head of the_chain and
+ *  FALSE otherwise.
+ *
+ *  Chain_Control                    *the_chain,		 * IN  * 
+ *  Chain_Node                       *the_node			 * IN  * 
+ */
+
+#define Chain_Is_head( the_chain, the_node ) \
+       _Chain_Is_head( the_chain, the_node )
+
+
+/* 
+ *  Chain_Is_tail
+ *
+ *  This function returns TRUE if the_node is the tail of the_chain and
+ *  FALSE otherwise.
+ *
+ *  Chain_Control                    *the_chain,		 * IN  * 
+ *  Chain_Node                       *the_node			 * IN  * 
+ */
+
+#define Chain_Is_tail( the_chain, the_node ) \
+       _Chain_Is_tail( the_chain, the_node )
+
+
+/* 
+ *  Chain_Is_first
+ *
+ *  This function returns TRUE if the_node is the first node on a chain and
+ *  FALSE otherwise.
+ *
+ *  Chain_Node                       *the_node			 * IN  * 
+ */
+
+#define Chain_Is_first( the_node ) \
+       _Chain_Is_first( the_node )
+
+
+/* 
+ *  Chain_Is_last
+ *
+ *  This function returns TRUE if the_node is the last node on a chain and
+ *  FALSE otherwise.
+ *
+ *  Chain_Node                       *the_node			 * IN  * 
+ */
+
+#define Chain_Is_last( the_node ) \
+       _Chain_Is_last( the_node )
+
+
+/* 
+ *  Chain_Is_empty
+ *
+ *  This function returns TRUE if there are no nodes on the_chain and
+ *  FALSE otherwise.
+ *
+ *  Chain_Control                    *the_chain			 * IN  * 
+ */
+
+#define Chain_Is_empty( the_chain ) \
+       _Chain_Is_empty( the_chain )
+
+
+/* 
+ *  Chain_Has_only_one_node
+ *
+ *  This function returns TRUE if there is only one node on the_chain and
+ *  FALSE otherwise.
+ *
+ *  Chain_Control                    *the_chain			 * IN  * 
+ */
+
+#define Chain_Has_only_one_node( the_chain ) \
+       _Chain_Has_only_one_node( the_chain )
+
+
+/* 
+ *  Chain_Is_null
+ *
+ *  This function returns TRUE if the_chain is NULL and FALSE otherwise.
+ *
+ *  Chain_Control                    *the_chain			 * IN  * 
+ */
+
+#define Chain_Is_null( the_chain ) \
+       _Chain_Is_null( the_chain )
+
+
+/* 
+ *  Chain_Is_null_node
+ *
+ *  This function returns TRUE if the_node is NULL and FALSE otherwise.
+ *
+ *  Chain_Node                       *the_node			 * IN  * 
+ */
+
+#define Chain_Is_null_node( the_node ) \
+       _Chain_Is_null_node( the_node )
+
+
+#undef __RTEMS_APPLICATION__
+#include <rtems/score/chain.inl>
+#define __RTEMS_APPLICATION__
+#endif
+/* end of include file */
diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/include/coverhd.h b/c/src/lib/libbsp/powerpc/ppcn_60x/include/coverhd.h
new file mode 100644
index 0000000000..340c5ca16d
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/ppcn_60x/include/coverhd.h
@@ -0,0 +1,119 @@
+/*  coverhd.h
+ *
+ *  This include file has defines to represent the overhead associated
+ *  with calling a particular directive from C.  These are used in the
+ *  Timing Test Suite to ignore the overhead required to pass arguments
+ *  to directives.  On some CPUs and/or target boards, this overhead
+ *  is significant and makes it difficult to distinguish internal
+ *  RTEMS execution time from that used to call the directive.
+ *  This file should be updated after running the C overhead timing
+ *  test.  Once this update has been performed, the RTEMS Time Test
+ *  Suite should be rebuilt to account for these overhead times in the
+ *  timing results.
+ *
+ *  NOTE:  If these are all zero, then the times reported include
+ *         calling overhead including passing of arguments.
+ *
+ *
+ *  COPYRIGHT (c) 1989-1997.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may in
+ *  the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#ifndef __COVERHD_h
+#define __COVERHD_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE      0
+#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE        0
+#define CALLING_OVERHEAD_TASK_CREATE               0
+#define CALLING_OVERHEAD_TASK_IDENT                0
+#define CALLING_OVERHEAD_TASK_START                0
+#define CALLING_OVERHEAD_TASK_RESTART              0
+#define CALLING_OVERHEAD_TASK_DELETE               0
+#define CALLING_OVERHEAD_TASK_SUSPEND              0
+#define CALLING_OVERHEAD_TASK_RESUME               0
+#define CALLING_OVERHEAD_TASK_SET_PRIORITY         0
+#define CALLING_OVERHEAD_TASK_MODE                 0
+#define CALLING_OVERHEAD_TASK_GET_NOTE             0
+#define CALLING_OVERHEAD_TASK_SET_NOTE             0
+#define CALLING_OVERHEAD_TASK_WAKE_WHEN            0
+#define CALLING_OVERHEAD_TASK_WAKE_AFTER           0
+#define CALLING_OVERHEAD_INTERRUPT_CATCH           0
+#define CALLING_OVERHEAD_CLOCK_GET                 0
+#define CALLING_OVERHEAD_CLOCK_SET                 0
+#define CALLING_OVERHEAD_CLOCK_TICK                0
+
+#define CALLING_OVERHEAD_TIMER_CREATE              0
+#define CALLING_OVERHEAD_TIMER_IDENT               0
+#define CALLING_OVERHEAD_TIMER_DELETE              0
+#define CALLING_OVERHEAD_TIMER_FIRE_AFTER          0
+#define CALLING_OVERHEAD_TIMER_FIRE_WHEN           0
+#define CALLING_OVERHEAD_TIMER_RESET               0
+#define CALLING_OVERHEAD_TIMER_CANCEL              0
+#define CALLING_OVERHEAD_SEMAPHORE_CREATE          0
+#define CALLING_OVERHEAD_SEMAPHORE_IDENT           0
+#define CALLING_OVERHEAD_SEMAPHORE_DELETE          0
+#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN          0 
+#define CALLING_OVERHEAD_SEMAPHORE_RELEASE         0 
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE      0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT       0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE      0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND        0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT      0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST   0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE     0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH       0
+
+#define CALLING_OVERHEAD_EVENT_SEND                0
+#define CALLING_OVERHEAD_EVENT_RECEIVE             0
+#define CALLING_OVERHEAD_SIGNAL_CATCH              0
+#define CALLING_OVERHEAD_SIGNAL_SEND               0
+#define CALLING_OVERHEAD_PARTITION_CREATE          0
+#define CALLING_OVERHEAD_PARTITION_IDENT           0
+#define CALLING_OVERHEAD_PARTITION_DELETE          0
+#define CALLING_OVERHEAD_PARTITION_GET_BUFFER      0
+#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER   0
+#define CALLING_OVERHEAD_REGION_CREATE             0
+#define CALLING_OVERHEAD_REGION_IDENT              0
+#define CALLING_OVERHEAD_REGION_DELETE             0
+#define CALLING_OVERHEAD_REGION_GET_SEGMENT        0
+#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT     0
+#define CALLING_OVERHEAD_PORT_CREATE               0
+#define CALLING_OVERHEAD_PORT_IDENT                0
+#define CALLING_OVERHEAD_PORT_DELETE               0 
+#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 0 
+#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 0
+
+#define CALLING_OVERHEAD_IO_INITIALIZE             0
+#define CALLING_OVERHEAD_IO_OPEN                   0
+#define CALLING_OVERHEAD_IO_CLOSE                  0
+#define CALLING_OVERHEAD_IO_READ                   0
+#define CALLING_OVERHEAD_IO_WRITE                  0
+#define CALLING_OVERHEAD_IO_CONTROL                0
+#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED      0
+#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE     0
+#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT      0
+#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE     0
+#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL     0
+#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD     0
+#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE  0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/* end of include file */
+
+
+
diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/include/extisrdrv.h b/c/src/lib/libbsp/powerpc/ppcn_60x/include/extisrdrv.h
new file mode 100644
index 0000000000..32d0e7562c
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/ppcn_60x/include/extisrdrv.h
@@ -0,0 +1,41 @@
+/*  extisrdrv.h
+ *
+ *  This file describes the external interrupt driver
+ *
+ */
+
+#ifndef __EXT_ISR_DRIVER_H
+#define __EXT_ISR_DRIVER_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* variables */
+
+extern rtems_device_major_number rtems_externalISR_major;
+extern rtems_device_minor_number rtems_externalISR_minor;
+
+/* default external ISR driver entry */
+
+#define EXTISR_DRIVER_TABLE_ENTRY \
+  { ExternalISR_initialize, NULL, NULL, NULL, NULL, ExternalISR_control }
+ 
+rtems_device_driver ExternalISR_initialize(
+  rtems_device_major_number,
+  rtems_device_minor_number,
+  void *
+);
+
+rtems_device_driver ExternalISR_control(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void *pargp
+);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/* end of include file */
diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/include/nvram.h b/c/src/lib/libbsp/powerpc/ppcn_60x/include/nvram.h
new file mode 100644
index 0000000000..246c2679c5
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/ppcn_60x/include/nvram.h
@@ -0,0 +1,60 @@
+/*
+ *  This file contains the NvRAM driver definitions for the PPCn_60x
+ *
+ *  COPYRIGHT (c) 1998 by Radstone Technology
+ *
+ *
+ * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
+ * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
+ * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
+ *
+ * You are hereby granted permission to use, copy, modify, and distribute
+ * this file, provided that this notice, plus the above copyright notice
+ * and disclaimer, appears in all copies. Radstone Technology will provide
+ * no support for this code.
+ *
+ */
+
+#ifndef _NVRAM_H
+#define _NVRAM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ *  This initializes the NvRAM driver
+ */
+
+void InitializeNvRAM(void);
+
+
+/*
+ * These routines access data in the NvRAM's OS area
+ */
+extern rtems_status_code ReadNvRAM8(unsigned32 ulOffset, unsigned8 *pucData);
+extern rtems_status_code WriteNvRAM8(unsigned32 ulOffset, unsigned8 ucValue);
+extern rtems_status_code ReadNvRAM16(unsigned32 ulOffset, unsigned16 *pusData);
+extern rtems_status_code WriteNvRAM16(unsigned32 ulOffset, unsigned16 usValue);
+extern rtems_status_code ReadNvRAM32(unsigned32 ulOffset, unsigned32 *pulData);
+extern rtems_status_code WriteNvRAM32(unsigned32 ulOffset, unsigned32 ulValue);
+rtems_status_code ReadNvRAMBlock(
+  unsigned32 ulOffset, unsigned8 *pucData, unsigned32 length);
+rtems_status_code WriteNvRAMBlock(
+  unsigned32 ulOffset, unsigned8 *ucValue, unsigned32 length);
+/*
+ * This routine returns the size of the NvRAM
+ */
+extern unsigned32 SizeNvRAM();
+
+/*
+ * This routine commits changes to the NvRAM
+ */
+extern void CommitNvRAM();
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _NVRAM_H */
diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/include/pci.h b/c/src/lib/libbsp/powerpc/ppcn_60x/include/pci.h
new file mode 100644
index 0000000000..f012d882d7
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/ppcn_60x/include/pci.h
@@ -0,0 +1,322 @@
+/*
+ *  COPYRIGHT (c) 1998 by Radstone Technology
+ *
+ *
+ * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
+ * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
+ * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
+ *
+ * You are hereby granted permission to use, copy, modify, and distribute
+ * this file, provided that this notice, plus the above copyright notice
+ * and disclaimer, appears in all copies. Radstone Technology will provide
+ * no support for this code.
+ *
+ */
+#ifndef _PCI_H_
+#define _PCI_H_
+
+/*
+ * PCI Configuration space definitions
+ */
+
+#define PCI_CONFIG_ADDR	0xcf8
+#define PCI_CONFIG_DATA	0xcfc
+
+#define PCI_MAX_DEVICES		16
+#define PCI_MAX_FUNCTIONS	8
+
+#define PCI_CONFIG_VENDOR_LOW		0x00
+#define PCI_CONFIG_VENDOR_HIGH		0x01
+#define PCI_CONFIG_DEVICE_LOW		0x02
+#define PCI_CONFIG_DEVICE_HIGH		0x03
+#define PCI_CONFIG_COMMAND		0x04
+#define PCI_CONFIG_STATUS		0x06
+#define PCI_CONFIG_REVISIONID		0x08
+#define PCI_CONFIG_CLASS_CODE_L		0x09
+#define PCI_CONFIG_CLASS_CODE_M		0x0a
+#define PCI_CONFIG_CLASS_CODE_U		0x0b
+#define PCI_CONFIG_CACHE_LINE_SIZE	0x0c
+#define PCI_CONFIG_LATENCY_TIMER	0x0d
+#define PCI_CONFIG_HEADER_TYPE		0x0e
+#define PCI_CONFIG_BIST			0x0f
+#define PCI_CONFIG_BAR_0		0x10
+#define PCI_CONFIG_BAR_1		0x14
+#define PCI_CONFIG_BAR_2		0x18
+#define PCI_CONFIG_BAR_3		0x1c
+#define PCI_CONFIG_BAR_4		0x20
+#define PCI_CONFIG_BAR_5		0x24
+#define PCI_CONFIG_SUBVENDOR_LOW	0x2c
+#define PCI_CONFIG_SUBVENDOR_HIGH	0x2d
+#define PCI_CONFIG_SUBDEVICE_LOW	0x2e
+#define PCI_CONFIG_SUBDEVICE_HIGH	0x2f
+#define PCI_CONFIG_ROM_BAR		0x30
+#define PCI_CONFIG_INTERRUPTLINE	0x3c
+#define PCI_CONFIG_INTERRUPTPIN		0x3d
+#define PCI_CONFIG_MIN_GNT		0x3e
+#define PCI_CONFIG_MAX_LAT		0x3f
+
+/*
+ * PCI Status register definitions
+ */
+
+#define PCI_STATUS_66MHZ_CAPABLE	0x0020
+#define PCI_STATUS_UDF_SUPPORTED	0x0040
+#define PCI_STATUS_FAST_BACK_TO_BACK	0x0080
+#define PCI_STATUS_DET_DPAR_ERR		0x0100
+#define PCI_STATUS_DEVSEL_MSK		0x0600
+#define PCI_STATUS_DEVSEL_SLOW		0x0400
+#define PCI_STATUS_DEVSEL_MED		0x0200
+#define PCI_STATUS_DEVSEL_FAST		0x0000
+#define PCI_STATUS_SIG_TARG_ABT		0x0800
+#define PCI_STATUS_REC_TARG_ABT		0x1000
+#define PCI_STATUS_REC_MAST_ABT		0x2000
+#define PCI_STATUS_SIG_SYS_ERR		0x4000
+#define PCI_STATUS_DET_PAR_ERR		0x8000
+
+/*
+ * PCI Enable register definitions
+ */
+
+#define PCI_ENABLE_IO_SPACE             0x0001
+#define PCI_ENABLE_MEMORY_SPACE         0x0002
+#define PCI_ENABLE_BUS_MASTER           0x0004
+#define PCI_ENABLE_SPECIAL_CYCLES       0x0008
+#define PCI_ENABLE_WRITE_AND_INVALIDATE 0x0010
+#define PCI_ENABLE_VGA_COMPATIBLE_PALETTE 0x0020
+#define PCI_ENABLE_PARITY               0x0040
+#define PCI_ENABLE_WAIT_CYCLE           0x0080
+#define PCI_ENABLE_SERR                 0x0100
+#define PCI_ENABLE_FAST_BACK_TO_BACK    0x0200
+
+/*
+ * Bit encode for PCI_CONFIG_HEADER_TYPE register
+ */
+
+#define PCI_MULTI_FUNCTION	0x80
+
+/*
+ * Bit encodes for PCI Config BaseAddressesRegisters (BARs)
+ */
+
+#define PCI_ADDRESS_IO_SPACE                0x00000001
+#define PCI_ADDRESS_MEMORY_TYPE_MASK        0x00000007
+#define PCI_ADDRESS_MEMORY_PREFETCHABLE     0x00000008
+
+#define PCI_TYPE_32BIT      0
+#define PCI_TYPE_20BIT      2
+#define PCI_TYPE_64BIT      4
+
+/*
+ * Bit encodes for PCI Config ROMBaseAddresses
+ */
+
+#define PCI_ROMADDRESS_ENABLED              0x00000001
+
+/*
+ * PCI Bridge Configuration space definitions
+ */
+
+#define PCI_BRIDGE_PRIMARY_BUS		0x18
+#define PCI_BRIDGE_SECONDARY_BUS	0x19
+#define PCI_BRIDGE_SUBORDINATE_BUS	0x1a
+#define PCI_BRIDGE_SECONDARY_LAT	0x1b
+#define PCI_BRIDGE_IO_BASE		0x1c
+#define PCI_BRIDGE_IO_LIMIT		0x1d
+#define PCI_BRIDGE_SECONDARY_STATUS	0x1e
+#define PCI_BRIDGE_MEMORY_BASE		0x20
+#define PCI_BRIDGE_MEMORY_LIMIT		0x22
+#define PCI_BRIDGE_PRE_MEMORY_BASE	0x24
+#define PCI_BRIDGE_PRE_MEMORY_LIMIT	0x26
+#define PCI_BRIDGE_PRE_BASE_U		0x28
+#define PCI_BRIDGE_PRE_LIMIT_U		0x2c
+#define PCI_BRIDGE_IO_BASE_U		0x30
+#define PCI_BRIDGE_IO_LIMIT_U		0x32
+#define PCI_BRIDGE_ROM_BAR		0x38
+#define PCI_BRIDGE_CONTROL		0x3e
+
+/*
+ * PCI Bridge Control register definitions
+ */
+
+#define PCI_BRIDGE_PAR_ERR_RESPONSE	0x01
+#define PCI_BRIDGE_S_SERR_L_FWD_EN	0x02
+#define PCI_BRIDGE_ENABLE_ISA		0x04
+#define PCI_BRIDGE_ENABLE_VGA		0x08
+#define PCI_BRIDGE_MASTER_ABORT		0x20
+#define PCI_BRIDGE_SECONDARY_RESET	0x40
+#define PCI_BRIDGE_BACK_TO_BACK_EN	0x80
+
+/*
+ * PCI IO address forwarding capability
+ */
+#define PCI_BRIDGE_IO_CAPABILITY	0x0f
+#define PCI_BRIDGE_IO_16BIT		0x00
+#define PCI_BRIDGE_IO_32BIT		0x01
+
+/*
+ * Class codes
+ */
+#define PCI_BASE_CLASS_NULL			0x00
+#define PCI_BASE_CLASS_STORAGE		0x01
+#define PCI_BASE_CLASS_NETWORK		0x02
+#define PCI_BASE_CLASS_DISPLAY		0x03
+#define PCI_BASE_CLASS_MULTIMEDIA	0x04
+#define PCI_BASE_CLASS_MEMORY		0x05
+#define PCI_BASE_CLASS_BRIDGE		0x06
+#define PCI_BASE_CLASS_COM_CTRL		0x07
+#define PCI_BASE_CLASS_BASEPERIPH	0x08
+#define PCI_BASE_CLASS_INPUTDEV		0x09
+#define PCI_BASE_CLASS_DOCKING		0x0a
+#define PCI_BASE_CLASS_PROC			0x0b
+#define PCI_BASE_CLASS_SERBUSCTRL	0x0c
+#define PCI_BASE_CLASS_UNDEFINED	0xff
+
+#define PCI_SUB_CLASS_NULL_NVGA		0x00
+#define PCI_IF_CLASS_DISPLAY_VGA		0x00
+#define PCI_IF_CLASS_DISPLAY_VGA8514	0x01
+#define PCI_SUB_CLASS_NULL_VGA		0x01
+
+#define PCI_SUB_CLASS_STORAGE_SCSI		0x00
+#define PCI_SUB_CLASS_STORAGE_IDE		0x01
+#define PCI_SUB_CLASS_STORAGE_FLOPPY	0x02
+#define PCI_SUB_CLASS_STORAGE_IPI		0x03
+#define PCI_SUB_CLASS_STORAGE_RAID		0x04
+#define PCI_SUB_CLASS_STORAGE_OTHER		0x80
+
+#define PCI_SUB_CLASS_NETWORK_ETH		0x00
+#define PCI_SUB_CLASS_NETWORK_TOKEN		0x01
+#define PCI_SUB_CLASS_NETWORK_FDDI		0x02
+#define PCI_SUB_CLASS_NETWORK_ATM		0x03
+#define PCI_SUB_CLASS_NETWORK_OTHER		0x80
+
+#define PCI_SUB_CLASS_DISPLAY_VGA		0x00
+#define PCI_SUB_CLASS_DISPLAY_XGA		0x01
+#define PCI_SUB_CLASS_DISPLAY_OTHER		0x80
+
+#define PCI_SUB_CLASS_MULTIMEDIA_VIDEO	0x00
+#define PCI_SUB_CLASS_MULTIMEDIA_AUDIO	0x01
+#define PCI_SUB_CLASS_MULTIMEDIA_OTHER	0x80
+
+#define PCI_SUB_CLASS_MEMORY_RAM		0x00
+#define PCI_SUB_CLASS_MEMORY_FLASH		0x01
+#define PCI_SUB_CLASS_MEMORY_OTHER		0x80
+
+#define PCI_SUB_CLASS_BRIDGE_HOST		0x00
+#define PCI_SUB_CLASS_BRIDGE_ISA		0x01
+#define PCI_SUB_CLASS_BRIDGE_EISA		0x02
+#define PCI_SUB_CLASS_BRIDGE_MC			0x03
+#define PCI_SUB_CLASS_BRIDGE_PCI		0x04
+#define PCI_SUB_CLASS_BRIDGE_PCMCIA		0x05
+#define PCI_SUB_CLASS_BRIDGE_NUBUS		0x06
+#define PCI_SUB_CLASS_BRIDGE_CARDBUS	0x07
+#define PCI_SUB_CLASS_BRIDGE_OTHER		0x80
+
+#define PCI_SUB_CLASS_COM_CTRL_SERIAL	0x00
+#define PCI_IF_CLASS_COM_SER_XT			0x00
+#define PCI_IF_CLASS_COM_SER_16450		0x01
+#define PCI_IF_CLASS_COM_SER_16550		0x02
+#define PCI_SUB_CLASS_COM_CTRL_PARALLEL	0x01
+#define PCI_IF_CLASS_COM_PAR			0x00
+#define PCI_IF_CLASS_COM_PAR_BI			0x01
+#define PCI_IF_CLASS_COM_PAR_ECP		0x02
+#define PCI_SUB_CLASS_COM_CTRL_OTHER	0x80
+
+#define PCI_SUB_CLASS_BASEPERIPH_PIC		0x00
+#define PCI_IF_CLASS_BASEPERIPH_PIC			0x00
+#define PCI_IF_CLASS_BASEPERIPH_PIC_ISA		0x01
+#define PCI_IF_CLASS_BASEPERIPH_PIC_EISA	0x02
+#define PCI_SUB_CLASS_BASEPERIPH_DMA		0x01
+#define PCI_IF_CLASS_BASEPERIPH_DMA			0x00
+#define PCI_IF_CLASS_BASEPERIPH_DMA_ISA		0x01
+#define PCI_IF_CLASS_BASEPERIPH_DMA_EISA	0x02
+#define PCI_SUB_CLASS_BASEPERIPH_TIMER		0x02
+#define PCI_IF_CLASS_BASEPERIPH_TIMER		0x00
+#define PCI_IF_CLASS_BASEPERIPH_TIMER_ISA	0x01
+#define PCI_IF_CLASS_BASEPERIPH_TIMER_EISA	0x02
+#define PCI_SUB_CLASS_BASEPERIPH_RTC		0x03
+#define PCI_IF_CLASS_BASEPERIPH_RTC			0x00
+#define PCI_IF_CLASS_BASEPERIPH_RTC_ISA		0x01
+#define PCI_SUB_CLASS_BASEPERIPH_OTHER		0x80
+
+#define PCI_SUB_CLASS_INPUTDEV_KEYBOARD	0x00
+#define PCI_SUB_CLASS_INPUTDEV_PEN		0x01
+#define PCI_SUB_CLASS_INPUTDEV_MOUSE	0x02
+#define PCI_SUB_CLASS_INPUTDEV_OTHER	0x80
+
+#define PCI_SUB_CLASS_DOCKING_GENERIC	0x00
+#define PCI_SUB_CLASS_DOCKING_OTHER		0x80
+
+#define PCI_SUB_CLASS_PROC_386			0x00
+#define PCI_SUB_CLASS_PROC_486			0x01
+#define PCI_SUB_CLASS_PROC_PENTIUM		0x02
+#define PCI_SUB_CLASS_PROC_ALPHA		0x10
+#define PCI_SUB_CLASS_PROC_POWERPC		0x20
+#define PCI_SUB_CLASS_PROC_COPROC		0x40
+
+#define PCI_SUB_CLASS_SERBUSCTRL_FIREWIRE	0x00
+#define PCI_SUB_CLASS_SERBUSCTRL_ACCESS		0x01
+#define PCI_SUB_CLASS_SERBUSCTRL_SSA		0x02
+#define PCI_SUB_CLASS_SERBUSCTRL_USB		0x03
+#define PCI_SUB_CLASS_SERBUSCTRL_FIBRECHAN	0x04
+
+#define PCI_INVALID_VENDORDEVICEID	0xffffffff
+#define PCI_ID(v, d) ((d << 16) | v)
+
+/*
+ * PCI access functions
+ */
+extern rtems_status_code PCIConfigWrite8(
+    unsigned8 ucBusNumber,
+    unsigned8 ucSlotNumber,
+    unsigned8 ucFunctionNumber,
+    unsigned8 ucOffset,
+    unsigned8 ucValue
+);
+
+extern rtems_status_code PCIConfigWrite16(
+    unsigned8 ucBusNumber,
+    unsigned8 ucSlotNumber,
+    unsigned8 ucFunctionNumber,
+    unsigned8 ucOffset,
+    unsigned16 usValue
+);
+
+extern rtems_status_code PCIConfigWrite32(
+    unsigned8 ucBusNumber,
+    unsigned8 ucSlotNumber,
+    unsigned8 ucFunctionNumber,
+    unsigned8 ucOffset,
+    unsigned32 ulValue
+);
+
+extern rtems_status_code PCIConfigRead8(
+    unsigned8 ucBusNumber,
+    unsigned8 ucSlotNumber,
+    unsigned8 ucFunctionNumber,
+    unsigned8 ucOffset,
+    unsigned8 *pucValue
+);
+
+extern rtems_status_code PCIConfigRead16(
+    unsigned8 ucBusNumber,
+    unsigned8 ucSlotNumber,
+    unsigned8 ucFunctionNumber,
+    unsigned8 ucOffset,
+    unsigned16 *pusValue
+);
+
+extern rtems_status_code PCIConfigRead32(
+    unsigned8 ucBusNumber,
+    unsigned8 ucSlotNumber,
+    unsigned8 ucFunctionNumber,
+    unsigned8 ucOffset,
+    unsigned32 *pulValue
+);
+
+/*
+ * Return the number of PCI busses in the system
+ */
+extern unsigned8 BusCountPCI();
+
+#endif /* _PCI_H_ */
diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/include/tod.h b/c/src/lib/libbsp/powerpc/ppcn_60x/include/tod.h
new file mode 100644
index 0000000000..ef94d35252
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/ppcn_60x/include/tod.h
@@ -0,0 +1,38 @@
+/*
+ * Real Time Clock (MK48T08) for RTEMS on PPCn_60x
+ *
+ *  Based on MVME162 TOD by:
+ *    COPYRIGHT (C) 1997
+ *    by Katsutoshi Shibuya - BU Denken Co.,Ltd. - Sapporo - JAPAN
+ *    ALL RIGHTS RESERVED
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+
+#ifndef TOD_H
+#define TOD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern void setRealTimeToRTEMS();
+/* Read real time from RTC and set it to RTEMS' clock manager */
+
+extern void setRealTimeFromRTEMS();
+/* Read time from RTEMS' clock manager and set it to RTC */
+
+extern int checkRealTime();
+/* Return the difference between RTC and RTEMS' clock manager time in minutes.
+   If the difference is greater than 1 day, this returns 9999. */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif