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| author | Ralf Corsepius <ralf.corsepius@rtems.org> | 2009-11-30 04:37:44 +0000 |
|---|---|---|
| committer | Ralf Corsepius <ralf.corsepius@rtems.org> | 2009-11-30 04:37:44 +0000 |
| commit | ac7af4a359cc51bc06e1bf0ed3314744972b8395 (patch) | |
| tree | 7c73805f8b66af9b3082fbde80f6eb70edd966ac /c/src/lib/libbsp/powerpc/mpc8260ads | |
| parent | 2009-11-30 Ralf Corsépius <ralf.corsepius@rtems.org> (diff) | |
| download | rtems-ac7af4a359cc51bc06e1bf0ed3314744972b8395.tar.bz2 | |
Whitespace removal.
Diffstat (limited to 'c/src/lib/libbsp/powerpc/mpc8260ads')
| -rw-r--r-- | c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c b/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c index 8994896696..ebfb5cc32c 100644 --- a/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c +++ b/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c @@ -192,18 +192,18 @@ int BSP_irq_disable_at_cpm(const rtems_irq_number irqLine) return 0; } - -int BSP_irq_enabled_at_cpm(const rtems_irq_number irqLine) -{ - int cpm_irq_index; - - if (!is_cpm_irq(irqLine)) - return 0; - - cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET); - - return ((m8260.simr_h & SIU_MaskBit[cpm_irq_index].mask_h) || - (m8260.simr_l & SIU_MaskBit[cpm_irq_index].mask_l)); + +int BSP_irq_enabled_at_cpm(const rtems_irq_number irqLine) +{ + int cpm_irq_index; + + if (!is_cpm_irq(irqLine)) + return 0; + + cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET); + + return ((m8260.simr_h & SIU_MaskBit[cpm_irq_index].mask_h) || + (m8260.simr_l & SIU_MaskBit[cpm_irq_index].mask_l)); } #ifdef DISPATCH_HANDLER_STAT @@ -274,8 +274,8 @@ int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned excNum) m8260.sipnr_h |= SIU_MaskBit[irq].mask_h; m8260.sipnr_l |= SIU_MaskBit[irq].mask_l; - /* - * make sure, that the masking operations in + /* + * make sure, that the masking operations in * ICTL and MSR are executed in order */ asm volatile("sync":::"memory"); @@ -291,8 +291,8 @@ int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned excNum) /* disable exceptions again */ _CPU_MSR_SET(msr); - /* - * make sure, that the masking operations in + /* + * make sure, that the masking operations in * ICTL and MSR are executed in order */ asm volatile("sync":::"memory"); |