2001-03-30 Eric Valette <valette@crf.canon.fr>

	* clock/.cvsignore, clock/Makefile.am, clock/p_clock.c,
	include/8xx_immap.h, include/commproc.h, include/mbx.h,
	irq/.cvsignore, irq/Makefile.am, irq/irq.c, irq/irq.h,
	irq/irq_asm.S, irq/irq_init.c, vectors/.cvsignore,
	vectors/Makefile.am, vectors/vectors.S, vectors/vectors.h,
	vectors/vectors_init.c: New files.
	* Makefile.am, configure.in, console/console.c,
	include/Makefile.am, network/network.c, startup/Makefile.am,
	startup/bspstart.c, startup/imbx8xx.c, startup/linkcmds,
	startup/mmutlbtab.c, startup/start.S, wrapup/Makefile.am:
	The modifications to this BSP reflect the conversion of the
	mpc8xx CPU to the "new exception processing model."

4 files changed, 1064 insertions, 2 deletions

diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/include/8xx_immap.h b/c/src/lib/libbsp/powerpc/mbx8xx/include/8xx_immap.h
new file mode 100644
index 0000000000..3e9f981b31
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/mbx8xx/include/8xx_immap.h
@@ -0,0 +1,455 @@
+
+/*
+ * MPC8xx Internal Memory Map
+ * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
+ *
+ * The I/O on the MPC860 is comprised of blocks of special registers
+ * and the dual port ram for the Communication Processor Module.
+ * Within this space are functional units such as the SIU, memory
+ * controller, system timers, and other control functions.  It is
+ * a combination that I found difficult to separate into logical
+ * functional files.....but anyone else is welcome to try.  -- Dan
+ */
+#ifndef __IMMAP_8XX__
+#define __IMMAP_8XX__
+
+/* System configuration registers.
+*/
+typedef	struct sys_conf {
+	unsigned int	sc_siumcr;
+	unsigned int	sc_sypcr;
+	unsigned int	sc_swt;
+	char		res1[2];
+	unsigned short	sc_swsr;
+	unsigned int	sc_sipend;
+	unsigned int	sc_simask;
+	unsigned int	sc_siel;
+	unsigned int	sc_sivec;
+	unsigned int	sc_tesr;
+	char		res2[0xc];
+	unsigned int	sc_sdcr;
+	char		res3[0x4c];
+} sysconf8xx_t;
+
+/* PCMCIA configuration registers.
+*/
+typedef struct pcmcia_conf {
+	unsigned int	pcmc_pbr0;
+	unsigned int	pcmc_por0;
+	unsigned int	pcmc_pbr1;
+	unsigned int	pcmc_por1;
+	unsigned int	pcmc_pbr2;
+	unsigned int	pcmc_por2;
+	unsigned int	pcmc_pbr3;
+	unsigned int	pcmc_por3;
+	unsigned int	pcmc_pbr4;
+	unsigned int	pcmc_por4;
+	unsigned int	pcmc_pbr5;
+	unsigned int	pcmc_por5;
+	unsigned int	pcmc_pbr6;
+	unsigned int	pcmc_por6;
+	unsigned int	pcmc_pbr7;
+	unsigned int	pcmc_por7;
+	char		res1[0x20];
+	unsigned int	pcmc_pgcra;
+	unsigned int	pcmc_pgcrb;
+	unsigned int	pcmc_pscr;
+	char		res2[4];
+	unsigned int	pcmc_pipr;
+	char		res3[4];
+	unsigned int	pcmc_per;
+	char		res4[4];
+} pcmconf8xx_t;
+
+/* Memory controller registers.
+*/
+typedef struct	mem_ctlr {
+	unsigned int	memc_br0;
+	unsigned int	memc_or0;
+	unsigned int	memc_br1;
+	unsigned int	memc_or1;
+	unsigned int	memc_br2;
+	unsigned int	memc_or2;
+	unsigned int	memc_br3;
+	unsigned int	memc_or3;
+	unsigned int	memc_br4;
+	unsigned int	memc_or4;
+	unsigned int	memc_br5;
+	unsigned int	memc_or5;
+	unsigned int	memc_br6;
+	unsigned int	memc_or6;
+	unsigned int	memc_br7;
+	unsigned int	memc_or7;
+	char		res1[0x24];
+	unsigned int	memc_mar;
+	unsigned int	memc_mcr;
+	char		res2[4];
+	unsigned int	memc_mamr;
+	unsigned int	memc_mbmr;
+	unsigned short	memc_mstat;
+	unsigned short	memc_mptpr;
+	unsigned int	memc_mdr;
+	char		res3[0x80];
+} memctl8xx_t;
+
+/* System Integration Timers.
+*/
+typedef struct	sys_int_timers {
+	unsigned short	sit_tbscr;
+	unsigned int	sit_tbreff0;
+	unsigned int	sit_tbreff1;
+	char		res1[0x14];
+	unsigned short	sit_rtcsc;
+	unsigned int	sit_rtc;
+	unsigned int	sit_rtsec;
+	unsigned int	sit_rtcal;
+	char		res2[0x10];
+	unsigned short	sit_piscr;
+	char		res3[2];
+	unsigned int	sit_pitc;
+	unsigned int	sit_pitr;
+	char		res4[0x34];
+} sit8xx_t;
+
+#define TBSCR_TBIRQ_MASK	((unsigned short)0xff00)
+#define TBSCR_REFA		((unsigned short)0x0080)
+#define TBSCR_REFB		((unsigned short)0x0040)
+#define TBSCR_REFAE		((unsigned short)0x0008)
+#define TBSCR_REFBE		((unsigned short)0x0004)
+#define TBSCR_TBF		((unsigned short)0x0002)
+#define TBSCR_TBE		((unsigned short)0x0001)
+
+#define RTCSC_RTCIRQ_MASK	((unsigned short)0xff00)
+#define RTCSC_SEC		((unsigned short)0x0080)
+#define RTCSC_ALR		((unsigned short)0x0040)
+#define RTCSC_38K		((unsigned short)0x0010)
+#define RTCSC_SIE		((unsigned short)0x0008)
+#define RTCSC_ALE		((unsigned short)0x0004)
+#define RTCSC_RTF		((unsigned short)0x0002)
+#define RTCSC_RTE		((unsigned short)0x0001)
+
+#define PISCR_PIRQ_MASK		((unsigned short)0xff00)
+#define PISCR_PS		((unsigned short)0x0080)
+#define PISCR_PIE		((unsigned short)0x0004)
+#define PISCR_PTF		((unsigned short)0x0002)
+#define PISCR_PTE		((unsigned short)0x0001)
+
+/* Clocks and Reset.
+*/
+typedef struct clk_and_reset {
+	unsigned int	car_sccr;
+	unsigned int	car_plprcr;
+	unsigned int	car_rsr;
+	char		res[0x74];        /* Reserved area                  */
+} car8xx_t;
+
+/* System Integration Timers keys.
+*/
+typedef struct sitk {
+	unsigned int	sitk_tbscrk;
+	unsigned int	sitk_tbreff0k;
+	unsigned int	sitk_tbreff1k;
+	unsigned int	sitk_tbk;
+	char		res1[0x10];
+	unsigned int	sitk_rtcsck;
+	unsigned int	sitk_rtck;
+	unsigned int	sitk_rtseck;
+	unsigned int	sitk_rtcalk;
+	char		res2[0x10];
+	unsigned int	sitk_piscrk;
+	unsigned int	sitk_pitck;
+	char		res3[0x38];
+} sitk8xx_t;
+
+/* Clocks and reset keys.
+*/
+typedef struct cark {
+	unsigned int	cark_sccrk;
+	unsigned int	cark_plprcrk;
+	unsigned int	cark_rsrk;
+	char		res[0x474];
+} cark8xx_t;
+
+/* The key to unlock registers maintained by keep-alive power.
+*/
+#define KAPWR_KEY	((unsigned int)0x55ccaa33)
+
+/* LCD interface.  MPC821 Only.
+*/
+typedef struct lcd {
+	unsigned short	lcd_lcolr[16];
+	char		res[0x20];
+	unsigned int	lcd_lccr;
+	unsigned int	lcd_lchcr;
+	unsigned int	lcd_lcvcr;
+	char		res2[4];
+	unsigned int	lcd_lcfaa;
+	unsigned int	lcd_lcfba;
+	char		lcd_lcsr;
+	char		res3[0x7];
+} lcd8xx_t;
+
+/* I2C
+*/
+typedef struct i2c {
+	unsigned char	i2c_i2mod;
+	char		res1[3];
+	unsigned char	i2c_i2add;
+	char		res2[3];
+	unsigned char	i2c_i2brg;
+	char		res3[3];
+	unsigned char	i2c_i2com;
+	char		res4[3];
+	unsigned char	i2c_i2cer;
+	char		res5[3];
+	unsigned char	i2c_i2cmr;
+	char		res6[0x8b];
+} i2c8xx_t;
+
+/* DMA control/status registers.
+*/
+typedef struct sdma_csr {
+	char		res1[4];
+	unsigned int	sdma_sdar;
+	unsigned char	sdma_sdsr;
+	char		res3[3];
+	unsigned char	sdma_sdmr;
+	char		res4[3];
+	unsigned char	sdma_idsr1;
+	char		res5[3];
+	unsigned char	sdma_idmr1;
+	char		res6[3];
+	unsigned char	sdma_idsr2;
+	char		res7[3];
+	unsigned char	sdma_idmr2;
+	char		res8[0x13];
+} sdma8xx_t;
+
+/* Communication Processor Module Interrupt Controller.
+*/
+typedef struct cpm_ic {
+	unsigned short	cpic_civr;
+	char		res[0xe];
+	unsigned int	cpic_cicr;
+	unsigned int	cpic_cipr;
+	unsigned int	cpic_cimr;
+	unsigned int	cpic_cisr;
+} cpic8xx_t;
+
+/* Input/Output Port control/status registers.
+*/
+typedef struct io_port {
+	unsigned short	iop_padir;
+	unsigned short	iop_papar;
+	unsigned short	iop_paodr;
+	unsigned short	iop_padat;
+	char		res1[8];
+	unsigned short	iop_pcdir;
+	unsigned short	iop_pcpar;
+	unsigned short	iop_pcso;
+	unsigned short	iop_pcdat;
+	unsigned short	iop_pcint;
+	char		res2[6];
+	unsigned short	iop_pddir;
+	unsigned short	iop_pdpar;
+	char		res3[2];
+	unsigned short	iop_pddat;
+	char		res4[8];
+} iop8xx_t;
+
+/* Communication Processor Module Timers
+*/
+typedef struct cpm_timers {
+	unsigned short	cpmt_tgcr;
+	char		res1[0xe];
+	unsigned short	cpmt_tmr1;
+	unsigned short	cpmt_tmr2;
+	unsigned short	cpmt_trr1;
+	unsigned short	cpmt_trr2;
+	unsigned short	cpmt_tcr1;
+	unsigned short	cpmt_tcr2;
+	unsigned short	cpmt_tcn1;
+	unsigned short	cpmt_tcn2;
+	unsigned short	cpmt_tmr3;
+	unsigned short	cpmt_tmr4;
+	unsigned short	cpmt_trr3;
+	unsigned short	cpmt_trr4;
+	unsigned short	cpmt_tcr3;
+	unsigned short	cpmt_tcr4;
+	unsigned short	cpmt_tcn3;
+	unsigned short	cpmt_tcn4;
+	unsigned short	cpmt_ter1;
+	unsigned short	cpmt_ter2;
+	unsigned short	cpmt_ter3;
+	unsigned short	cpmt_ter4;
+	char		res2[8];
+} cpmtimer8xx_t;
+
+/* Finally, the Communication Processor stuff.....
+*/
+typedef struct scc {		/* Serial communication channels */
+	unsigned int	scc_gsmrl;
+	unsigned int	scc_gsmrh;
+	unsigned short	scc_pmsr;
+	char		res1[2];
+	unsigned short	scc_todr;
+	unsigned short	scc_dsr;
+	unsigned short	scc_scce;
+	char		res2[2];
+	unsigned short	scc_sccm;
+	char		res3;
+	unsigned char	scc_sccs;
+	char		res4[8];
+} scc_t;
+
+typedef struct smc {		/* Serial management channels */
+	char		res1[2];
+	unsigned short	smc_smcmr;
+	char		res2[2];
+	unsigned char	smc_smce;
+	char		res3[3];
+	unsigned char	smc_smcm;
+	char		res4[5];
+} smc_t;
+
+/* MPC860T Fast Ethernet Controller.  It isn't part of the CPM, but
+ * it fits within the address space.
+ */
+typedef struct fec {
+	unsigned int	fec_addr_low;		/* LS 32 bits of station address */
+	unsigned short	fec_addr_high;		/* MS 16 bits of address */
+	unsigned short	res1;
+	unsigned int	fec_hash_table_high;
+	unsigned int	fec_hash_table_low;
+	unsigned int	fec_r_des_start;
+	unsigned int	fec_x_des_start;
+	unsigned int	fec_r_buff_size;
+	unsigned int	res2[9];
+	unsigned int	fec_ecntrl;
+	unsigned int	fec_ievent;
+	unsigned int	fec_imask;
+	unsigned int	fec_ivec;
+	unsigned int	fec_r_des_active;
+	unsigned int	fec_x_des_active;
+	unsigned int	res3[10];
+	unsigned int	fec_mii_data;
+	unsigned int	fec_mii_speed;
+	unsigned int	res4[17];
+	unsigned int	fec_r_bound;
+	unsigned int	fec_r_fstart;
+	unsigned int	res5[6];
+	unsigned int	fec_x_fstart;
+	unsigned int	res6[17];
+	unsigned int	fec_fun_code;
+	unsigned int	res7[3];
+	unsigned int	fec_r_cntrl;
+	unsigned int	fec_r_hash;
+	unsigned int	res8[14];
+	unsigned int	fec_x_cntrl;
+	unsigned int	res9[0x1e];
+} fec_t;
+
+typedef struct comm_proc {
+	/* General control and status registers.
+	*/
+	unsigned short	cp_cpcr;
+	char		res1[2];
+	unsigned short	cp_rccr;
+	char		res2[6];
+	unsigned short	cp_cpmcr1;
+	unsigned short	cp_cpmcr2;
+	unsigned short	cp_cpmcr3;
+	unsigned short	cp_cpmcr4;
+	char		res3[2];
+	unsigned short	cp_rter;
+	char		res4[2];
+	unsigned short	cp_rtmr;
+	char		res5[0x14];
+
+	/* Baud rate generators.
+	*/
+	unsigned int	cp_brgc1;
+	unsigned int	cp_brgc2;
+	unsigned int	cp_brgc3;
+	unsigned int	cp_brgc4;
+
+	/* Serial Communication Channels.
+	*/
+	scc_t	cp_scc[4];
+
+	/* Serial Management Channels.
+	*/
+	smc_t	cp_smc[2];
+
+	/* Serial Peripheral Interface.
+	*/
+	unsigned short	cp_spmode;
+	char		res6[4];
+	unsigned char	cp_spie;
+	char		res7[3];
+	unsigned char	cp_spim;
+	char		res8[2];
+	unsigned char	cp_spcom;
+	char		res9[2];
+
+	/* Parallel Interface Port.
+	*/
+	char		res10[2];
+	unsigned short	cp_pipc;
+	char		res11[2];
+	unsigned short	cp_ptpr;
+	unsigned int	cp_pbdir;
+	unsigned int	cp_pbpar;
+	char		res12[2];
+	unsigned short	cp_pbodr;
+	unsigned int	cp_pbdat;
+	char		res13[0x18];
+
+	/* Serial Interface and Time Slot Assignment.
+	*/
+	unsigned int	cp_simode;
+	unsigned char	cp_sigmr;
+	char		res14;
+	unsigned char	cp_sistr;
+	unsigned char	cp_sicmr;
+	char		res15[4];
+	unsigned int	cp_sicr;
+	unsigned int	cp_sirp;
+	char		res16[0x10c];
+	unsigned char	cp_siram[0x200];
+
+	/* The fast ethernet controller is not really part of the CPM,
+	 * but it resides in the address space.
+	 */
+	fec_t		cp_fec;
+	char		res18[0x1000];
+
+	/* Dual Ported RAM follows.
+	 * There are many different formats for this memory area
+	 * depending upon the devices used and options chosen.
+	 */
+	unsigned char	cp_dpmem[0x1000];	/* BD / Data / ucode */
+	unsigned char	res19[0xc00];
+	unsigned char	cp_dparam[0x400];	/* Parameter RAM */
+} cpm8xx_t;
+
+/* Internal memory map.
+*/
+typedef struct immap {
+	sysconf8xx_t	im_siu_conf;	/* SIU Configuration */
+	pcmconf8xx_t	im_pcmcia;	/* PCMCIA Configuration */
+	memctl8xx_t	im_memctl;	/* Memory Controller */
+	sit8xx_t	im_sit;		/* System integration timers */
+	car8xx_t	im_clkrst;	/* Clocks and reset */
+	sitk8xx_t	im_sitk;	/* Sys int timer keys */
+	cark8xx_t	im_clkrstk;	/* Clocks and reset keys */
+	lcd8xx_t	im_lcd;		/* LCD (821 only) */
+	i2c8xx_t	im_i2c;		/* I2C control/status */
+	sdma8xx_t	im_sdma;	/* SDMA control/status */
+	cpic8xx_t	im_cpic;	/* CPM Interrupt Controller */
+	iop8xx_t	im_ioport;	/* IO Port control/status */
+	cpmtimer8xx_t	im_cpmtimer;	/* CPM timers */
+	cpm8xx_t	im_cpm;		/* Communication processor */
+} immap_t;
+
+#endif /* __IMMAP_8XX__ */
diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/include/Makefile.am b/c/src/lib/libbsp/powerpc/mbx8xx/include/Makefile.am
index 6c4e41dd5d..6728c6032c 100644
--- a/c/src/lib/libbsp/powerpc/mbx8xx/include/Makefile.am
+++ b/c/src/lib/libbsp/powerpc/mbx8xx/include/Makefile.am
@@ -6,17 +6,33 @@ AUTOMAKE_OPTIONS = foreign 1.4
 
 H_FILES = bsp.h coverhd.h
 
+BSP_H_FILES = mbx.h commproc.h 8xx_immap.h
+
 $(PROJECT_INCLUDE):
 	$(mkinstalldirs) $@
 
+$(PROJECT_INCLUDE)/bsp: 
+	$(mkinstalldirs) $@
+
 $(PROJECT_INCLUDE)/bsp.h: bsp.h
 	$(INSTALL_DATA) $< $@
 
 $(PROJECT_INCLUDE)/coverhd.h: coverhd.h
 	$(INSTALL_DATA) $< $@
 
-PREINSTALL_FILES += $(PROJECT_INCLUDE) $(PROJECT_INCLUDE)/bsp.h \
-    $(PROJECT_INCLUDE)/coverhd.h
+$(PROJECT_INCLUDE)/bsp/mbx.h : mbx.h
+	$(INSTALL_DATA) $< $@
+
+$(PROJECT_INCLUDE)/bsp/commproc.h : commproc.h
+	$(INSTALL_DATA) $< $@
+
+$(PROJECT_INCLUDE)/bsp/8xx_immap.h : 8xx_immap.h
+	$(INSTALL_DATA) $< $@
+
+PREINSTALL_FILES += $(PROJECT_INCLUDE) $(PROJECT_INCLUDE)/bsp \
+	$(PROJECT_INCLUDE)/bsp.h \
+	$(PROJECT_INCLUDE)/coverhd.h $(PROJECT_INCLUDE)/bsp/mbx.h \
+	$(PROJECT_INCLUDE)/bsp/commproc.h $(PROJECT_INCLUDE)/bsp/8xx_immap.h
 
 all-local: $(PREINSTALL_FILES)
 
diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/include/commproc.h b/c/src/lib/libbsp/powerpc/mbx8xx/include/commproc.h
new file mode 100644
index 0000000000..e157203467
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/mbx8xx/include/commproc.h
@@ -0,0 +1,529 @@
+
+/*
+ * MPC8xx Communication Processor Module.
+ * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
+ *
+ * This file contains structures and information for the communication
+ * processor channels.  Some CPM control and status is available
+ * throught the MPC8xx internal memory map.  See immap.h for details.
+ * This file only contains what I need for the moment, not the total
+ * CPM capabilities.  I (or someone else) will add definitions as they
+ * are needed.  -- Dan
+ *
+ * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
+ * bytes of the DP RAM and relocates the I2C parameter area to the
+ * IDMA1 space.  The remaining DP RAM is available for buffer descriptors
+ * or other use.
+ */
+#ifndef __CPM_8XX__
+#define __CPM_8XX__
+
+#include <bsp/8xx_immap.h>
+
+/* CPM Command register.
+*/
+#define CPM_CR_RST	((ushort)0x8000)
+#define CPM_CR_OPCODE	((ushort)0x0f00)
+#define CPM_CR_CHAN	((ushort)0x00f0)
+#define CPM_CR_FLG	((ushort)0x0001)
+
+/* Some commands (there are more...later)
+*/
+#define CPM_CR_INIT_TRX		((ushort)0x0000)
+#define CPM_CR_INIT_RX		((ushort)0x0001)
+#define CPM_CR_INIT_TX		((ushort)0x0002)
+#define CPM_CR_STOP_TX		((ushort)0x0004)
+#define CPM_CR_RESTART_TX	((ushort)0x0006)
+#define CPM_CR_SET_GADDR	((ushort)0x0008)
+
+/* Channel numbers.
+*/
+#define CPM_CR_CH_SCC1	((ushort)0x0000)
+#define CPM_CR_CH_I2C	((ushort)0x0001)	/* I2C and IDMA1 */
+#define CPM_CR_CH_SCC2	((ushort)0x0004)
+#define CPM_CR_CH_SPI	((ushort)0x0005)	/* SPI / IDMA2 / Timers */
+#define CPM_CR_CH_SCC3	((ushort)0x0008)
+#define CPM_CR_CH_SMC1	((ushort)0x0009)	/* SMC1 / DSP1 */
+#define CPM_CR_CH_SCC4	((ushort)0x000c)
+#define CPM_CR_CH_SMC2	((ushort)0x000d)	/* SMC2 / DSP2 */
+
+#define mk_cr_cmd(CH, CMD)	((CMD << 8) | (CH << 4))
+
+/* The dual ported RAM is multi-functional.  Some areas can be (and are
+ * being) used for microcode.  There is an area that can only be used
+ * as data ram for buffer descriptors, which is all we use right now.
+ * Currently the first 512 and last 256 bytes are used for microcode.
+ */
+#define CPM_DATAONLY_BASE	((uint)0x0800)
+#define CPM_DATAONLY_SIZE	((uint)0x0700)
+#define CPM_DP_NOSPACE		((uint)0x7fffffff)
+
+/* Export the base address of the communication processor registers
+ * and dual port ram.
+ */
+extern	cpm8xx_t	*cpmp;		/* Pointer to comm processor */
+uint		m8xx_cpm_dpalloc(uint size);
+uint		m8xx_cpm_hostalloc(uint size);
+void		m8xx_cpm_setbrg(uint brg, uint rate);
+
+/* Buffer descriptors used by many of the CPM protocols.
+*/
+typedef struct cpm_buf_desc {
+	ushort	cbd_sc;		/* Status and Control */
+	ushort	cbd_datlen;	/* Data length in buffer */
+	uint	cbd_bufaddr;	/* Buffer address in host memory */
+} cbd_t;
+
+#define BD_SC_EMPTY	((ushort)0x8000)	/* Recieve is empty */
+#define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
+#define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
+#define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
+#define BD_SC_CM	((ushort)0x0200)	/* Continous mode */
+#define BD_SC_ID	((ushort)0x0100)	/* Rec'd too many idles */
+#define BD_SC_P		((ushort)0x0100)	/* xmt preamble */
+#define BD_SC_BR	((ushort)0x0020)	/* Break received */
+#define BD_SC_FR	((ushort)0x0010)	/* Framing error */
+#define BD_SC_PR	((ushort)0x0008)	/* Parity error */
+#define BD_SC_OV	((ushort)0x0002)	/* Overrun */
+#define BD_SC_CD	((ushort)0x0001)	/* ?? */
+
+/* Parameter RAM offsets.
+*/
+#define PROFF_SCC1	((uint)0x0000)
+#define PROFF_SCC2	((uint)0x0100)
+#define PROFF_SCC3	((uint)0x0200)
+#define PROFF_SMC1	((uint)0x0280)
+#define PROFF_SCC4	((uint)0x0300)
+#define PROFF_SMC2	((uint)0x0380)
+
+/* Define enough so I can at least use the serial port as a UART.
+ */
+typedef struct smc_uart {
+	ushort	smc_rbase;	/* Rx Buffer descriptor base address */
+	ushort	smc_tbase;	/* Tx Buffer descriptor base address */
+	u_char	smc_rfcr;	/* Rx function code */
+	u_char	smc_tfcr;	/* Tx function code */
+	ushort	smc_mrblr;	/* Max receive buffer length */
+	uint	smc_rstate;	/* Internal */
+	uint	smc_idp;	/* Internal */
+	ushort	smc_rbptr;	/* Internal */
+	ushort	smc_ibc;	/* Internal */
+	uint	smc_rxtmp;	/* Internal */
+	uint	smc_tstate;	/* Internal */
+	uint	smc_tdp;	/* Internal */
+	ushort	smc_tbptr;	/* Internal */
+	ushort	smc_tbc;	/* Internal */
+	uint	smc_txtmp;	/* Internal */
+	ushort	smc_maxidl;	/* Maximum idle characters */
+	ushort	smc_tmpidl;	/* Temporary idle counter */
+	ushort	smc_brklen;	/* Last received break length */
+	ushort	smc_brkec;	/* rcv'd break condition counter */
+	ushort	smc_brkcr;	/* xmt break count register */
+	ushort	smc_rmask;	/* Temporary bit mask */
+} smc_uart_t;
+
+/* Function code bits.
+*/
+#define SMC_EB	((u_char)0x10)	/* Set big endian byte order */
+
+/* SMC uart mode register.
+*/
+#define	SMCMR_REN	((ushort)0x0001)
+#define SMCMR_TEN	((ushort)0x0002)
+#define SMCMR_DM	((ushort)0x000c)
+#define SMCMR_SM_GCI	((ushort)0x0000)
+#define SMCMR_SM_UART	((ushort)0x0020)
+#define SMCMR_SM_TRANS	((ushort)0x0030)
+#define SMCMR_SM_MASK	((ushort)0x0030)
+#define SMCMR_PM_EVEN	((ushort)0x0100)	/* Even parity, else odd */
+#define SMCMR_PEN	((ushort)0x0200)	/* Parity enable */
+#define SMCMR_SL	((ushort)0x0400)	/* Two stops, else one */
+#define SMCR_CLEN_MASK	((ushort)0x7800)	/* Character length */
+#define smcr_mk_clen(C)	(((C) << 11) & SMCR_CLEN_MASK)
+
+/* SMC Event and Mask register.
+*/
+#define	SMCM_TXE	((unsigned char)0x10)
+#define	SMCM_BSY	((unsigned char)0x04)
+#define	SMCM_TX		((unsigned char)0x02)
+#define	SMCM_RX		((unsigned char)0x01)
+
+/* Baud rate generators.
+*/
+#define CPM_BRG_RST		((uint)0x00020000)
+#define CPM_BRG_EN		((uint)0x00010000)
+#define CPM_BRG_EXTC_INT	((uint)0x00000000)
+#define CPM_BRG_EXTC_CLK2	((uint)0x00004000)
+#define CPM_BRG_EXTC_CLK6	((uint)0x00008000)
+#define CPM_BRG_ATB		((uint)0x00002000)
+#define CPM_BRG_CD_MASK		((uint)0x00001ffe)
+#define CPM_BRG_DIV16		((uint)0x00000001)
+
+/* SCCs.
+*/
+#define SCC_GSMRH_IRP		((uint)0x00040000)
+#define SCC_GSMRH_GDE		((uint)0x00010000)
+#define SCC_GSMRH_TCRC_CCITT	((uint)0x00008000)
+#define SCC_GSMRH_TCRC_BISYNC	((uint)0x00004000)
+#define SCC_GSMRH_TCRC_HDLC	((uint)0x00000000)
+#define SCC_GSMRH_REVD		((uint)0x00002000)
+#define SCC_GSMRH_TRX		((uint)0x00001000)
+#define SCC_GSMRH_TTX		((uint)0x00000800)
+#define SCC_GSMRH_CDP		((uint)0x00000400)
+#define SCC_GSMRH_CTSP		((uint)0x00000200)
+#define SCC_GSMRH_CDS		((uint)0x00000100)
+#define SCC_GSMRH_CTSS		((uint)0x00000080)
+#define SCC_GSMRH_TFL		((uint)0x00000040)
+#define SCC_GSMRH_RFW		((uint)0x00000020)
+#define SCC_GSMRH_TXSY		((uint)0x00000010)
+#define SCC_GSMRH_SYNL16	((uint)0x0000000c)
+#define SCC_GSMRH_SYNL8		((uint)0x00000008)
+#define SCC_GSMRH_SYNL4		((uint)0x00000004)
+#define SCC_GSMRH_RTSM		((uint)0x00000002)
+#define SCC_GSMRH_RSYN		((uint)0x00000001)
+
+#define SCC_GSMRL_SIR		((uint)0x80000000)	/* SCC2 only */
+#define SCC_GSMRL_EDGE_NONE	((uint)0x60000000)
+#define SCC_GSMRL_EDGE_NEG	((uint)0x40000000)
+#define SCC_GSMRL_EDGE_POS	((uint)0x20000000)
+#define SCC_GSMRL_EDGE_BOTH	((uint)0x00000000)
+#define SCC_GSMRL_TCI		((uint)0x10000000)
+#define SCC_GSMRL_TSNC_3	((uint)0x0c000000)
+#define SCC_GSMRL_TSNC_4	((uint)0x08000000)
+#define SCC_GSMRL_TSNC_14	((uint)0x04000000)
+#define SCC_GSMRL_TSNC_INF	((uint)0x00000000)
+#define SCC_GSMRL_RINV		((uint)0x02000000)
+#define SCC_GSMRL_TINV		((uint)0x01000000)
+#define SCC_GSMRL_TPL_128	((uint)0x00c00000)
+#define SCC_GSMRL_TPL_64	((uint)0x00a00000)
+#define SCC_GSMRL_TPL_48	((uint)0x00800000)
+#define SCC_GSMRL_TPL_32	((uint)0x00600000)
+#define SCC_GSMRL_TPL_16	((uint)0x00400000)
+#define SCC_GSMRL_TPL_8		((uint)0x00200000)
+#define SCC_GSMRL_TPL_NONE	((uint)0x00000000)
+#define SCC_GSMRL_TPP_ALL1	((uint)0x00180000)
+#define SCC_GSMRL_TPP_01	((uint)0x00100000)
+#define SCC_GSMRL_TPP_10	((uint)0x00080000)
+#define SCC_GSMRL_TPP_ZEROS	((uint)0x00000000)
+#define SCC_GSMRL_TEND		((uint)0x00040000)
+#define SCC_GSMRL_TDCR_32	((uint)0x00030000)
+#define SCC_GSMRL_TDCR_16	((uint)0x00020000)
+#define SCC_GSMRL_TDCR_8	((uint)0x00010000)
+#define SCC_GSMRL_TDCR_1	((uint)0x00000000)
+#define SCC_GSMRL_RDCR_32	((uint)0x0000c000)
+#define SCC_GSMRL_RDCR_16	((uint)0x00008000)
+#define SCC_GSMRL_RDCR_8	((uint)0x00004000)
+#define SCC_GSMRL_RDCR_1	((uint)0x00000000)
+#define SCC_GSMRL_RENC_DFMAN	((uint)0x00003000)
+#define SCC_GSMRL_RENC_MANCH	((uint)0x00002000)
+#define SCC_GSMRL_RENC_FM0	((uint)0x00001000)
+#define SCC_GSMRL_RENC_NRZI	((uint)0x00000800)
+#define SCC_GSMRL_RENC_NRZ	((uint)0x00000000)
+#define SCC_GSMRL_TENC_DFMAN	((uint)0x00000600)
+#define SCC_GSMRL_TENC_MANCH	((uint)0x00000400)
+#define SCC_GSMRL_TENC_FM0	((uint)0x00000200)
+#define SCC_GSMRL_TENC_NRZI	((uint)0x00000100)
+#define SCC_GSMRL_TENC_NRZ	((uint)0x00000000)
+#define SCC_GSMRL_DIAG_LE	((uint)0x000000c0)	/* Loop and echo */
+#define SCC_GSMRL_DIAG_ECHO	((uint)0x00000080)
+#define SCC_GSMRL_DIAG_LOOP	((uint)0x00000040)
+#define SCC_GSMRL_DIAG_NORM	((uint)0x00000000)
+#define SCC_GSMRL_ENR		((uint)0x00000020)
+#define SCC_GSMRL_ENT		((uint)0x00000010)
+#define SCC_GSMRL_MODE_ENET	((uint)0x0000000c)
+#define SCC_GSMRL_MODE_DDCMP	((uint)0x00000009)
+#define SCC_GSMRL_MODE_BISYNC	((uint)0x00000008)
+#define SCC_GSMRL_MODE_V14	((uint)0x00000007)
+#define SCC_GSMRL_MODE_AHDLC	((uint)0x00000006)
+#define SCC_GSMRL_MODE_PROFIBUS	((uint)0x00000005)
+#define SCC_GSMRL_MODE_UART	((uint)0x00000004)
+#define SCC_GSMRL_MODE_SS7	((uint)0x00000003)
+#define SCC_GSMRL_MODE_ATALK	((uint)0x00000002)
+#define SCC_GSMRL_MODE_HDLC	((uint)0x00000000)
+
+#define SCC_TODR_TOD		((ushort)0x8000)
+
+/* SCC Event and Mask register.
+*/
+#define	SCCM_TXE	((unsigned char)0x10)
+#define	SCCM_BSY	((unsigned char)0x04)
+#define	SCCM_TX		((unsigned char)0x02)
+#define	SCCM_RX		((unsigned char)0x01)
+
+typedef struct scc_param {
+	ushort	scc_rbase;	/* Rx Buffer descriptor base address */
+	ushort	scc_tbase;	/* Tx Buffer descriptor base address */
+	u_char	scc_rfcr;	/* Rx function code */
+	u_char	scc_tfcr;	/* Tx function code */
+	ushort	scc_mrblr;	/* Max receive buffer length */
+	uint	scc_rstate;	/* Internal */
+	uint	scc_idp;	/* Internal */
+	ushort	scc_rbptr;	/* Internal */
+	ushort	scc_ibc;	/* Internal */
+	uint	scc_rxtmp;	/* Internal */
+	uint	scc_tstate;	/* Internal */
+	uint	scc_tdp;	/* Internal */
+	ushort	scc_tbptr;	/* Internal */
+	ushort	scc_tbc;	/* Internal */
+	uint	scc_txtmp;	/* Internal */
+	uint	scc_rcrc;	/* Internal */
+	uint	scc_tcrc;	/* Internal */
+} sccp_t;
+
+/* Function code bits.
+*/
+#define SCC_EB	((u_char)0x10)	/* Set big endian byte order */
+
+/* CPM Ethernet through SCC1.
+ */
+typedef struct scc_enet {
+	sccp_t	sen_genscc;
+	uint	sen_cpres;	/* Preset CRC */
+	uint	sen_cmask;	/* Constant mask for CRC */
+	uint	sen_crcec;	/* CRC Error counter */
+	uint	sen_alec;	/* alignment error counter */
+	uint	sen_disfc;	/* discard frame counter */
+	ushort	sen_pads;	/* Tx short frame pad character */
+	ushort	sen_retlim;	/* Retry limit threshold */
+	ushort	sen_retcnt;	/* Retry limit counter */
+	ushort	sen_maxflr;	/* maximum frame length register */
+	ushort	sen_minflr;	/* minimum frame length register */
+	ushort	sen_maxd1;	/* maximum DMA1 length */
+	ushort	sen_maxd2;	/* maximum DMA2 length */
+	ushort	sen_maxd;	/* Rx max DMA */
+	ushort	sen_dmacnt;	/* Rx DMA counter */
+	ushort	sen_maxb;	/* Max BD byte count */
+	ushort	sen_gaddr1;	/* Group address filter */
+	ushort	sen_gaddr2;
+	ushort	sen_gaddr3;
+	ushort	sen_gaddr4;
+	uint	sen_tbuf0data0;	/* Save area 0 - current frame */
+	uint	sen_tbuf0data1;	/* Save area 1 - current frame */
+	uint	sen_tbuf0rba;	/* Internal */
+	uint	sen_tbuf0crc;	/* Internal */
+	ushort	sen_tbuf0bcnt;	/* Internal */
+	ushort	sen_paddrh;	/* physical address (MSB) */
+	ushort	sen_paddrm;
+	ushort	sen_paddrl;	/* physical address (LSB) */
+	ushort	sen_pper;	/* persistence */
+	ushort	sen_rfbdptr;	/* Rx first BD pointer */
+	ushort	sen_tfbdptr;	/* Tx first BD pointer */
+	ushort	sen_tlbdptr;	/* Tx last BD pointer */
+	uint	sen_tbuf1data0;	/* Save area 0 - current frame */
+	uint	sen_tbuf1data1;	/* Save area 1 - current frame */
+	uint	sen_tbuf1rba;	/* Internal */
+	uint	sen_tbuf1crc;	/* Internal */
+	ushort	sen_tbuf1bcnt;	/* Internal */
+	ushort	sen_txlen;	/* Tx Frame length counter */
+	ushort	sen_iaddr1;	/* Individual address filter */
+	ushort	sen_iaddr2;
+	ushort	sen_iaddr3;
+	ushort	sen_iaddr4;
+	ushort	sen_boffcnt;	/* Backoff counter */
+
+	/* NOTE: Some versions of the manual have the following items
+	 * incorrectly documented.  Below is the proper order.
+	 */
+	ushort	sen_taddrh;	/* temp address (MSB) */
+	ushort	sen_taddrm;
+	ushort	sen_taddrl;	/* temp address (LSB) */
+} scc_enet_t;
+
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC1 use.  The TCLK and RCLK seem unique
+ * to the MBX860 board.  Any two of the four available clocks could be
+ * used, and the MPC860 cookbook manual has an example using different
+ * clock pins.
+ */
+#define PA_ENET_RXD	((ushort)0x0001)
+#define PA_ENET_TXD	((ushort)0x0002)
+#define PA_ENET_TCLK	((ushort)0x0200)
+#define PA_ENET_RCLK	((ushort)0x0800)
+#define PC_ENET_TENA	((ushort)0x0001)
+#define PC_ENET_CLSN	((ushort)0x0010)
+#define PC_ENET_RENA	((ushort)0x0020)
+
+/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
+ * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
+ */
+#define SICR_ENET_MASK	((uint)0x000000ff)
+#define SICR_ENET_CLKRT	((uint)0x0000003d)
+
+/* SCC Event register as used by Ethernet.
+*/
+#define SCCE_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
+#define SCCE_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
+#define SCCE_ENET_RXF	((ushort)0x0008)	/* Full frame received */
+#define SCCE_ENET_BSY	((ushort)0x0004)	/* All incoming buffers full */
+#define SCCE_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
+#define SCCE_ENET_RXB	((ushort)0x0001)	/* A buffer was received */
+
+/* SCC Mode Register (PMSR) as used by Ethernet.
+*/
+#define SCC_PMSR_HBC	((ushort)0x8000)	/* Enable heartbeat */
+#define SCC_PMSR_FC	((ushort)0x4000)	/* Force collision */
+#define SCC_PMSR_RSH	((ushort)0x2000)	/* Receive short frames */
+#define SCC_PMSR_IAM	((ushort)0x1000)	/* Check individual hash */
+#define SCC_PMSR_ENCRC	((ushort)0x0800)	/* Ethernet CRC mode */
+#define SCC_PMSR_PRO	((ushort)0x0200)	/* Promiscuous mode */
+#define SCC_PMSR_BRO	((ushort)0x0100)	/* Catch broadcast pkts */
+#define SCC_PMSR_SBT	((ushort)0x0080)	/* Special backoff timer */
+#define SCC_PMSR_LPB	((ushort)0x0040)	/* Set Loopback mode */
+#define SCC_PMSR_SIP	((ushort)0x0020)	/* Sample Input Pins */
+#define SCC_PMSR_LCW	((ushort)0x0010)	/* Late collision window */
+#define SCC_PMSR_NIB22	((ushort)0x000a)	/* Start frame search */
+#define SCC_PMSR_FDE	((ushort)0x0001)	/* Full duplex enable */
+
+/* Buffer descriptor control/status used by Ethernet receive.
+*/
+#define BD_ENET_RX_EMPTY	((ushort)0x8000)
+#define BD_ENET_RX_WRAP		((ushort)0x2000)
+#define BD_ENET_RX_INTR		((ushort)0x1000)
+#define BD_ENET_RX_LAST		((ushort)0x0800)
+#define BD_ENET_RX_FIRST	((ushort)0x0400)
+#define BD_ENET_RX_MISS		((ushort)0x0100)
+#define BD_ENET_RX_LG		((ushort)0x0020)
+#define BD_ENET_RX_NO		((ushort)0x0010)
+#define BD_ENET_RX_SH		((ushort)0x0008)
+#define BD_ENET_RX_CR		((ushort)0x0004)
+#define BD_ENET_RX_OV		((ushort)0x0002)
+#define BD_ENET_RX_CL		((ushort)0x0001)
+#define BD_ENET_RX_STATS	((ushort)0x013f)	/* All status bits */
+
+/* Buffer descriptor control/status used by Ethernet transmit.
+*/
+#define BD_ENET_TX_READY	((ushort)0x8000)
+#define BD_ENET_TX_PAD		((ushort)0x4000)
+#define BD_ENET_TX_WRAP		((ushort)0x2000)
+#define BD_ENET_TX_INTR		((ushort)0x1000)
+#define BD_ENET_TX_LAST		((ushort)0x0800)
+#define BD_ENET_TX_TC		((ushort)0x0400)
+#define BD_ENET_TX_DEF		((ushort)0x0200)
+#define BD_ENET_TX_HB		((ushort)0x0100)
+#define BD_ENET_TX_LC		((ushort)0x0080)
+#define BD_ENET_TX_RL		((ushort)0x0040)
+#define BD_ENET_TX_RCMASK	((ushort)0x003c)
+#define BD_ENET_TX_UN		((ushort)0x0002)
+#define BD_ENET_TX_CSL		((ushort)0x0001)
+#define BD_ENET_TX_STATS	((ushort)0x03ff)	/* All status bits */
+
+/* SCC as UART
+*/
+typedef struct scc_uart {
+	sccp_t	scc_genscc;
+	uint	scc_res1;	/* Reserved */
+	uint	scc_res2;	/* Reserved */
+	ushort	scc_maxidl;	/* Maximum idle chars */
+	ushort	scc_idlc;	/* temp idle counter */
+	ushort	scc_brkcr;	/* Break count register */
+	ushort	scc_parec;	/* receive parity error counter */
+	ushort	scc_frmec;	/* receive framing error counter */
+	ushort	scc_nosec;	/* receive noise counter */
+	ushort	scc_brkec;	/* receive break condition counter */
+	ushort	scc_brkln;	/* last received break length */
+	ushort	scc_uaddr1;	/* UART address character 1 */
+	ushort	scc_uaddr2;	/* UART address character 2 */
+	ushort	scc_rtemp;	/* Temp storage */
+	ushort	scc_toseq;	/* Transmit out of sequence char */
+	ushort	scc_char1;	/* control character 1 */
+	ushort	scc_char2;	/* control character 2 */
+	ushort	scc_char3;	/* control character 3 */
+	ushort	scc_char4;	/* control character 4 */
+	ushort	scc_char5;	/* control character 5 */
+	ushort	scc_char6;	/* control character 6 */
+	ushort	scc_char7;	/* control character 7 */
+	ushort	scc_char8;	/* control character 8 */
+	ushort	scc_rccm;	/* receive control character mask */
+	ushort	scc_rccr;	/* receive control character register */
+	ushort	scc_rlbc;	/* receive last break character */
+} scc_uart_t;
+
+/* SCC Event and Mask registers when it is used as a UART.
+*/
+#define UART_SCCM_GLR		((ushort)0x1000)
+#define UART_SCCM_GLT		((ushort)0x0800)
+#define UART_SCCM_AB		((ushort)0x0200)
+#define UART_SCCM_IDL		((ushort)0x0100)
+#define UART_SCCM_GRA		((ushort)0x0080)
+#define UART_SCCM_BRKE		((ushort)0x0040)
+#define UART_SCCM_BRKS		((ushort)0x0020)
+#define UART_SCCM_CCR		((ushort)0x0008)
+#define UART_SCCM_BSY		((ushort)0x0004)
+#define UART_SCCM_TX		((ushort)0x0002)
+#define UART_SCCM_RX		((ushort)0x0001)
+
+/* The SCC PMSR when used as a UART.
+*/
+#define SCU_PMSR_FLC		((ushort)0x8000)
+#define SCU_PMSR_SL		((ushort)0x4000)
+#define SCU_PMSR_CL		((ushort)0x3000)
+#define SCU_PMSR_UM		((ushort)0x0c00)
+#define SCU_PMSR_FRZ		((ushort)0x0200)
+#define SCU_PMSR_RZS		((ushort)0x0100)
+#define SCU_PMSR_SYN		((ushort)0x0080)
+#define SCU_PMSR_DRT		((ushort)0x0040)
+#define SCU_PMSR_PEN		((ushort)0x0010)
+#define SCU_PMSR_RPM		((ushort)0x000c)
+#define SCU_PMSR_REVP		((ushort)0x0008)
+#define SCU_PMSR_TPM		((ushort)0x0003)
+#define SCU_PMSR_TEVP		((ushort)0x0003)
+
+/* CPM Transparent mode SCC.
+ */
+typedef struct scc_trans {
+	sccp_t	st_genscc;
+	uint	st_cpres;	/* Preset CRC */
+	uint	st_cmask;	/* Constant mask for CRC */
+} scc_trans_t;
+
+/* CPM interrupts.  There are nearly 32 interrupts generated by CPM
+ * channels or devices.  All of these are presented to the PPC core
+ * as a single interrupt.  The CPM interrupt handler dispatches its
+ * own handlers, in a similar fashion to the PPC core handler.  We
+ * use the table as defined in the manuals (i.e. no special high
+ * priority and SCC1 == SCCa, etc...).
+ */
+#define CPMVEC_NR		32
+#define	CPMVEC_PIO_PC15		((ushort)0x1f)
+#define	CPMVEC_SCC1		((ushort)0x1e)
+#define	CPMVEC_SCC2		((ushort)0x1d)
+#define	CPMVEC_SCC3		((ushort)0x1c)
+#define	CPMVEC_SCC4		((ushort)0x1b)
+#define	CPMVEC_PIO_PC14		((ushort)0x1a)
+#define	CPMVEC_TIMER1		((ushort)0x19)
+#define	CPMVEC_PIO_PC13		((ushort)0x18)
+#define	CPMVEC_PIO_PC12		((ushort)0x17)
+#define	CPMVEC_SDMA_CB_ERR	((ushort)0x16)
+#define CPMVEC_IDMA1		((ushort)0x15)
+#define CPMVEC_IDMA2		((ushort)0x14)
+#define CPMVEC_TIMER2		((ushort)0x12)
+#define CPMVEC_RISCTIMER	((ushort)0x11)
+#define CPMVEC_I2C		((ushort)0x10)
+#define	CPMVEC_PIO_PC11		((ushort)0x0f)
+#define	CPMVEC_PIO_PC10		((ushort)0x0e)
+#define CPMVEC_TIMER3		((ushort)0x0c)
+#define	CPMVEC_PIO_PC9		((ushort)0x0b)
+#define	CPMVEC_PIO_PC8		((ushort)0x0a)
+#define	CPMVEC_PIO_PC7		((ushort)0x09)
+#define CPMVEC_TIMER4		((ushort)0x07)
+#define	CPMVEC_PIO_PC6		((ushort)0x06)
+#define	CPMVEC_SPI		((ushort)0x05)
+#define	CPMVEC_SMC1		((ushort)0x04)
+#define	CPMVEC_SMC2		((ushort)0x03)
+#define	CPMVEC_PIO_PC5		((ushort)0x02)
+#define	CPMVEC_PIO_PC4		((ushort)0x01)
+#define	CPMVEC_ERROR		((ushort)0x00)
+
+extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id);
+
+/* CPM interrupt configuration vector.
+*/
+#define	CICR_SCD_SCC4		((uint)0x00c00000)	/* SCC4 @ SCCd */
+#define	CICR_SCC_SCC3		((uint)0x00200000)	/* SCC3 @ SCCc */
+#define	CICR_SCB_SCC2		((uint)0x00040000)	/* SCC2 @ SCCb */
+#define	CICR_SCA_SCC1		((uint)0x00000000)	/* SCC1 @ SCCa */
+#define CICR_IRL_MASK		((uint)0x0000e000)	/* Core interrrupt */
+#define CICR_HP_MASK		((uint)0x00001f00)	/* Hi-pri int. */
+#define CICR_IEN		((uint)0x00000080)	/* Int. enable */
+#define CICR_SPS		((uint)0x00000001)	/* SCC Spread */
+#endif /* __CPM_8XX__ */
diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/include/mbx.h b/c/src/lib/libbsp/powerpc/mbx8xx/include/mbx.h
new file mode 100644
index 0000000000..0c72b4a9a9
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/mbx8xx/include/mbx.h
@@ -0,0 +1,62 @@
+
+/*
+ * A collection of structures, addresses, and values associated with
+ * the Motorola MBX boards.  This was originally created for the
+ * MBX860, and probably needs revisions for other boards (like the 821).
+ * When this file gets out of control, we can split it up into more
+ * meaningful pieces.
+ *
+ * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
+ */
+#ifndef __MACH_MBX_DEFS
+#define __MACH_MBX_DEFS
+
+/* A Board Information structure that is given to a program when
+ * EPPC-Bug starts it up.
+ */
+typedef struct bd_info {
+	unsigned int	bi_tag;		/* Should be 0x42444944 "BDID" */
+	unsigned int	bi_size;	/* Size of this structure */
+	unsigned int	bi_revision;	/* revision of this structure */
+	unsigned int	bi_bdate;	/* EPPCbug date, i.e. 0x11061997 */
+	unsigned int	bi_memstart;	/* Memory start address */
+	unsigned int	bi_memsize;	/* Memory (end) size in bytes */
+	unsigned int	bi_intfreq;	/* Internal Freq, in Hz */
+	unsigned int	bi_busfreq;	/* Bus Freq, in Hz */
+	unsigned int	bi_clun;	/* Boot device controller */
+	unsigned int	bi_dlun;	/* Boot device logical dev */
+} bd_t;
+
+/* Memory map for the MBX as configured by EPPC-Bug.  We could reprogram
+ * The SIU and PCI bridge, and try to use larger MMU pages, but the
+ * performance gain is not measureable and it certainly complicates the
+ * generic MMU model.
+ *
+ * In a effort to minimize memory usage for embedded applications, any
+ * PCI driver or ISA driver must request or map the region required by
+ * the device.  For convenience (and since we can map up to 4 Mbytes with
+ * a single page table page), the MMU initialization will map the
+ * NVRAM, Status/Control registers, CPM Dual Port RAM, and the PCI
+ * Bridge CSRs 1:1 into the kernel address space.
+ */
+#define PCI_ISA_IO_ADDR		((unsigned int)0x80000000)
+#define PCI_ISA_IO_SIZE		((unsigned int)(512 * 1024 * 1024))
+#define PCI_ISA_MEM_ADDR	((unsigned int)0xc0000000)
+#define PCI_ISA_MEM_SIZE	((unsigned int)(512 * 1024 * 1024))
+#define PCMCIA_MEM_ADDR		((unsigned int)0xe0000000)
+#define PCMCIA_MEM_SIZE		((unsigned int)(64 * 1024 * 1024))
+#define PCMCIA_DMA_ADDR		((unsigned int)0xe4000000)
+#define PCMCIA_DMA_SIZE		((unsigned int)(64 * 1024 * 1024))
+#define PCMCIA_ATTRB_ADDR	((unsigned int)0xe8000000)
+#define PCMCIA_ATTRB_SIZE	((unsigned int)(64 * 1024 * 1024))
+#define PCMCIA_IO_ADDR		((unsigned int)0xec000000)
+#define PCMCIA_IO_SIZE		((unsigned int)(64 * 1024 * 1024))
+#define NVRAM_ADDR		((unsigned int)0xfa000000)
+#define NVRAM_SIZE		((unsigned int)(1 * 1024 * 1024))
+#define MBX_CSR_ADDR		((unsigned int)0xfa100000)
+#define MBX_CSR_SIZE		((unsigned int)(1 * 1024 * 1024))
+#define IMAP_ADDR		((unsigned int)0xfa200000)
+#define IMAP_SIZE		((unsigned int)(64 * 1024))
+#define PCI_CSR_ADDR		((unsigned int)0xfa210000)
+#define PCI_CSR_SIZE		((unsigned int)(64 * 1024))
+#endif