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author | Ralf Corsepius <ralf.corsepius@rtems.org> | 2009-11-30 04:37:44 +0000 |
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committer | Ralf Corsepius <ralf.corsepius@rtems.org> | 2009-11-30 04:37:44 +0000 |
commit | ac7af4a359cc51bc06e1bf0ed3314744972b8395 (patch) | |
tree | 7c73805f8b66af9b3082fbde80f6eb70edd966ac /c/src/lib/libbsp/powerpc/haleakala/irq | |
parent | 2009-11-30 Ralf Corsépius <ralf.corsepius@rtems.org> (diff) | |
download | rtems-ac7af4a359cc51bc06e1bf0ed3314744972b8395.tar.bz2 |
Whitespace removal.
Diffstat (limited to 'c/src/lib/libbsp/powerpc/haleakala/irq')
-rw-r--r-- | c/src/lib/libbsp/powerpc/haleakala/irq/irq.c | 44 | ||||
-rw-r--r-- | c/src/lib/libbsp/powerpc/haleakala/irq/irq.h | 12 | ||||
-rw-r--r-- | c/src/lib/libbsp/powerpc/haleakala/irq/irq_init.c | 6 |
3 files changed, 31 insertions, 31 deletions
diff --git a/c/src/lib/libbsp/powerpc/haleakala/irq/irq.c b/c/src/lib/libbsp/powerpc/haleakala/irq/irq.c index 736fde0e52..e6263389d4 100644 --- a/c/src/lib/libbsp/powerpc/haleakala/irq/irq.c +++ b/c/src/lib/libbsp/powerpc/haleakala/irq/irq.c @@ -69,11 +69,11 @@ static inline int IsUICIRQ(const rtems_irq_number irqLine) static void WriteIState(void) /* Write the gEnabledInts state masked by gIntInhibited to the hardware */ { - PPC_SET_DEVICE_CONTROL_REGISTER(UIC0_ER, + PPC_SET_DEVICE_CONTROL_REGISTER(UIC0_ER, gEnabledInts[0] & ~gIntInhibited[0]); - PPC_SET_DEVICE_CONTROL_REGISTER(UIC1_ER, + PPC_SET_DEVICE_CONTROL_REGISTER(UIC1_ER, gEnabledInts[1] & ~gIntInhibited[1]); - PPC_SET_DEVICE_CONTROL_REGISTER(UIC2_ER, + PPC_SET_DEVICE_CONTROL_REGISTER(UIC2_ER, gEnabledInts[2] & ~gIntInhibited[2]); } @@ -96,7 +96,7 @@ BSP_disable_irq_at_pic(const rtems_irq_number irq) uint32_t oldState; int iword = irq>>5; uint32_t mask = (0x80000000 >> (irq & 0x1F)); - + oldState = gEnabledInts[iword] & mask; gEnabledInts[iword] &= ~mask; WriteIState(); @@ -109,14 +109,14 @@ int BSP_setup_the_pic(rtems_irq_global_settings* config) { int i; - + dflt_entry = config->defaultEntry; rtems_hdl_tblP = config->irqHdlTbl; for (i=0; i<kUICWords; i++) gIntInhibited[i] = 0; - + /* disable all interrupts */ - PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_ER, 0x00000000); + PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_ER, 0x00000000); /* Set Critical / Non Critical interrupts */ PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_CR, 0x00000000); /* Set Interrupt Polarities */ @@ -153,7 +153,7 @@ BSP_setup_the_pic(rtems_irq_global_settings* config) PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_VR, 0x00000001); /* clear all interrupts */ PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_SR, 0xffffffff); - + return 1; } @@ -164,8 +164,8 @@ BSP_setup_the_pic(rtems_irq_global_settings* config) * * No support for critical interrupts here yet */ - -int + +int C_dispatch_irq_handler( BSP_Exception_frame* frame, unsigned int excNum ) { if (excNum == ASM_EXT_VECTOR) { @@ -180,15 +180,15 @@ C_dispatch_irq_handler( BSP_Exception_frame* frame, unsigned int excNum ) gIntInhibited[0] |= active[0]; gIntInhibited[1] |= active[1]; gIntInhibited[2] |= active[2]; - + /* ...and update the hardware so the active interrupts are disabled */ WriteIState(); - + /* Loop, calling bsp_irq_dispatch_list for each active interrupt */ while ((active[0] | active[1] | active[2]) != 0) { uint32_t index = -1; uint32_t bit, bmask; - + /* Find an active interrupt, searching 0..2, bit 0..bit 31 (IBM order) */ do { index++; @@ -201,17 +201,17 @@ C_dispatch_irq_handler( BSP_Exception_frame* frame, unsigned int excNum ) /* Write a 1-bit to the appropriate status register to clear it */ bmask = 0x80000000 >> bit; switch (index) { - case 0: + case 0: PPC_SET_DEVICE_CONTROL_REGISTER(UIC0_SR, bmask); break; - case 1: + case 1: PPC_SET_DEVICE_CONTROL_REGISTER(UIC1_SR, bmask); break; - case 2: + case 2: PPC_SET_DEVICE_CONTROL_REGISTER(UIC2_SR, bmask); break; } - + /* Clear in the active record and gIntInhibited */ active[index] &= ~bmask; gIntInhibited[index] &= ~bmask; @@ -220,20 +220,20 @@ C_dispatch_irq_handler( BSP_Exception_frame* frame, unsigned int excNum ) /* Update the hardware again so the interrupts we have handled are unmasked */ WriteIState(); return 0; - + } else if (excNum == ASM_DEC_VECTOR) { /* 0x1000 remapped by C_dispatch_dec_handler_bookE */ bsp_irq_dispatch_list(rtems_hdl_tblP, BSP_PIT, dflt_entry.hdl); return 0; - + } else if (excNum == ASM_BOOKE_FIT_VECTOR) { /* 0x1010 mapped to 0x13 by ppc_get_vector_addr */ bsp_irq_dispatch_list(rtems_hdl_tblP, BSP_FIT, dflt_entry.hdl); return 0; - + } else if (excNum == ASM_BOOKE_WDOG_VECTOR) { /* 0x1020 mapped to 0x14 by ppc_get_vector_addr */ bsp_irq_dispatch_list(rtems_hdl_tblP, BSP_WDOG, dflt_entry.hdl); return 0; - - } else + + } else return -1; /* unhandled interrupt, panic time */ } diff --git a/c/src/lib/libbsp/powerpc/haleakala/irq/irq.h b/c/src/lib/libbsp/powerpc/haleakala/irq/irq.h index 908fe4bf9b..d8395a609b 100644 --- a/c/src/lib/libbsp/powerpc/haleakala/irq/irq.h +++ b/c/src/lib/libbsp/powerpc/haleakala/irq/irq.h @@ -23,7 +23,7 @@ #ifdef __cplusplus extern "C" { #endif - + /* Define UIC interrupt numbers; IRQs that cause an external interrupt that needs further decode. These are arbitrary but it makes things easier if they match the CPU interrupt numbers */ @@ -103,7 +103,7 @@ extern "C" { #define BSP_UIC_EIPKP_SLAVE (BSP_UIC1_IRQ_LOWEST_OFFSET + 7) #define BSP_UIC_GPT_TIMER5 (BSP_UIC1_IRQ_LOWEST_OFFSET + 8) #define BSP_UIC_GPT_TIMER6 (BSP_UIC1_IRQ_LOWEST_OFFSET + 9) - + #define BSP_UIC_GPT_TIMER0 (BSP_UIC1_IRQ_LOWEST_OFFSET + 16) #define BSP_UIC_GPT_TIMER1 (BSP_UIC1_IRQ_LOWEST_OFFSET + 17) #define BSP_UIC_IRQ7 (BSP_UIC1_IRQ_LOWEST_OFFSET + 18) @@ -127,7 +127,7 @@ extern "C" { #define BSP_UIC_PCIe0INTC (BSP_UIC2_IRQ_LOWEST_OFFSET + 2) #define BSP_UIC_PCIe0INTD (BSP_UIC2_IRQ_LOWEST_OFFSET + 3) #define BSP_UIC_IRQ3 (BSP_UIC2_IRQ_LOWEST_OFFSET + 4) - + #define BSP_UIC_USBOTG (BSP_UIC2_IRQ_LOWEST_OFFSET + 30) #define BSP_UIC_IRQ_NUMBER (95) @@ -143,7 +143,7 @@ extern "C" { #define BSP_PIT BSP_PROCESSOR_IRQ_LOWEST_OFFSET /* Required by ppc403/clock.c */ #define BSP_FIT BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1 - #define BSP_WDOG BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2 + #define BSP_WDOG BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2 #define BSP_PROCESSOR_IRQ_NUMBER (3) #define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_UIC_IRQ_MAX_OFFSET + 1) @@ -154,10 +154,10 @@ extern "C" { #define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) #define BSP_LOWEST_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET) #define BSP_MAX_OFFSET (BSP_IRQ_NUMBER - 1) - + extern void BSP_rtems_irq_mng_init(unsigned cpuId); // Implemented in irq_init.c #include <bsp/irq_supp.h> - + #ifdef __cplusplus } #endif diff --git a/c/src/lib/libbsp/powerpc/haleakala/irq/irq_init.c b/c/src/lib/libbsp/powerpc/haleakala/irq/irq_init.c index cafe6f6d7a..1e801c8431 100644 --- a/c/src/lib/libbsp/powerpc/haleakala/irq/irq_init.c +++ b/c/src/lib/libbsp/powerpc/haleakala/irq/irq_init.c @@ -57,7 +57,7 @@ static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={ void BSP_rtems_irq_mng_init(unsigned cpuId) { int i; - + /* * re-init the rtemsIrq table */ @@ -82,8 +82,8 @@ void BSP_rtems_irq_mng_init(unsigned cpuId) "Unable to initialize RTEMS interrupt management!!! System locked\n" ); } - - #ifdef TRACE_IRQ_INIT + + #ifdef TRACE_IRQ_INIT printk("RTEMS IRQ management is now operational\n"); #endif } |