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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2013-04-19 11:53:07 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2013-04-23 09:59:57 +0200 |
| commit | 92d80383ff5b83258a111f90e17fb1c6825297b8 (patch) | |
| tree | 0cd791cef811c6862e4dfab41c037224d8762481 /c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c | |
| parent | bsp/mpc5200: Change SDRAM initialization (diff) | |
| download | rtems-92d80383ff5b83258a111f90e17fb1c6825297b8.tar.bz2 | |
bsp/mpc5200: New BSP variant BRS6L
Diffstat (limited to 'c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c')
| -rw-r--r-- | c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c | 54 |
1 files changed, 41 insertions, 13 deletions
diff --git a/c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c b/c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c index 6a1a810681..1379667cd3 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c +++ b/c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c @@ -121,7 +121,7 @@ static void cpu_init_bsp(void) { BAT dbat; -#if defined(MPC5200_BOARD_BRS5L) +#if defined(MPC5200_BOARD_BRS5L) || defined(MPC5200_BOARD_BRS6L) calc_dbat_regvals( &dbat, (uint32_t) bsp_ram_start, @@ -157,18 +157,6 @@ static void cpu_init_bsp(void) BPP_RW ); SET_DBAT(2,dbat.batu,dbat.batl); - - calc_dbat_regvals( - &dbat, - (uint32_t) bsp_dpram_start, - 128 * 1024, - false, - true, - false, - true, - BPP_RW - ); - SET_DBAT(3,dbat.batu,dbat.batl); #elif defined (HAS_UBOOT) uint32_t start = 0; @@ -285,6 +273,46 @@ static void cpu_init_bsp(void) BPP_RW ); SET_DBAT(4, dbat.batu, dbat.batl); +#elif defined(MPC5200_BOARD_BRS5L) + calc_dbat_regvals( + &dbat, + (uint32_t) bsp_dpram_start, + 128 * 1024, + false, + true, + false, + true, + BPP_RW + ); + SET_DBAT(3,dbat.batu,dbat.batl); +#elif defined(MPC5200_BOARD_BRS6L) + enable_bat_4_to_7(); + + /* FPGA */ + calc_dbat_regvals( + &dbat, + MPC5200_BRS6L_FPGA_BEGIN, + MPC5200_BRS6L_FPGA_SIZE, + false, + true, + false, + true, + BPP_RW + ); + SET_DBAT(3,dbat.batu,dbat.batl); + + /* MRAM */ + calc_dbat_regvals( + &dbat, + MPC5200_BRS6L_MRAM_BEGIN, + MPC5200_BRS6L_MRAM_SIZE, + true, + false, + false, + false, + BPP_RW + ); + SET_DBAT(4,dbat.batu,dbat.batl); #endif } |