update to current PPC exception and memory map structure

3 files changed, 521 insertions, 0 deletions

diff --git a/c/src/lib/libbsp/powerpc/gen5200/include/irq-config.h b/c/src/lib/libbsp/powerpc/gen5200/include/irq-config.h
new file mode 100644
index 0000000000..bf50e06ad8
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/gen5200/include/irq-config.h
@@ -0,0 +1,44 @@
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ *
+ * @brief BSP interrupt support configuration.
+ */
+
+/*
+ * Copyright (c) 2008
+ * Embedded Brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * rtems@embedded-brains.de
+ *
+ * The license and distribution terms for this file may be found in the file
+ * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_POWERPC_GEN5200_IRQ_CONFIG_H
+#define LIBBSP_POWERPC_GEN5200_IRQ_CONFIG_H
+
+#include <bsp/irq.h>
+
+/**
+ * @addtogroup bsp_interrupt
+ *
+ * @{
+ */
+
+/**
+ * @brief Minimum vector number.
+ */
+#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET
+
+/**
+ * @brief Maximum vector number.
+ */
+#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET
+
+/** @} */
+
+#endif /* LIBBSP_POWERPC_GEN5200_IRQ_CONFIG_H */
diff --git a/c/src/lib/libbsp/powerpc/gen5200/include/irq.h b/c/src/lib/libbsp/powerpc/gen5200/include/irq.h
new file mode 100644
index 0000000000..a8d516093a
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/gen5200/include/irq.h
@@ -0,0 +1,211 @@
+/*===============================================================*\
+| Project: RTEMS generic MPC5200 BSP                              |
++-----------------------------------------------------------------+
+| Partially based on the code references which are named below.   |
+| Adaptions, modifications, enhancements and any recent parts of  |
+| the code are:                                                   |
+|                    Copyright (c) 2005                           |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.com/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+| this file contains declarations for the irq controller handler  |
+\*===============================================================*/
+/***********************************************************************/
+/*                                                                     */
+/*   Module:       irq.h                                               */
+/*   Date:         07/17/2003                                          */
+/*   Purpose:      RTEMS MPC5x00 CPU interrupt header file             */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   Description:  This include file describe the data structure and   */
+/*                 the functions implemented by rtems to write         */
+/*                 interrupt handlers.                                 */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   Code                                                              */
+/*   References:   MPC8260ads CPU interrupt header file                */
+/*   Module:       irq.h                                               */
+/*   Project:      RTEMS 4.6.0pre1 / MCF8260ads BSP                    */
+/*   Version       1.1                                                 */
+/*   Date:         10/10/2002                                          */
+/*                                                                     */
+/*   Author(s) / Copyright(s):                                         */
+/*                                                                     */
+/*   Copyright (C) 1999 valette@crf.canon.fr                           */
+/*                                                                     */
+/*   This code is heavilly inspired by the public specification of     */
+/*   STREAM V2 that can be found at:                                   */
+/*                                                                     */
+/*   <http://www.chorus.com/Documentation/index.html> by following     */
+/*   the STREAM API Specification Document link.                       */
+/*                                                                     */
+/*   Modified for mpc8260 by Andy Dachs <a.dachs@sstl.co.uk>           */
+/*   Surrey Satellite Technology Limited                               */
+/*   The interrupt handling on the mpc8260 seems quite different from  */
+/*   the 860 (I don't know the 860 well).  Although some interrupts    */
+/*   are routed via the CPM irq and some are direct to the SIU they    */
+/*   all appear logically the same.Therefore I removed the distinction */
+/*   between SIU and CPM interrupts.                                   */
+/*                                                                     */
+/*   The license and distribution terms for this file may be           */
+/*   found in found in the file LICENSE in this distribution or at     */
+/*   http://www.rtems.com/license/LICENSE.                        */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   Partially based on the code references which are named above.     */
+/*   Adaptions, modifications, enhancements and any recent parts of    */
+/*   the code are under the right of                                   */
+/*                                                                     */
+/*         IPR Engineering, Dachauer Straße 38, D-80335 München        */
+/*                        Copyright(C) 2003                            */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   IPR Engineering makes no representation or warranties with        */
+/*   respect to the performance of this computer program, and          */
+/*   specifically disclaims any responsibility for any damages,        */
+/*   special or consequential, connected with the use of this program. */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   Version history:  1.0                                             */
+/*                                                                     */
+/***********************************************************************/
+
+#ifndef LIBBSP_POWERPC_GEN5200_IRQ_H
+#define LIBBSP_POWERPC_GEN5200_IRQ_H
+
+#define CHK_CE_SHADOW(_pmce)	((_pmce) & 0x00000001)
+#define CHK_CSE_STICKY(_pmce)	(((_pmce) >> 10) & 0x00000001)
+#define CHK_MSE_STICKY(_pmce)	(((_pmce) >> 21) & 0x00000001)
+#define CHK_PSE_STICKY(_pmce)	(((_pmce) >> 29) & 0x00000001)
+#define CLR_CSE_STICKY(_pmce)	((_pmce) |= (1 << 29 ))
+#define CLR_MSE_STICKY(_pmce)	((_pmce) |= (1 << 21 ))
+#define CLR_PSE_STICKY(_pmce)	((_pmce) |= (1 << 10 ))
+#define CSE_SOURCE(_source)	(((_source) >> 8) & 0x00000003)
+#define MSE_SOURCE(_source)	(((_source) >> 16) & 0x0000001F)
+#define PSE_SOURCE(_source)	(((_source) >> 24) & 0x0000001F)
+
+/*
+ * Peripheral IRQ handlers related definitions
+ */
+#define BSP_PER_IRQ_NUMBER		22
+#define BSP_PER_IRQ_LOWEST_OFFSET	0
+#define BSP_PER_IRQ_MAX_OFFSET		\
+	(BSP_PER_IRQ_LOWEST_OFFSET + BSP_PER_IRQ_NUMBER - 1) /* 21 */
+/*
+ * Main IRQ handlers related definitions
+ */
+#define BSP_MAIN_IRQ_NUMBER		17
+#define BSP_MAIN_IRQ_LOWEST_OFFSET	BSP_PER_IRQ_MAX_OFFSET + 1 /* 22 */
+#define BSP_MAIN_IRQ_MAX_OFFSET		\
+	(BSP_MAIN_IRQ_LOWEST_OFFSET + BSP_MAIN_IRQ_NUMBER - 1) /* 38 */
+/*
+ * Critical IRQ handlers related definitions
+ */
+#define BSP_CRIT_IRQ_NUMBER		4
+#define BSP_CRIT_IRQ_LOWEST_OFFSET	BSP_MAIN_IRQ_MAX_OFFSET + 1 /* 39 */
+#define BSP_CRIT_IRQ_MAX_OFFSET		\
+	(BSP_CRIT_IRQ_LOWEST_OFFSET + BSP_CRIT_IRQ_NUMBER - 1) /* 42 */
+/*
+ * Summary of SIU interrupts
+ */
+#define BSP_SIU_IRQ_NUMBER		BSP_CRIT_IRQ_MAX_OFFSET + 1 /* 43 */
+#define BSP_SIU_IRQ_LOWEST_OFFSET	BSP_PER_IRQ_LOWEST_OFFSET /* 0 */
+#define BSP_SIU_IRQ_MAX_OFFSET		BSP_CRIT_IRQ_MAX_OFFSET	 /* 42 */
+/*
+ * Processor IRQ handlers related definitions
+ */
+#define BSP_PROCESSOR_IRQ_NUMBER	3
+#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET	BSP_CRIT_IRQ_MAX_OFFSET + 1 /* 44  */
+#define BSP_PROCESSOR_IRQ_MAX_OFFSET	\
+        (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) /* 46 */
+/*
+ * Summary
+ */
+#define BSP_IRQ_NUMBER		BSP_PROCESSOR_IRQ_MAX_OFFSET + 1 /* 47 */
+#define BSP_LOWEST_OFFSET	BSP_PER_IRQ_LOWEST_OFFSET /* 0 */
+#define BSP_MAX_OFFSET		BSP_PROCESSOR_IRQ_MAX_OFFSET /* 46 */
+
+#ifndef ASM
+
+#include <rtems.h>
+#include <rtems/irq.h>
+#include <rtems/irq-extension.h>
+
+/*
+ * index table for the module specific handlers, a few entries are only placeholders
+ */
+typedef enum {
+  BSP_SIU_IRQ_SMARTCOMM		= BSP_PER_IRQ_LOWEST_OFFSET + 0,
+  BSP_SIU_IRQ_PSC1		= BSP_PER_IRQ_LOWEST_OFFSET + 1,
+  BSP_SIU_IRQ_PSC2		= BSP_PER_IRQ_LOWEST_OFFSET + 2,
+  BSP_SIU_IRQ_PSC3		= BSP_PER_IRQ_LOWEST_OFFSET + 3,
+  BSP_SIU_IRQ_PSC6		= BSP_PER_IRQ_LOWEST_OFFSET + 4,
+  BSP_SIU_IRQ_ETH		= BSP_PER_IRQ_LOWEST_OFFSET + 5,
+  BSP_SIU_IRQ_USB		= BSP_PER_IRQ_LOWEST_OFFSET + 6,
+  BSP_SIU_IRQ_ATA		= BSP_PER_IRQ_LOWEST_OFFSET + 7,
+  BSP_SIU_IRQ_PCI_CRT		= BSP_PER_IRQ_LOWEST_OFFSET + 8,
+  BSP_SIU_IRQ_PCI_SC_RX	        = BSP_PER_IRQ_LOWEST_OFFSET + 9,
+  BSP_SIU_IRQ_PCI_SC_TX	        = BSP_PER_IRQ_LOWEST_OFFSET + 10,
+  BSP_SIU_IRQ_PSC4		= BSP_PER_IRQ_LOWEST_OFFSET + 11,
+  BSP_SIU_IRQ_PSC5		= BSP_PER_IRQ_LOWEST_OFFSET + 12,
+  BSP_SIU_IRQ_SPI_MODF	        = BSP_PER_IRQ_LOWEST_OFFSET + 13,
+  BSP_SIU_IRQ_SPI_SPIF	        = BSP_PER_IRQ_LOWEST_OFFSET + 14,
+  BSP_SIU_IRQ_I2C1		= BSP_PER_IRQ_LOWEST_OFFSET + 15,
+  BSP_SIU_IRQ_I2C2		= BSP_PER_IRQ_LOWEST_OFFSET + 16,
+  BSP_SIU_IRQ_MSCAN1		= BSP_PER_IRQ_LOWEST_OFFSET + 17,
+  BSP_SIU_IRQ_MSCAN2		= BSP_PER_IRQ_LOWEST_OFFSET + 18,
+  BSP_SIU_IRQ_IR_RX		= BSP_PER_IRQ_LOWEST_OFFSET + 19,
+  BSP_SIU_IRQ_IR_TX		= BSP_PER_IRQ_LOWEST_OFFSET + 20,
+  BSP_SIU_IRQ_XLB_ARB		= BSP_PER_IRQ_LOWEST_OFFSET + 21,
+
+  /* SL_TIMER1 -- handler entry only used in case of SMI */
+  BSP_SIU_IRQ_SL_TIMER1	        = BSP_MAIN_IRQ_LOWEST_OFFSET + 0,
+  BSP_SIU_IRQ_IRQ1		= BSP_MAIN_IRQ_LOWEST_OFFSET + 1,
+  BSP_SIU_IRQ_IRQ2		= BSP_MAIN_IRQ_LOWEST_OFFSET + 2,
+  BSP_SIU_IRQ_IRQ3		= BSP_MAIN_IRQ_LOWEST_OFFSET + 3,
+  /* LO_INT --  handler entry never used (only placeholder) */
+  BSP_SIU_IRQ_LO_INT		= BSP_MAIN_IRQ_LOWEST_OFFSET + 4,
+  BSP_SIU_IRQ_RTC_PER		= BSP_MAIN_IRQ_LOWEST_OFFSET + 5,
+  BSP_SIU_IRQ_RTC_STW		= BSP_MAIN_IRQ_LOWEST_OFFSET + 6,
+  BSP_SIU_IRQ_GPIO_STD		= BSP_MAIN_IRQ_LOWEST_OFFSET + 7,
+  BSP_SIU_IRQ_GPIO_WKUP		= BSP_MAIN_IRQ_LOWEST_OFFSET + 8,
+  BSP_SIU_IRQ_TMR0		= BSP_MAIN_IRQ_LOWEST_OFFSET + 9,
+  BSP_SIU_IRQ_TMR1		= BSP_MAIN_IRQ_LOWEST_OFFSET + 10,
+  BSP_SIU_IRQ_TMR2		= BSP_MAIN_IRQ_LOWEST_OFFSET + 1,
+  BSP_SIU_IRQ_TMR3		= BSP_MAIN_IRQ_LOWEST_OFFSET + 12,
+  BSP_SIU_IRQ_TMR4		= BSP_MAIN_IRQ_LOWEST_OFFSET + 13,
+  BSP_SIU_IRQ_TMR5		= BSP_MAIN_IRQ_LOWEST_OFFSET + 14,
+  BSP_SIU_IRQ_TMR6		= BSP_MAIN_IRQ_LOWEST_OFFSET + 15,
+  BSP_SIU_IRQ_TMR7		= BSP_MAIN_IRQ_LOWEST_OFFSET + 16,
+
+  BSP_SIU_IRQ_IRQ0		= BSP_CRIT_IRQ_LOWEST_OFFSET + 0,
+  BSP_SIU_IRQ_SL_TIMER0		= BSP_CRIT_IRQ_LOWEST_OFFSET + 1,
+  /* HI_INT -- handler entry never used (only placeholder) */
+  BSP_SIU_IRQ_HI_INT		= BSP_CRIT_IRQ_LOWEST_OFFSET + 2,
+  BSP_SIU_IRQ_CSS_WKUP		= BSP_CRIT_IRQ_LOWEST_OFFSET + 3,
+
+  BSP_DECREMENTER		= BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 0,
+  BSP_SYSMGMT			= BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1,
+  BSP_EXT                 	= BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2
+} rtems_irq_symbolic_name;
+
+#define BSP_CRIT_IRQ_PRIO_LEVELS	  		  4
+#define BSP_PERIODIC_TIMER                    BSP_SIU_IRQ_TMR6
+
+#endif
+
+#endif /* LIBBSP_POWERPC_GEN5200_IRQ_H */
diff --git a/c/src/lib/libbsp/powerpc/gen5200/include/mscan-base.h b/c/src/lib/libbsp/powerpc/gen5200/include/mscan-base.h
new file mode 100644
index 0000000000..46acb17bab
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/gen5200/include/mscan-base.h
@@ -0,0 +1,266 @@
+/**
+ * @file
+ *
+ * @ingroup m
+ *
+ * @brief MSCAN register definitions and support functions.
+ */
+
+/*
+ * Copyright (c) 2008
+ * Embedded Brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * rtems@embedded-brains.de
+ *
+ * The license and distribution terms for this file may be found in the file
+ * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_MSCAN_BASE_H
+#define LIBBSP_MSCAN_BASE_H
+
+#include <stdbool.h>
+
+#include <bsp/mpc5200.h>
+
+/**
+ * @defgroup m MSCAN
+ *
+ * @{
+ */
+
+#define MSCAN_BIT_RATE_DEFAULT 100000
+
+#define MSCAN_FILTER_NUMBER_MIN 0
+
+#define MSCAN_FILTER_NUMBER_2 2
+
+#define MSCAN_FILTER_NUMBER_4 4
+
+#define MSCAN_FILTER_NUMBER_MAX 8
+
+#define MSCAN_FILTER_ID_DEFAULT 0U
+
+#define MSCAN_FILTER_MASK_DEFAULT 0xffffffffU
+
+#define MSCAN_TRANSMIT_BUFFER_NUMBER 3
+
+/**
+ * @name MSCAN Control Register 0 (CANCTL0)
+ *
+ * @{
+ */
+
+#define CTL0_RXFRM               (1 << 7)
+#define CTL0_RXACT               (1 << 6)
+#define CTL0_CSWAI               (1 << 5)
+#define CTL0_SYNCH               (1 << 4)
+#define CTL0_TIME                (1 << 3)
+#define CTL0_WUPE                (1 << 2)
+#define CTL0_SLPRQ               (1 << 1)
+#define CTL0_INITRQ              (1 << 0)
+
+/** @} */
+
+/**
+ * @name MSCAN Control Register 1 (CANCTL1)
+ *
+ * @{
+ */
+
+#define CTL1_CANE                (1 << 7)
+#define CTL1_CLKSRC              (1 << 6)
+#define CTL1_LOOPB               (1 << 5)
+#define CTL1_LISTEN              (1 << 4)
+#define CTL1_WUPM                (1 << 2)
+#define CTL1_SLPAK               (1 << 1)
+#define CTL1_INITAK              (1 << 0)
+
+/** @} */
+
+/**
+ * @name MSCAN Bus Timing Register 0 (CANBTR0)
+ *
+ * @{
+ */
+
+#define BTR0_SJW(btr0)           ((btr0) << 6)
+#define BTR0_BRP(btr0)           ((btr0) << 0)
+
+/** @} */
+
+/**
+ * @name MSCAN Bus Timing Register 1 (CANBTR1)
+ *
+ * @{
+ */
+
+#define BTR1_SAMP                (1 << 7)
+#define BTR1_TSEG2(btr1)    ((btr1) << 4)
+#define BTR1_TSEG1(btr1)    ((btr1) << 0)
+
+/** @} */
+
+/**
+ * @name MSCAN Receiver Flag Register (CANRFLG)
+ *
+ * @{
+ */
+
+#define RFLG_WUPIF               (1 << 7)
+#define RFLG_CSCIF               (1 << 6)
+#define RFLG_RSTAT_MASK          (3 << 4)
+#define RFLG_RSTAT_OK            (0 << 4)
+#define RFLG_RSTAT_WRN           (1 << 4)
+#define RFLG_RSTAT_ERR           (2 << 4)
+#define RFLG_RSTAT_OFF           (3 << 4)
+#define RFLG_TSTAT_MASK          (3 << 2)
+#define RFLG_TSTAT_OK            (0 << 2)
+#define RFLG_TSTAT_WRN           (1 << 2)
+#define RFLG_TSTAT_ERR           (2 << 2)
+#define RFLG_TSTAT_OFF           (3 << 2)
+#define RFLG_OVRIF               (1 << 1)
+#define RFLG_RXF                 (1 << 0)
+#define RFLG_GET_RX_STATE(rflg)  (((rflg) >> 4) & 0x03)
+#define RFLG_GET_TX_STATE(rflg)  (((rflg) >> 2) & 0x03)
+
+/** @} */
+
+/**
+ * @name MSCAN Receiver Interrupt Enable Register (CANRIER)
+ *
+ * @{
+ */
+
+#define RIER_WUPIE               (1 << 7)
+#define RIER_CSCIE               (1 << 6)
+#define RIER_RSTAT(rier)         ((rier) << 4)
+#define RIER_TSTAT(rier)         ((rier) << 2)
+#define RIER_OVRIE               (1 << 1)
+#define RIER_RXFIE               (1 << 0)
+
+/** @} */
+
+/**
+ * @name MSCAN Transmitter Flag Register (CANTFLG)
+ *
+ * @{
+ */
+
+#define TFLG_TXE2                (1 << 2)
+#define TFLG_TXE1                (1 << 1)
+#define TFLG_TXE0                (1 << 0)
+
+/** @} */
+
+/**
+ * @name MSCAN Transmitter Interrupt Enable Register (CANTIER)
+ *
+ * @{
+ */
+
+#define TIER_TXEI2               (1 << 2)
+#define TIER_TXEI1               (1 << 1)
+#define TIER_TXEI0               (1 << 0)
+
+/** @} */
+
+/**
+ * @name MSCAN Transmitter Message Abort Request (CANTARQ)
+ *
+ * @{
+ */
+
+#define TARQ_ABTRQ2              (1 << 2)
+#define TARQ_ABTRQ1              (1 << 1)
+#define TARQ_ABTRQ0              (1 << 0)
+
+/** @} */
+
+/**
+ * @name MSCAN Transmitter Message Abort Acknoledge (CANTAAK)
+ *
+ * @{
+ */
+
+#define TAAK_ABTRQ2              (1 << 2)
+#define TAAK_ABTRQ1              (1 << 1)
+#define TAAK_ABTRQ0              (1 << 0)
+
+/** @} */
+
+/**
+ * @name MSCAN Transmit Buffer Selection (CANBSEL)
+ *
+ * @{
+ */
+
+#define BSEL_TX2                 (1 << 2)
+#define BSEL_TX1                 (1 << 1)
+#define BSEL_TX0                 (1 << 0)
+
+/** @} */
+
+/**
+ * @name MSCAN ID Acceptance Control Register (CANIDAC)
+ *
+ * @{
+ */
+
+#define IDAC_IDAM1               (1 << 5)
+#define IDAC_IDAM0               (1 << 4)
+#define IDAC_IDAM                (IDAC_IDAM1 | IDAC_IDAM0)
+#define IDAC_IDHIT( idac)        ((idac) & 0x7)
+
+/** @} */
+
+/**
+ * @brief MSCAN registers.
+ */
+typedef struct mpc5200_mscan mscan;
+
+/**
+ * @brief MSCAN context that has to be saved throughout the initialization
+ * mode.
+ */
+typedef struct {
+  uint8_t ctl0;
+  uint8_t rier;
+  uint8_t tier;
+} mscan_context;
+
+void mscan_enable( mscan *m, unsigned bit_rate);
+
+void mscan_disable( mscan *m);
+
+void mscan_interrupts_disable( mscan *m);
+
+void mscan_set_bit_rate( mscan *m, unsigned bit_rate);
+
+void mscan_initialization_mode_enter( mscan *m, mscan_context *context);
+
+void mscan_initialization_mode_leave( mscan *m, const mscan_context *context);
+
+void mscan_sleep_mode_enter( mscan *m);
+
+void mscan_sleep_mode_leave( mscan *m);
+
+uint8_t *mscan_id_acceptance_register( mscan *m, unsigned i);
+
+uint8_t *mscan_id_mask_register( mscan *m, unsigned i);
+
+unsigned mscan_filter_number( mscan *m);
+
+bool mscan_set_filter_number( mscan *m, unsigned number);
+
+bool mscan_filter_operation( mscan *m, bool set, unsigned index, uint32_t *id, uint32_t *mask);
+
+void mscan_filter_clear( mscan *m);
+
+void mscan_get_error_counters( mscan *m, unsigned *rec, unsigned *tec);
+
+/** @} */
+
+#endif /* LIBBSP_MSCAN_BASE_H */