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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2004-11-23 22:20:44 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2004-11-23 22:20:44 +0000 |
| commit | 279eb2c2e06a9803021d8fd752f0de575796f1ae (patch) | |
| tree | bda5bb60ea9027918675ee9fbaa4a3bb7035215f /c/src/lib/libbsp/powerpc/eth_comm/startup/cpuinit.c | |
| parent | Add PR617 as fixed by conversion to new exceptions. (diff) | |
| download | rtems-279eb2c2e06a9803021d8fd752f0de575796f1ae.tar.bz2 | |
2004-11-23 Joel Sherrill <joel@OARcorp.com>
* eth_comm/.cvsignore, eth_comm/ChangeLog, eth_comm/Makefile.am,
eth_comm/README, eth_comm/bsp_specs, eth_comm/configure.ac,
eth_comm/times, eth_comm/canbus/canbus.c, eth_comm/clock/p_clock.c,
eth_comm/console/console.c, eth_comm/include/.cvsignore,
eth_comm/include/8xx_immap.h, eth_comm/include/bsp.h,
eth_comm/include/canbus.h, eth_comm/include/commproc.h,
eth_comm/include/coverhd.h, eth_comm/include/info.h,
eth_comm/include/tm27.h, eth_comm/irq/irq.c, eth_comm/irq/irq.h,
eth_comm/irq/irq_asm.S, eth_comm/irq/irq_init.c,
eth_comm/network/README, eth_comm/network/network.c,
eth_comm/start/start.S, eth_comm/startup/bspstart.c,
eth_comm/startup/cpuinit.c, eth_comm/startup/linkcmds,
eth_comm/startup/mmutlbtab.c, eth_comm/vectors/vectors.S,
eth_comm/vectors/vectors.h, eth_comm/vectors/vectors_init.c,
eth_comm/wrapup/.cvsignore, eth_comm/wrapup/Makefile.am: Removed.
Diffstat (limited to 'c/src/lib/libbsp/powerpc/eth_comm/startup/cpuinit.c')
| -rw-r--r-- | c/src/lib/libbsp/powerpc/eth_comm/startup/cpuinit.c | 44 |
1 files changed, 0 insertions, 44 deletions
diff --git a/c/src/lib/libbsp/powerpc/eth_comm/startup/cpuinit.c b/c/src/lib/libbsp/powerpc/eth_comm/startup/cpuinit.c deleted file mode 100644 index 99355ea11e..0000000000 --- a/c/src/lib/libbsp/powerpc/eth_comm/startup/cpuinit.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * cpuinit.c - this file contains functions for initializing the CPU - * - * Written by Jay Monkman (jmonkman@frasca.com) - * - * $Id$ - */ - -#include <bsp.h> - -/* Macros for handling all the MMU SPRs */ -#define PUT_IC_CST(r) __asm__ volatile ("mtspr 0x230,%0\n" ::"r"(r)) -#define GET_IC_CST(r) __asm__ volatile ("mfspr %0,0x230\n" :"=r"(r)) -#define PUT_DC_CST(r) __asm__ volatile ("mtspr 0x238,%0\n" ::"r"(r)) -#define GET_DC_CST(r) __asm__ volatile ("mfspr %0,0x238\n" :"=r"(r)) - -void cpu_init(void) -{ - register unsigned long t1, t2; - - /* Let's clear MSR[IR] and MSR[DR] */ - t2 = PPC_MSR_IR | PPC_MSR_DR; - __asm__ volatile ( - "mfmsr %0\n" - "andc %0, %0, %1\n" - "mtmsr %0\n" :"=r"(t1), "=r"(t2): - "1"(t2)); - - t1 = M8xx_CACHE_CMD_UNLOCK; - /* PUT_DC_CST(t1); */ - PUT_IC_CST(t1); - - t1 = M8xx_CACHE_CMD_INVALIDATE; - /* PUT_DC_CST(t1); */ - PUT_IC_CST(t1); - - t1 = M8xx_CACHE_CMD_ENABLE; - PUT_IC_CST(t1); - - t1 = M8xx_CACHE_CMD_SFWT; - /* PUT_DC_CST(t1); */ - t1 = M8xx_CACHE_CMD_ENABLE; - /* PUT_DC_CST(t1);*/ -} |