2005-04-28 Jennifer Averett <jennifer.averett@oarcorp.com>

	* acinclude.m4: Initial release of ep1a bsp
	* ep1a/Makefile.am, ep1a/bsp_specs, ep1a/configure.ac,
	ep1a/console/alloc360.c, ep1a/console/console.c,
	ep1a/console/console.h, ep1a/console/init68360.c,
	ep1a/console/m68360.h, ep1a/console/mc68360_scc.c,
	ep1a/console/ns16550cfg.c, ep1a/console/ns16550cfg.h,
	ep1a/console/rsPMCQ1.c, ep1a/console/rsPMCQ1.h, ep1a/include/bsp.h,
	ep1a/irq/irq.c, ep1a/irq/irq_init.c, ep1a/pci/no_host_bridge.c,
	ep1a/start/start.S, ep1a/startup/bspstart.c, ep1a/startup/linkcmds,
	ep1a/vme/vmeconfig.c: New files.

2 files changed, 902 insertions, 0 deletions

diff --git a/c/src/lib/libbsp/powerpc/ep1a/irq/irq.c b/c/src/lib/libbsp/powerpc/ep1a/irq/irq.c
new file mode 100644
index 0000000000..1c83338e6d
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/ep1a/irq/irq.c
@@ -0,0 +1,570 @@
+/*
+ *
+ *  This file contains the implementation of the function described in irq.h
+ *
+ *  COPYRIGHT (c) 1989-1999.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ */
+  
+#include <rtems/system.h>
+#include <bsp.h>
+#include <bsp/irq.h>
+#include <bsp/VME.h>
+#include <bsp/openpic.h>
+#include <rtems/score/thread.h>
+#include <rtems/score/apiext.h>
+#include <libcpu/raw_exception.h>
+#include <libcpu/io.h>
+#include <bsp/vectors.h>
+#include <stdlib.h>
+#include <rtems/bspIo.h> /* for printk */
+#define RAVEN_INTR_ACK_REG 0xfeff0030
+
+/*
+ * pointer to the mask representing the additionnal irq vectors
+ * that must be disabled when a particular entry is activated.
+ * They will be dynamically computed from teh prioruty table given
+ * in BSP_rtems_irq_mngt_set();
+ * CAUTION : this table is accessed directly by interrupt routine
+ * 	     prologue.
+ */
+rtems_i8259_masks 	irq_mask_or_tbl[BSP_IRQ_NUMBER];
+/*
+ * default handler connected on each irq after bsp initialization
+ */
+static rtems_irq_connect_data	default_rtems_entry;
+
+/*
+ * location used to store initial tables used for interrupt
+ * management.
+ */
+static rtems_irq_global_settings* 	internal_config;
+static rtems_irq_connect_data*		rtems_hdl_tbl;
+
+/*
+ * Check if IRQ is an ISA IRQ
+ */
+static inline int is_isa_irq(const rtems_irq_symbolic_name irqLine)
+{
+  return (((int) irqLine <= BSP_ISA_IRQ_MAX_OFFSET) &
+	  ((int) irqLine >= BSP_ISA_IRQ_LOWEST_OFFSET)
+	 );
+}
+
+/*
+ * Check if IRQ is an OPENPIC IRQ
+ */
+static inline int is_pci_irq(const rtems_irq_symbolic_name irqLine)
+{
+  return (((int) irqLine <= BSP_PCI_IRQ_MAX_OFFSET) &
+	  ((int) irqLine >= BSP_PCI_IRQ_LOWEST_OFFSET)
+	 );
+}
+
+/*
+ * Check if IRQ is a Porcessor IRQ
+ */
+static inline int is_processor_irq(const rtems_irq_symbolic_name irqLine)
+{
+  return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) &
+	  ((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
+	 );
+}
+
+
+/*
+ * ------------------------ RTEMS Irq helper functions ----------------
+ */
+ 
+/*
+ * Caution : this function assumes the variable "internal_config"
+ * is already set and that the tables it contains are still valid
+ * and accessible.
+ */
+static void compute_i8259_masks_from_prio ()
+{
+  int i;
+  int j;
+  /*
+   * Always mask at least current interrupt to prevent re-entrance
+   */
+  for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) {
+    * ((unsigned short*) &irq_mask_or_tbl[i]) = (1 << i);
+    for (j = BSP_ISA_IRQ_LOWEST_OFFSET; j < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; j++) {
+      /*
+       * Mask interrupts at i8259 level that have a lower priority
+       */
+      if (internal_config->irqPrioTbl [i] > internal_config->irqPrioTbl [j]) {
+	* ((unsigned short*) &irq_mask_or_tbl[i]) |= (1 << j);
+      }
+    }
+  }
+}
+
+/*
+ * This function check that the value given for the irq line
+ * is valid.
+ */
+
+static int isValidInterrupt(int irq)
+{
+  if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET))
+    return 0;
+  return 1;
+}
+
+
+/*
+ * ------------------------ RTEMS Shared Irq Handler Mngt Routines ----------------
+ */
+int BSP_install_rtems_shared_irq_handler  (const rtems_irq_connect_data* irq)
+{
+    unsigned int level;
+    rtems_irq_connect_data* vchain;
+
+    if (!isValidInterrupt(irq->name)) {
+      printk("Invalid interrupt vector %d\n",irq->name);
+      return 0;
+    }
+    printk("Install Shared interrupt %d\n", irq->name);
+
+    _CPU_ISR_Disable(level);
+
+    if ( (int)rtems_hdl_tbl[irq->name].next_handler  == -1 ) {
+      _CPU_ISR_Enable(level);
+      printk("IRQ vector %d already connected to an unshared handler\n",irq->name);
+      return 0;
+    }
+
+     vchain = (rtems_irq_connect_data*)malloc(sizeof(rtems_irq_connect_data));
+
+    /* save off topmost handler */
+    vchain[0]= rtems_hdl_tbl[irq->name];
+    
+    /*
+     * store the data provided by user
+     */
+    rtems_hdl_tbl[irq->name] = *irq;
+
+    /* link chain to new topmost handler */
+    rtems_hdl_tbl[irq->name].next_handler = (void *)vchain;
+
+    
+    if (is_isa_irq(irq->name)) {
+      /*
+       * Enable interrupt at PIC level
+       */
+      BSP_irq_enable_at_i8259s (irq->name);
+    }
+    
+    if (is_pci_irq(irq->name)) {
+      /*
+       * Enable interrupt at OPENPIC level
+       */
+      printk(" openpic_enable_irq %d\n", (int)irq->name );
+      openpic_enable_irq ((int) irq->name );  /* - BSP_PCI_IRQ_LOWEST_OFFSET); */
+    }
+
+    if (is_processor_irq(irq->name)) {
+      /*
+       * Enable exception at processor level
+       */
+    }
+    /*
+     * Enable interrupt on device
+     */
+    irq->on(irq);
+    
+    _CPU_ISR_Enable(level);
+
+    return 1;
+}
+
+
+/*
+ * ------------------------ RTEMS Single Irq Handler Mngt Routines ----------------
+ */
+
+int BSP_install_rtems_irq_handler  (const rtems_irq_connect_data* irq)
+{
+    unsigned int level;
+
+    if (!isValidInterrupt(irq->name)) {
+      printk("Invalid interrupt vector %d\n",irq->name);
+      return 0;
+    }
+    /*
+     * Check if default handler is actually connected. If not issue an error.
+     * You must first get the current handler via i386_get_current_idt_entry
+     * and then disconnect it using i386_delete_idt_entry.
+     * RATIONALE : to always have the same transition by forcing the user
+     * to get the previous handler before accepting to disconnect.
+     */
+    _CPU_ISR_Disable(level);
+    if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) {
+      _CPU_ISR_Enable(level);
+      printk("IRQ vector %d already connected\n",irq->name);
+      return 0;
+    }
+
+    /*
+     * store the data provided by user
+     */
+    rtems_hdl_tbl[irq->name] = *irq;
+    rtems_hdl_tbl[irq->name].next_handler = (void *)-1;
+    
+    if (is_isa_irq(irq->name)) {
+      /*
+       * Enable interrupt at PIC level
+       */
+      BSP_irq_enable_at_i8259s (irq->name);
+    }
+    
+    if (is_pci_irq(irq->name)) {
+      /*
+       * Enable interrupt at OPENPIC level
+       */
+      openpic_enable_irq ((int) irq->name ); /* - BSP_PCI_IRQ_LOWEST_OFFSET); */
+    }
+
+    if (is_processor_irq(irq->name)) {
+      /*
+       * Enable exception at processor level
+       */
+    }
+    /*
+     * Enable interrupt on device
+     */
+    irq->on(irq);
+    
+    _CPU_ISR_Enable(level);
+
+    return 1;
+}
+
+
+int BSP_get_current_rtems_irq_handler	(rtems_irq_connect_data* irq)
+{
+     unsigned int level;
+
+     if (!isValidInterrupt(irq->name)) {
+      return 0;
+     }
+     _CPU_ISR_Disable(level);
+     *irq = rtems_hdl_tbl[irq->name];
+     _CPU_ISR_Enable(level);
+     return 1;
+}
+
+int BSP_remove_rtems_irq_handler  (const rtems_irq_connect_data* irq)
+{
+   rtems_irq_connect_data *pchain= NULL, *vchain = NULL;
+    unsigned int level;
+  
+    if (!isValidInterrupt(irq->name)) {
+      return 0;
+    }
+    /*
+     * Check if default handler is actually connected. If not issue an error.
+     * You must first get the current handler via i386_get_current_idt_entry
+     * and then disconnect it using i386_delete_idt_entry.
+     * RATIONALE : to always have the same transition by forcing the user
+     * to get the previous handler before accepting to disconnect.
+     */
+    _CPU_ISR_Disable(level);
+    if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) {
+      _CPU_ISR_Enable(level);
+      return 0;
+    }
+
+    if( (int)rtems_hdl_tbl[irq->name].next_handler != -1 )
+    {
+       int found = 0;
+
+       for( (pchain= NULL, vchain = &rtems_hdl_tbl[irq->name]);
+            (vchain->hdl != default_rtems_entry.hdl);
+            (pchain= vchain, vchain = (rtems_irq_connect_data*)vchain->next_handler) )
+       {
+          if( vchain->hdl == irq->hdl )
+          {
+             found= -1; break;
+          }
+       }
+
+       if( !found )
+       {
+          _CPU_ISR_Enable(level);
+          return 0;
+       }
+    }
+    else
+    {
+       if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) 
+       {
+          _CPU_ISR_Enable(level);
+         return 0;
+       }
+    }
+
+    if (is_isa_irq(irq->name)) {
+      /*
+       * disable interrupt at PIC level
+       */
+      BSP_irq_disable_at_i8259s (irq->name);
+    }
+    if (is_pci_irq(irq->name)) {
+      /*
+       * disable interrupt at OPENPIC level
+       */
+      openpic_disable_irq ((int) irq->name );  
+    }
+    if (is_processor_irq(irq->name)) {
+      /*
+       * disable exception at processor level
+       */
+    }    
+
+    /*
+     * Disable interrupt on device
+     */
+    irq->off(irq);
+
+    /*
+     * restore the default irq value
+     */
+    if( !vchain )
+    {
+       /* single handler vector... */
+       rtems_hdl_tbl[irq->name] = default_rtems_entry;
+    }
+    else
+    {
+       if( pchain )
+       {
+          /* non-first handler being removed */
+          pchain->next_handler = vchain->next_handler;
+       }
+       else
+       {
+          /* first handler isn't malloc'ed, so just overwrite it.  Since
+          the contents of vchain are being struct copied, vchain itself
+          goes away */
+          rtems_hdl_tbl[irq->name]= *vchain;
+       }
+       free(vchain);
+    }
+
+    _CPU_ISR_Enable(level);
+
+    return 1;
+}
+
+/*
+ * ------------------------ RTEMS Global Irq Handler Mngt Routines ----------------
+ */
+
+int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
+{
+    int i;
+    unsigned int level;
+   /*
+    * Store various code accelerators
+    */
+    internal_config 		= config;
+    default_rtems_entry 	= config->defaultEntry;
+    rtems_hdl_tbl 		= config->irqHdlTbl;
+    return 1;  
+
+    _CPU_ISR_Disable(level);
+    /*
+     * set up internal tables used by rtems interrupt prologue
+     */
+    for (i=BSP_PCI_IRQ_LOWEST_OFFSET; i < BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER ; i++) {
+      /*
+       * Note that openpic_set_priority() sets the TASK priority of the PIC
+       */
+      openpic_set_source_priority(i, internal_config->irqPrioTbl[i]);
+      if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
+         openpic_enable_irq ((int) i); 
+         {
+            rtems_irq_connect_data* vchain;
+            for( vchain = &rtems_hdl_tbl[i];
+                 ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); 
+                 vchain = (rtems_irq_connect_data*)vchain->next_handler )
+            {
+               vchain->on(vchain);
+            }
+         }
+
+      }
+      else {
+         /* rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); */
+         {
+            rtems_irq_connect_data* vchain;
+            for( vchain = &rtems_hdl_tbl[i];
+                 ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); 
+                 vchain = (rtems_irq_connect_data*)vchain->next_handler )
+            {
+               vchain->off(vchain);
+            }
+         }
+         
+         openpic_disable_irq ((int) i ); 
+      }
+    }
+    /*
+     * Must enable PCI/ISA bridge IRQ
+     */
+    openpic_enable_irq (0);
+    /*
+     * finish with Processor exceptions handled like IRQ
+     */
+    for (i=BSP_PROCESSOR_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER; i++) {
+      if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
+         /* rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); */
+         {
+            rtems_irq_connect_data* vchain;
+            for( vchain = &rtems_hdl_tbl[i];
+                 ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); 
+                 vchain = (rtems_irq_connect_data*)vchain->next_handler )
+            {
+               vchain->on(vchain);
+            }
+         }
+
+      }
+      else {
+         /* rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); */
+         {
+            rtems_irq_connect_data* vchain;
+            for( vchain = &rtems_hdl_tbl[i];
+                 ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); 
+                 vchain = (rtems_irq_connect_data*)vchain->next_handler )
+            {
+               vchain->off(vchain);
+            }
+         }
+
+      }
+    }
+    _CPU_ISR_Enable(level);
+    return 1;
+}
+
+int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config)
+{
+    *config = internal_config;
+    return 0;
+}    
+
+int _BSP_vme_bridge_irq = -1;
+ 
+unsigned BSP_spuriousIntr = 0;
+/*
+ * High level IRQ handler called from shared_raw_irq_code_entry
+ */
+void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
+{
+  register unsigned int irq;
+  register unsigned isaIntr;                  /* boolean */
+  register unsigned oldMask = 0;	      /* old isa pic masks */
+  register unsigned newMask;                  /* new isa pic masks */
+  register unsigned msr;
+  register unsigned new_msr;
+
+  if (excNum == ASM_DEC_VECTOR) {
+    _CPU_MSR_GET(msr);
+    new_msr = msr | MSR_EE;
+    _CPU_MSR_SET(new_msr);
+    
+    rtems_hdl_tbl[BSP_DECREMENTER].hdl( rtems_hdl_tbl[BSP_DECREMENTER].handle );
+
+    _CPU_MSR_SET(msr);
+    return;
+    
+  }
+
+  irq = openpic_irq(0);
+
+  if (irq == OPENPIC_VEC_SPURIOUS) {
+    ++BSP_spuriousIntr;
+   return;
+  }
+
+  isaIntr = (irq == BSP_PCI_ISA_BRIDGE_IRQ);
+  if (isaIntr)  {
+    /*
+     * Acknowledge and read 8259 vector
+     */
+    irq = (unsigned int) (*(unsigned char *) RAVEN_INTR_ACK_REG);
+    /*
+     * store current PIC mask
+     */
+    oldMask = i8259s_cache;
+    newMask = oldMask | irq_mask_or_tbl [irq];
+    i8259s_cache = newMask;
+    outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff);
+    outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
+    BSP_irq_ack_at_i8259s (irq);
+    openpic_eoi(0);
+  }
+
+  _CPU_MSR_GET(msr);
+  new_msr = msr | MSR_EE;
+  _CPU_MSR_SET(new_msr);
+
+  {
+     rtems_irq_connect_data* vchain;
+     irq -= 16;    /* Correct the vector for the 8240 */  
+     for( vchain = &rtems_hdl_tbl[irq];
+          ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl);
+          vchain = (rtems_irq_connect_data*)vchain->next_handler )
+     {
+        vchain->hdl( vchain->handle );
+     }
+  }
+  _CPU_MSR_SET(msr);
+
+  if (isaIntr)  {
+    i8259s_cache = oldMask;
+    outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff);
+    outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
+  }
+  else {
+#ifdef BSP_PCI_VME_DRIVER_DOES_EOI
+	/* leave it to the VME bridge driver to do EOI, so
+     * it can re-enable the openpic while handling
+     * VME interrupts (-> VME priorities in software)
+	 */
+	if (_BSP_vme_bridge_irq != irq)
+#endif
+    		openpic_eoi(0);
+  }
+}
+    
+    
+  
+void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx)
+{
+  /*
+   * Process pending signals that have not already been
+   * processed by _Thread_Displatch. This happens quite
+   * unfrequently : the ISR must have posted an action
+   * to the current running thread.
+   */
+  if ( _Thread_Do_post_task_switch_extension ||
+       _Thread_Executing->do_post_task_switch_extension ) {
+    _Thread_Executing->do_post_task_switch_extension = FALSE;
+    _API_extensions_Run_postswitch();
+  }
+  /*
+   * I plan to process other thread related events here.
+   * This will include DEBUG session requested from keyboard...
+   */
+}
diff --git a/c/src/lib/libbsp/powerpc/ep1a/irq/irq_init.c b/c/src/lib/libbsp/powerpc/ep1a/irq/irq_init.c
new file mode 100644
index 0000000000..5ef8467619
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/ep1a/irq/irq_init.c
@@ -0,0 +1,332 @@
+/* irq_init.c
+ *
+ *  This file contains the implementation of rtems initialization
+ *  related to interrupt handling.
+ *
+ *  CopyRight (C) 1999 valette@crf.canon.fr
+ *
+ * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com>
+ * to make it valid for MVME2300 Motorola boards.
+ *
+ * Till Straumann <strauman@slac.stanford.edu>, 12/20/2001:
+ * Use the new interface to openpic_init
+ *
+ *  COPYRIGHT (c) 1989-1999.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ */
+
+#include <libcpu/io.h>
+#include <libcpu/spr.h>
+#include <bsp/pci.h>
+#include <bsp/residual.h>
+#include <bsp/openpic.h>
+#include <bsp/irq.h>
+#include <bsp.h>
+#include <libcpu/raw_exception.h>
+#include <bsp/motorola.h>
+#include <rtems/bspIo.h>
+
+/*
+#define SHOW_ISA_PCI_BRIDGE_SETTINGS
+*/
+
+typedef struct {
+  unsigned char bus;	/* few chance the PCI/ISA bridge is not on first bus but ... */
+  unsigned char device;
+  unsigned char function;
+} pci_isa_bridge_device;
+
+pci_isa_bridge_device* via_82c586 = 0;
+static pci_isa_bridge_device bridge;
+
+extern unsigned int external_exception_vector_prolog_code_size[];
+extern void external_exception_vector_prolog_code();
+extern unsigned int decrementer_exception_vector_prolog_code_size[];
+extern void decrementer_exception_vector_prolog_code();
+
+/*
+ * default on/off function
+ */
+static void nop_func(){}
+/*
+ * default isOn function
+ */
+static int not_connected() {return 0;}
+/*
+ * default possible isOn function
+ */
+static int connected() {return 1;}
+
+static rtems_irq_connect_data     	rtemsIrq[BSP_IRQ_NUMBER];
+static rtems_irq_global_settings     	initial_config;
+static rtems_irq_connect_data     	defaultIrq = {
+  /* vectorIdex,	 hdl		, handle	, on		, off		, isOn */
+  0, 			 nop_func	, NULL		, nop_func	, nop_func	, not_connected
+};
+static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={
+  /*
+   * actual rpiorities for interrupt :
+   *	0   means that only current interrupt is masked
+   *	255 means all other interrupts are masked
+   */
+  /*
+   * ISA interrupts.
+   * The second entry has a priority of 255 because
+   * it is the slave pic entry and is should always remain
+   * unmasked.
+   */
+  0,0,
+  255,
+  0, 0, 0, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
+  /*
+   * PCI Interrupts
+   */
+  8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, /* for raven prio 0 means unactive... */
+  /*
+   * Processor exceptions handled as interrupts
+   */
+  0
+};
+
+static unsigned char mcp750_openpic_initpolarities[] = {
+    1,  /*  0 8259 cascade */
+    0,	/*  1 all the rest of them */
+    0,  /*  2 all the rest of them */
+    0,  /*  3 all the rest of them */
+    0,  /*  4 all the rest of them */
+    0,  /*  5 all the rest of them */
+    0,  /*  6 all the rest of them */
+    0,  /*  7 all the rest of them */
+    0,  /*  8 all the rest of them */
+    0,  /*  9 all the rest of them */
+    0,  /* 10 all the rest of them */
+    0,  /* 11 all the rest of them */
+    0,  /* 12 all the rest of them */
+    0,  /* 13 all the rest of them */
+    0,  /* 14 all the rest of them */
+    0,  /* 15 all the rest of them */
+    0,  /* 16 all the rest of them */
+    0,  /* 17 all the rest of them */
+    1,  /* 18 all the rest of them */
+    1,  /* 19 all the rest of them */
+    1,  /* 20 all the rest of them */
+    1,  /* 21 all the rest of them */
+    1,  /* 22 all the rest of them */
+    1,  /* 23 all the rest of them */
+    1,  /* 24 all the rest of them */
+    1,  /* 25 all the rest of them */
+};
+
+static unsigned char mcp750_openpic_initsenses[] = {
+    1,	/* 0 MCP750_INT_PCB(8259) */
+    0,	/* 1 MCP750_INT_FALCON_ECC_ERR */
+    1,	/* 2 MCP750_INT_PCI_ETHERNET */
+    1,	/* 3 MCP750_INT_PCI_PMC */
+    1,	/* 4 MCP750_INT_PCI_WATCHDOG_TIMER1 */
+    1,	/* 5 MCP750_INT_PCI_PRST_SIGNAL */
+    1,	/* 6 MCP750_INT_PCI_FALL_SIGNAL */
+    1,	/* 7 MCP750_INT_PCI_DEG_SIGNAL */
+    1,	/* 8 MCP750_INT_PCI_BUS1_INTA */
+    1,	/* 9 MCP750_INT_PCI_BUS1_INTB */
+    1,	/*10 MCP750_INT_PCI_BUS1_INTC */
+    1,	/*11 MCP750_INT_PCI_BUS1_INTD */
+    1,	/*12 MCP750_INT_PCI_BUS2_INTA */
+    1,	/*13 MCP750_INT_PCI_BUS2_INTB */
+    1,	/*14 MCP750_INT_PCI_BUS2_INTC */
+    1,	/*15 MCP750_INT_PCI_BUS2_INTD */
+    1,
+    1, 
+    1,
+    1,
+    1,
+    1,
+    1,
+    1,
+    1,
+    1
+};
+
+void VIA_isa_bridge_interrupts_setup(void)
+{
+  pci_isa_bridge_device pci_dev;
+  unsigned int temp;
+  unsigned char tmp;
+  unsigned char maxBus;
+  unsigned found = 0;
+
+  maxBus = BusCountPCI();
+  pci_dev.function 	= 0; /* Assumes the bidge is the first function */
+     
+  for (pci_dev.bus = 0; pci_dev.bus < maxBus; pci_dev.bus++) {
+#ifdef SCAN_PCI_PRINT       
+    printk("isa_bridge_interrupts_setup: Scanning bus %d\n", pci_dev.bus);
+#endif       
+    for (pci_dev.device = 0; pci_dev.device < PCI_MAX_DEVICES; pci_dev.device++) {
+#ifdef SCAN_PCI_PRINT       
+      printk("isa_bridge_interrupts_setup: Scanning device %d\n", pci_dev.device);
+#endif       
+      pci_read_config_dword(pci_dev.bus, pci_dev.device,  pci_dev.function,
+			       PCI_VENDOR_ID, &temp);
+#ifdef SCAN_PCI_PRINT       
+      printk("Vendor/device = %x\n", temp);
+#endif
+      if ((temp == (((unsigned short) PCI_VENDOR_ID_VIA) | (PCI_DEVICE_ID_VIA_82C586_0 << 16)))
+	 ) {
+	bridge = pci_dev;
+	via_82c586 = &bridge;
+#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS	
+	/*
+	 * Should print : bus = 0, device = 11, function = 0 on a MCP750.
+	 */
+	printk("Via PCI/ISA bridge found at bus = %d, device = %d, function = %d\n",
+	       via_82c586->bus,
+	       via_82c586->device,
+	       via_82c586->function);
+#endif       
+	found = 1;
+	goto loop_exit;
+	   
+      }
+    }
+  }
+loop_exit:
+  if (!found) BSP_panic("VIA_82C586 PCI/ISA bridge not found!n");
+     
+  tmp = inb(0x810);
+  if  ( !(tmp & 0x2)) {
+#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS	
+    printk("This is a second generation MCP750 board\n");
+    printk("We must reprogram the PCI/ISA bridge...\n");
+#endif       
+    pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
+			 0x47,  &tmp);
+#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS	
+    printk(" PCI ISA bridge control2 = %x\n", (unsigned) tmp);
+#endif       
+    /*
+     * Enable 4D0/4D1 ISA interrupt level/edge config registers
+     */
+    tmp |= 0x20;
+    pci_write_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
+			  0x47, tmp);
+    /*
+     * Now program the ISA interrupt edge/level
+     */
+    tmp = ELCRS_INT9_LVL | ELCRS_INT10_LVL | ELCRS_INT11_LVL;
+    outb(tmp, ISA8259_S_ELCR);
+    tmp = ELCRM_INT5_LVL;
+    outb(tmp, ISA8259_M_ELCR);;
+    /*
+     * Set the Interrupt inputs to non-inverting level interrupt
+     */
+    pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
+			    0x54, &tmp);
+#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS	
+    printk(" PCI ISA bridge PCI/IRQ Edge/Level Select = %x\n", (unsigned) tmp);
+#endif       
+    tmp = 0;
+    pci_write_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
+			  0x54, tmp);
+  }
+  else {
+#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS	
+    printk("This is a first generation MCP750 board\n");
+    printk("We just show the actual value used by PCI/ISA bridge\n");
+#endif       
+    pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
+			 0x47,  &tmp);
+#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS	
+    printk(" PCI ISA bridge control2 = %x\n", (unsigned) tmp);
+#endif       
+    /*
+     * Show the Interrupt inputs inverting/non-inverting level status
+     */
+    pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
+			 0x54, &tmp);
+#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS	
+    printk(" PCI ISA bridge PCI/IRQ Edge/Level Select = %x\n", (unsigned) tmp);
+#endif       
+  }
+}
+
+  /*
+   * This code assumes the exceptions management setup has already
+   * been done. We just need to replace the exceptions that will
+   * be handled like interrupt. On mcp750/mpc750 and many PPC processors
+   * this means the decrementer exception and the external exception.
+   */
+void BSP_rtems_irq_mng_init(unsigned cpuId)
+{
+  rtems_raw_except_connect_data vectorDesc;
+  int i;
+
+  /*
+   * First initialize the Interrupt management hardware
+   */
+#ifdef TRACE_IRQ_INIT  
+  printk("Going to initialize openpic compliant device\n");
+#endif       
+  openpic_init(1, mcp750_openpic_initpolarities, mcp750_openpic_initsenses);
+
+#ifdef TRACE_IRQ_INIT  
+  printk("Going to initialize the PCI/ISA bridge IRQ related setting (VIA 82C586)\n");
+#endif
+
+  /*
+   * Initialize Rtems management interrupt table
+   */
+    /*
+     * re-init the rtemsIrq table
+     */
+    for (i = 0; i < BSP_IRQ_NUMBER; i++) {
+      rtemsIrq[i]      = defaultIrq;
+      rtemsIrq[i].name = i;
+    }
+    /*
+     * Init initial Interrupt management config
+     */
+    initial_config.irqNb 	= BSP_IRQ_NUMBER;
+    initial_config.defaultEntry = defaultIrq;
+    initial_config.irqHdlTbl	= rtemsIrq;
+    initial_config.irqBase	= BSP_ASM_IRQ_VECTOR_BASE;
+    initial_config.irqPrioTbl	= irqPrioTable;
+
+    if (!BSP_rtems_irq_mngt_set(&initial_config)) {
+      /*
+       * put something here that will show the failure...
+       */
+      BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n");
+    }
+  
+  /*
+   * We must connect the raw irq handler for the two
+   * expected interrupt sources : decrementer and external interrupts.
+   */
+    vectorDesc.exceptIndex 	=	ASM_DEC_VECTOR;
+    vectorDesc.hdl.vector	=	ASM_DEC_VECTOR;
+    vectorDesc.hdl.raw_hdl	=	decrementer_exception_vector_prolog_code;
+    vectorDesc.hdl.raw_hdl_size	=	(unsigned) decrementer_exception_vector_prolog_code_size;
+    vectorDesc.on		=	nop_func;
+    vectorDesc.off		=	nop_func;
+    vectorDesc.isOn		=	connected;
+    if (!mpc60x_set_exception (&vectorDesc)) {
+      BSP_panic("Unable to initialize RTEMS decrementer raw exception\n");
+    }
+    vectorDesc.exceptIndex	=	ASM_EXT_VECTOR;
+    vectorDesc.hdl.vector	=	ASM_EXT_VECTOR;
+    vectorDesc.hdl.raw_hdl	=	external_exception_vector_prolog_code;
+    vectorDesc.hdl.raw_hdl_size	=	(unsigned) external_exception_vector_prolog_code_size;
+    if (!mpc60x_set_exception (&vectorDesc)) {
+      BSP_panic("Unable to initialize RTEMS external raw exception\n");
+    }
+#ifdef TRACE_IRQ_INIT  
+    printk("RTEMS IRQ management is now operationnal\n");
+#endif
+}
+