diff options
| author | Hesham ALMatary <heshamelmatary@gmail.com> | 2015-04-14 10:22:35 -0500 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@oarcorp.com> | 2015-04-14 11:10:14 -0500 |
| commit | 0a73de2fc802e183affed8b2f6835e29f5c89b4d (patch) | |
| tree | 323b6b3e3211c8fb2fedbf7ebc2d402bba85fda0 /c/src/lib/libbsp/or1k/or1ksim/console/uart.c | |
| parent | score: Rename _Watchdog_Reset() (diff) | |
| download | rtems-0a73de2fc802e183affed8b2f6835e29f5c89b4d.tar.bz2 | |
or1ksim: Fix bug at UART driver.
Fix some UART register addresses and implementation bugs that
were causing malfunction of console driver on real hardware.
hello and ticker samples are tested and working fine now on mor1kx
based SoC on Atlys FPGA board.
BSP_OR1K_OR1KSIM_PERIPHCLK has been changed to 50MHz as with mor1kx/atlys
SoC; this change has no effect on the current simulators that RTEMS run
on.
Diffstat (limited to 'c/src/lib/libbsp/or1k/or1ksim/console/uart.c')
| -rw-r--r-- | c/src/lib/libbsp/or1k/or1ksim/console/uart.c | 35 |
1 files changed, 11 insertions, 24 deletions
diff --git a/c/src/lib/libbsp/or1k/or1ksim/console/uart.c b/c/src/lib/libbsp/or1k/or1ksim/console/uart.c index bb86bae251..87b1aeaa07 100644 --- a/c/src/lib/libbsp/or1k/or1ksim/console/uart.c +++ b/c/src/lib/libbsp/or1k/or1ksim/console/uart.c @@ -46,39 +46,34 @@ static uint32_t uart_get_baud(const console_tbl *ct) static void uart_set_baud(int baud) { - int divisor = (OR1KSIM_BSP_CLOCK_FREQ) / (16 * baud); - OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_CTRL) |= + uint16_t divisor = (OR1KSIM_BSP_CLOCK_FREQ) / (16 * baud); + OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_CTRL) = OR1KSIM_BSP_UART_REG_LINE_CTRL_DLAB; OR1KSIM_REG(OR1KSIM_BSP_UART_REG_DEV_LATCH_LOW) = divisor & 0xff; OR1KSIM_REG(OR1KSIM_BSP_UART_REG_DEV_LATCH_HIGH) = - (divisor >> 8) & 0xff; - - OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_CTRL) &= - ~(OR1KSIM_BSP_UART_REG_LINE_CTRL_DLAB); + (divisor >> 8); } static void uart_initialize(int minor) { - /* Disable all interrupts */ - OR1KSIM_REG(OR1KSIM_BSP_UART_REG_INT_ENABLE) = 0x00; + /* Set baud rate */ + uart_set_baud(OR1KSIM_UART_DEFAULT_BAUD); + + /* Set data pattern configuration */ + OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_CTRL) = + OR1KSIM_BSP_UART_REG_LINE_CTRL_WLEN8; /* Reset receiver and transmitter */ OR1KSIM_REG(OR1KSIM_BSP_UART_REG_FIFO_CTRL) = OR1KSIM_BSP_UART_REG_FIFO_CTRL_ENABLE_FIFO | OR1KSIM_BSP_UART_REG_FIFO_CTRL_CLEAR_RCVR | - OR1KSIM_BSP_UART_REG_FIFO_CTRL_CLEAR_XMIT | OR1KSIM_BSP_UART_REG_FIFO_CTRL_TRIGGER_14; - /* Set data pattern configuration */ - OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_CTRL) = - OR1KSIM_BSP_UART_REG_LINE_CTRL_WLEN8 & - (OR1KSIM_BSP_UART_REG_LINE_CTRL_STOP | - OR1KSIM_BSP_UART_REG_LINE_CTRL_PARITY); + /* Disable all interrupts */ + OR1KSIM_REG(OR1KSIM_BSP_UART_REG_INT_ENABLE) = 0x00; - /* Set baud rate */ - uart_set_baud(OR1KSIM_UART_DEFAULT_BAUD); } static int uart_first_open(int major, int minor, void *arg) @@ -115,9 +110,6 @@ static int uart_read_polled(int minor) static void uart_write_polled(int minor, char c) { unsigned char lsr; - const uint32_t transmit_finished = - (OR1KSIM_BSP_UART_REG_LINE_STATUS_TEMT | - OR1KSIM_BSP_UART_REG_LINE_STATUS_THRE); /* Wait until there is no pending data in the transmitter FIFO (empty) */ do { @@ -125,11 +117,6 @@ static void uart_write_polled(int minor, char c) } while (!(lsr & OR1KSIM_BSP_UART_REG_LINE_STATUS_THRE)); OR1KSIM_REG(OR1KSIM_BSP_UART_REG_TX) = c; - - /* Wait until trasmit data is finished */ - do { - lsr = OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_STATUS); - } while ( (lsr & transmit_finished) != transmit_finished ); } static ssize_t uart_write( |