Whitespace removal.

author: Ralf Corsepius <ralf.corsepius@rtems.org> 2009-11-29 15:27:07 +0000
committer: Ralf Corsepius <ralf.corsepius@rtems.org> 2009-11-29 15:27:07 +0000
commit: efdfd48add0e7f5549ce99a3cabf6aed9f170230 (patch)
tree: 396c3c8ae3a969c7fe1b1d3f334e4b2bc442ff37 /c/src/lib/libbsp/mips
parent: Whitespace removal. (diff)
download: rtems-efdfd48add0e7f5549ce99a3cabf6aed9f170230.tar.bz2
28 files changed, 414 insertions, 414 deletions
diff --git a/c/src/lib/libbsp/mips/csb350/clock/clockdrv.c b/c/src/lib/libbsp/mips/csb350/clock/clockdrv.c
index e2b97c555a..393c1d7638 100644
--- a/c/src/lib/libbsp/mips/csb350/clock/clockdrv.c
+++ b/c/src/lib/libbsp/mips/csb350/clock/clockdrv.c
@@ -5,7 +5,7 @@
  *
  *  Copyright (c) 2005 by Cogent Computer Systems
  *  Written by Jay Monkman <jtm@lopingdog.com>
- *	
+ *
  *  The license and distribution terms for this file may be
  *  found in found in the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
@@ -46,27 +46,27 @@ uint32_t last_match;
 void au1x00_clock_init(void)
 {
     uint32_t wakemask;
-    /* Clear the trim register */ 
-    AU1X00_SYS_TOYTRIM(AU1X00_SYS_ADDR) = 0; 
-    
-    /* Clear the TOY counter */ 
-    while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TS); 
-    AU1X00_SYS_TOYWRITE(AU1X00_SYS_ADDR) = 0; 
-    while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TS); 
-    
-    wakemask = AU1X00_SYS_WAKEMSK(AU1X00_SYS_ADDR); 
+    /* Clear the trim register */
+    AU1X00_SYS_TOYTRIM(AU1X00_SYS_ADDR) = 0;
+
+    /* Clear the TOY counter */
+    while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TS);
+    AU1X00_SYS_TOYWRITE(AU1X00_SYS_ADDR) = 0;
+    while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TS);
+
+    wakemask = AU1X00_SYS_WAKEMSK(AU1X00_SYS_ADDR);
     wakemask |= AU1X00_SYS_WAKEMSK_M20;
-    AU1X00_SYS_WAKEMSK(AU1X00_SYS_ADDR) = wakemask; 
+    AU1X00_SYS_WAKEMSK(AU1X00_SYS_ADDR) = wakemask;
     AU1X00_IC_WAKESET(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2;
-    
-    tick_interval = 32768 * rtems_configuration_get_microseconds_per_tick(); 
-    tick_interval = tick_interval / 1000000; 
-    printk("tick_interval = %d\n", tick_interval); 
-    
-    last_match = AU1X00_SYS_TOYREAD(AU1X00_SYS_ADDR); 
-    AU1X00_SYS_TOYMATCH2(AU1X00_SYS_ADDR) = last_match + (50*tick_interval); 
+
+    tick_interval = 32768 * rtems_configuration_get_microseconds_per_tick();
+    tick_interval = tick_interval / 1000000;
+    printk("tick_interval = %d\n", tick_interval);
+
+    last_match = AU1X00_SYS_TOYREAD(AU1X00_SYS_ADDR);
+    AU1X00_SYS_TOYMATCH2(AU1X00_SYS_ADDR) = last_match + (50*tick_interval);
     AU1X00_IC_MASKSET(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2;
-    while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TM0); 
+    while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TM0);
 }
 
 #define Clock_driver_support_initialize_hardware() \
@@ -74,7 +74,7 @@ void au1x00_clock_init(void)
      au1x00_clock_init(); \
   } while(0)
 
-                  
+
 
 #define Clock_driver_support_shutdown_hardware()
 
diff --git a/c/src/lib/libbsp/mips/csb350/console/console-io.c b/c/src/lib/libbsp/mips/csb350/console/console-io.c
index f604203db2..94d82acdc2 100644
--- a/c/src/lib/libbsp/mips/csb350/console/console-io.c
+++ b/c/src/lib/libbsp/mips/csb350/console/console-io.c
@@ -47,13 +47,13 @@ void console_outbyte_polled(
     while ((uart0->linestat & 0x20) == 0) {
         continue;
     }
-    
+
     uart0->txdata = ch;
     au_sync();
 }
 
 /*
- *  console_inbyte_nonblocking 
+ *  console_inbyte_nonblocking
  *
  *  This routine polls for a character.
  */
@@ -74,11 +74,11 @@ int console_inbyte_nonblocking(
 
 #include <rtems/bspIo.h>
 
-void csb250_output_char(char c) 
-{ 
-    console_outbyte_polled( 0, c ); 
+void csb250_output_char(char c)
+{
+    console_outbyte_polled( 0, c );
     if (c == '\n') {
-        console_outbyte_polled( 0, '\r' ); 
+        console_outbyte_polled( 0, '\r' );
     }
 }
 
diff --git a/c/src/lib/libbsp/mips/csb350/include/bsp.h b/c/src/lib/libbsp/mips/csb350/include/bsp.h
index ba4771810a..370a5942a4 100644
--- a/c/src/lib/libbsp/mips/csb350/include/bsp.h
+++ b/c/src/lib/libbsp/mips/csb350/include/bsp.h
@@ -34,7 +34,7 @@ extern "C" {
  */
 extern struct rtems_bsdnet_ifconfig *config;
 
-int rtems_au1x00_emac_attach(struct rtems_bsdnet_ifconfig *config, 
+int rtems_au1x00_emac_attach(struct rtems_bsdnet_ifconfig *config,
                              int attaching);
 #define RTEMS_BSP_NETWORK_DRIVER_NAME	"eth0"
 #define RTEMS_BSP_NETWORK_DRIVER_ATTACH	rtems_au1x00_emac_attach
diff --git a/c/src/lib/libbsp/mips/csb350/network/network.c b/c/src/lib/libbsp/mips/csb350/network/network.c
index 4ce42f528c..69a5898a97 100644
--- a/c/src/lib/libbsp/mips/csb350/network/network.c
+++ b/c/src/lib/libbsp/mips/csb350/network/network.c
@@ -3,7 +3,7 @@
  *
  *  Copyright (c) 2005 by Cogent Computer Systems
  *  Written by Jay Monkman <jtm@lopingdog.com>
- *	
+ *
  *  The license and distribution terms for this file may be
  *  found in found in the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
@@ -61,23 +61,23 @@ typedef struct
      * This entry *must* be the first in the sonic_softc structure.
      */
     struct arpcom                    arpcom;
-    
+
     /*
      * Interrupt vector
      */
     rtems_vector_number             vector;
-    
+
     /*
      *  Indicates configuration
      */
     int                             acceptBroadcast;
-    
+
     /*
      * Tasks waiting for interrupts
      */
     rtems_id                        rx_daemon_tid;
     rtems_id                        tx_daemon_tid;
-    
+
     /*
      * Buffers
      */
@@ -125,7 +125,7 @@ typedef struct
     unsigned long                   rx_watchdog;
     unsigned long                   rx_pkts;
     unsigned long                   rx_dropped;
-    
+
     unsigned long                   tx_deferred;
     unsigned long                   tx_underrun;
     unsigned long                   tx_aborted;
@@ -136,7 +136,7 @@ static au1x00_emac_softc_t softc[NUM_IFACES];
 
 
 /* function prototypes */
-int rtems_au1x00_emac_attach (struct rtems_bsdnet_ifconfig *config, 
+int rtems_au1x00_emac_attach (struct rtems_bsdnet_ifconfig *config,
                               int attaching);
 void au1x00_emac_init(void *arg);
 void au1x00_emac_init_hw(au1x00_emac_softc_t *sc);
@@ -160,10 +160,10 @@ static void mii_write(au1x00_emac_softc_t *sc, uint8_t reg, uint16_t val)
 
     /* write to address 0 - we only support address 0 */
     AU1X00_MAC_MIIDATA(sc->ctrl_regs) = val;
-    AU1X00_MAC_MIICTRL(sc->ctrl_regs) = (((reg & 0x1f) << 6) | 
+    AU1X00_MAC_MIICTRL(sc->ctrl_regs) = (((reg & 0x1f) << 6) |
                                          AU1X00_MAC_MIICTRL_MW);
     au_sync();
-    
+
     /* wait for it to complete */
     while (AU1X00_MAC_MIICTRL(sc->ctrl_regs) & AU1X00_MAC_MIICTRL_MB) {
         continue;
@@ -180,7 +180,7 @@ static void mii_read(au1x00_emac_softc_t *sc, uint8_t reg, uint16_t *val)
     /* write to address 0 - we only support address 0 */
     AU1X00_MAC_MIICTRL(sc->ctrl_regs) = ((reg & 0x1f) << 6);
     au_sync();
-    
+
     /* wait for it to complete */
     while (AU1X00_MAC_MIICTRL(sc->ctrl_regs) & AU1X00_MAC_MIICTRL_MB) {
         continue;
@@ -214,13 +214,13 @@ int rtems_au1x00_emac_attach (
     int unitnumber;
     char *unitname;
     static au1x00_emac_softc_t *sc;
-    
+
     /*
      * Parse driver name
      */
     if ((unitnumber = rtems_bsdnet_parse_driver_name (config, &unitname)) < 0)
         return 0;
-    
+
     /*
      * Is driver free?
      */
@@ -240,9 +240,9 @@ int rtems_au1x00_emac_attach (
     /*
      *  zero out the control structure
      */
-    
+
     memset((void *)sc, 0, sizeof(*sc));
-    
+
     sc->unitnumber = unitnumber;
     sc->int_ctrlr = AU1X00_IC0_ADDR;
 
@@ -260,7 +260,7 @@ int rtems_au1x00_emac_attach (
 
     /* If the ethernet controller is already set up, read the MAC address */
     if ((*sc->en_reg & 0x33) == 0x33) {
-        sc->arpcom.ac_enaddr[5] = ((AU1X00_MAC_ADDRHIGH(sc->ctrl_regs) >> 8) & 
+        sc->arpcom.ac_enaddr[5] = ((AU1X00_MAC_ADDRHIGH(sc->ctrl_regs) >> 8) &
                                    0xff);
         sc->arpcom.ac_enaddr[4] = ((AU1X00_MAC_ADDRHIGH(sc->ctrl_regs) >> 0) &
                                    0xff);
@@ -268,9 +268,9 @@ int rtems_au1x00_emac_attach (
                                    0xff);
         sc->arpcom.ac_enaddr[2] = ((AU1X00_MAC_ADDRLOW(sc->ctrl_regs) >> 16) &
                                    0xff);
-        sc->arpcom.ac_enaddr[1] = ((AU1X00_MAC_ADDRLOW(sc->ctrl_regs) >> 8) & 
+        sc->arpcom.ac_enaddr[1] = ((AU1X00_MAC_ADDRLOW(sc->ctrl_regs) >> 8) &
                                    0xff);
-        sc->arpcom.ac_enaddr[0] = ((AU1X00_MAC_ADDRLOW(sc->ctrl_regs) >> 0) & 
+        sc->arpcom.ac_enaddr[0] = ((AU1X00_MAC_ADDRLOW(sc->ctrl_regs) >> 0) &
                                    0xff);
     } else {
         /* It's not set up yet, so we set a MAC address */
@@ -281,7 +281,7 @@ int rtems_au1x00_emac_attach (
         sc->arpcom.ac_enaddr[1] = 0x23;
         sc->arpcom.ac_enaddr[0] = 0x00;
     }
-    
+
 
     if (config->mtu) {
         mtu = config->mtu;
@@ -290,7 +290,7 @@ int rtems_au1x00_emac_attach (
     }
 
     sc->acceptBroadcast = !config->ignore_broadcast;
-    
+
     /*
      * Set up network interface values
      */
@@ -317,19 +317,19 @@ int rtems_au1x00_emac_attach (
 
 void au1x00_emac_init(void *arg)
 {
-    au1x00_emac_softc_t     *sc = arg;      
+    au1x00_emac_softc_t     *sc = arg;
     struct ifnet *ifp = &sc->arpcom.ac_if;
 
-    /* 
-     *This is for stuff that only gets done once (au1x00_emac_init() 
-     * gets called multiple times 
+    /*
+     *This is for stuff that only gets done once (au1x00_emac_init()
+     * gets called multiple times
      */
     if (sc->tx_daemon_tid == 0)
     {
         /* Set up EMAC hardware */
         au1x00_emac_init_hw(sc);
-        
-        
+
+
         /* install the interrupt handler */
         if (sc->unitnumber == 0) {
             set_vector(au1x00_emac_isr, AU1X00_IRQ_MAC0, 1);
@@ -338,48 +338,48 @@ void au1x00_emac_init(void *arg)
         }
         AU1X00_IC_MASKCLR(sc->int_ctrlr) = sc->int_mask;
         au_sync();
-            
+
         /* set src bit */
         AU1X00_IC_SRCSET(sc->int_ctrlr) = sc->int_mask;
-        
+
         /* high level */
         AU1X00_IC_CFG0SET(sc->int_ctrlr) = sc->int_mask;
         AU1X00_IC_CFG1CLR(sc->int_ctrlr) = sc->int_mask;
         AU1X00_IC_CFG2SET(sc->int_ctrlr) = sc->int_mask;
-            
+
         /* assign to request 0 - negative logic */
         AU1X00_IC_ASSIGNSET(sc->int_ctrlr) = sc->int_mask;
         au_sync();
 
         /* Start driver tasks */
-        sc->tx_daemon_tid = rtems_bsdnet_newproc("ENTx", 
-                                                 4096, 
-                                                 au1x00_emac_tx_daemon, 
+        sc->tx_daemon_tid = rtems_bsdnet_newproc("ENTx",
+                                                 4096,
+                                                 au1x00_emac_tx_daemon,
                                                  sc);
-    
-        sc->rx_daemon_tid = rtems_bsdnet_newproc("ENRx", 
-                                                 4096, 
-                                                 au1x00_emac_rx_daemon, 
+
+        sc->rx_daemon_tid = rtems_bsdnet_newproc("ENRx",
+                                                 4096,
+                                                 au1x00_emac_rx_daemon,
                                                  sc);
-    
+
 
     }
     /* EMAC doesn't support promiscuous, so ignore requests */
     if (ifp->if_flags & IFF_PROMISC)
         printf ("Warning - AU1X00 EMAC doesn't support Promiscuous Mode!\n");
-    
+
     /*
      * Tell the world that we're running.
      */
     ifp->if_flags |= IFF_RUNNING;
-    
+
     /*
-     * start tx, rx 
+     * start tx, rx
      */
-    AU1X00_MAC_CONTROL(sc->ctrl_regs) |= (AU1X00_MAC_CTRL_TE | 
+    AU1X00_MAC_CONTROL(sc->ctrl_regs) |= (AU1X00_MAC_CTRL_TE |
                                              AU1X00_MAC_CTRL_RE);
     au_sync();
-    
+
 
 } /* au1x00_emac_init() */
 
@@ -390,7 +390,7 @@ void  au1x00_emac_init_hw(au1x00_emac_softc_t *sc)
     struct ifnet *ifp = &sc->arpcom.ac_if;
 
     /* reset the MAC */
-    *sc->en_reg = 0x40; 
+    *sc->en_reg = 0x40;
     au_sync();
     for (i = 0; i < 10000; i++) {
         continue;
@@ -404,9 +404,9 @@ void  au1x00_emac_init_hw(au1x00_emac_softc_t *sc)
     }
 
 /*
-    *sc->en_reg = (AU1X00_MAC_EN_CE | 
-                   AU1X00_MAC_EN_E2 | 
-                   AU1X00_MAC_EN_E1 | 
+    *sc->en_reg = (AU1X00_MAC_EN_CE |
+                   AU1X00_MAC_EN_E2 |
+                   AU1X00_MAC_EN_E1 |
                    AU1X00_MAC_EN_E0);
 */
     *sc->en_reg = 0x33;
@@ -445,7 +445,7 @@ void  au1x00_emac_init_hw(au1x00_emac_softc_t *sc)
     au_sync();
     printk("mac_control was set to 0x%x\n", AU1X00_MAC_CONTROL(sc->ctrl_regs));
     printk("mac_control addr is 0x%x\n", &AU1X00_MAC_CONTROL(sc->ctrl_regs));
-    
+
     /* initialize our receive buffer descriptors */
     for (i = 0; i < NUM_RX_DMA_BUFS; i++) {
         MGETHDR(m, M_WAIT, MT_DATA);
@@ -456,7 +456,7 @@ void  au1x00_emac_init_hw(au1x00_emac_softc_t *sc)
 
         /*
          * The receive buffer must be aligned with a cache line
-         * boundary. 
+         * boundary.
          */
         if (mtod(m, uint32_t) & 0x1f) {
 	  uint32_t *p = mtod(m, uint32_t *);
@@ -491,7 +491,7 @@ void  au1x00_emac_init_hw(au1x00_emac_softc_t *sc)
 void au1x00_emac_start(struct ifnet *ifp)
 {
     au1x00_emac_softc_t *sc = ifp->if_softc;
-    
+
     rtems_event_send(sc->tx_daemon_tid, START_TX_EVENT);
     ifp->if_flags |= IFF_OACTIVE;
 }
@@ -499,15 +499,15 @@ void au1x00_emac_start(struct ifnet *ifp)
 void au1x00_emac_stop (au1x00_emac_softc_t *sc)
 {
     struct ifnet *ifp = &sc->arpcom.ac_if;
-    
+
     ifp->if_flags &= ~IFF_RUNNING;
-    
+
     /*
      * Stop the transmitter and receiver.
      */
 
     /* Disable TX/RX  */
-    AU1X00_MAC_CONTROL(sc->ctrl_regs) &= ~(AU1X00_MAC_CTRL_TE | 
+    AU1X00_MAC_CONTROL(sc->ctrl_regs) &= ~(AU1X00_MAC_CTRL_TE |
                                       AU1X00_MAC_CTRL_RE);
     au_sync();
 }
@@ -577,7 +577,7 @@ void au1x00_emac_rx_daemon (void *arg)
 
         /* while there are packets to receive */
 
-        while (!(sc->rx_dma[sc->rx_head].addr & (AU1X00_MAC_DMA_RXADDR_DN | 
+        while (!(sc->rx_dma[sc->rx_head].addr & (AU1X00_MAC_DMA_RXADDR_DN |
                                                 AU1X00_MAC_DMA_RXADDR_EN))) {
             status = sc->rx_dma[sc->rx_head].stat;
             if (status & AU1X00_MAC_DMA_RXSTAT_MI) {
@@ -621,51 +621,51 @@ void au1x00_emac_rx_daemon (void *arg)
             }
 
             /* If no errrors, accept packet */
-            if ((status & (AU1X00_MAC_DMA_RXSTAT_CR | 
-                           AU1X00_MAC_DMA_RXSTAT_DB | 
+            if ((status & (AU1X00_MAC_DMA_RXSTAT_CR |
+                           AU1X00_MAC_DMA_RXSTAT_DB |
                            AU1X00_MAC_DMA_RXSTAT_RF)) == 0) {
 
                 sc->rx_pkts++;
 
                 /* find the start of the mbuf */
                 m = sc->rx_mbuf[sc->rx_head];
-                
+
                 /* set the length of the mbuf */
                 m->m_len = AU1X00_MAC_DMA_RXSTAT_LEN(sc->rx_dma[sc->rx_head].stat);
                 m->m_len -= 4; /* remove ethernet CRC */
-                
+
                 m->m_pkthdr.len = m->m_len;
-                
+
                 /* strip off the ethernet header from the mbuf */
                 /* but save the pointer to it */
                 eh = mtod (m, struct ether_header *);
                 m->m_data += sizeof(struct ether_header);
-                
+
                 /* give the received packet to the stack */
                 ether_input(ifp, eh, m);
                 /* get a new buf and make it ready for the MAC */
                 MGETHDR(m, M_WAIT, MT_DATA);
                 MCLGET(m, M_WAIT);
-                
+
                 m->m_pkthdr.rcvif = ifp;
                 m->m_nextpkt = 0;
-                
+
                 /*
                  * The receive buffer must be aligned with a cache line
-                 * boundary. 
+                 * boundary.
                  */
 		{
                   uint32_t *p = mtod(m, uint32_t *);
                   *p = (mtod(m, uint32_t) + 0x1f) & ~0x1f;
 		}
-            
+
             } else {
                 sc->rx_dropped++;
 
                 /* find the mbuf so we can reuse it*/
                 m = sc->rx_mbuf[sc->rx_head];
             }
-            
+
             /* set up the receive dma to use the mbuf's cluster */
             sc->rx_dma[sc->rx_head].addr = (mtod(m, uint32_t) & ~0xe0000000);
             au_sync();
@@ -673,7 +673,7 @@ void au1x00_emac_rx_daemon (void *arg)
 
             sc->rx_dma[sc->rx_head].addr |= AU1X00_MAC_DMA_RXADDR_EN;
             au_sync();
-            
+
 
             /* increment the buffer index */
             sc->rx_head++;
@@ -697,20 +697,20 @@ void au1x00_emac_sendpacket (struct ifnet *ifp, struct mbuf *m)
                                            AU1X00_MAC_DMA_TXADDR_DN)) != 0) {
         continue;
     }
-    
+
     /* copy the mbuf chain into the transmit buffer */
     l = m;
 
     txbuf = (uint32_t)sc->tx_buf[sc->tx_head];
     while (l != NULL)
     {
-        
+
         memcpy(((char *)txbuf + pkt_offset), /* offset into pkt for mbuf */
-               (char *)mtod(l, void *),      /* cast to void */ 
+               (char *)mtod(l, void *),      /* cast to void */
                l->m_len);                    /* length of this mbuf */
-        
+
         pkt_offset += l->m_len;              /* update offset */
-        l = l->m_next;                       /* get next mbuf, if any */     
+        l = l->m_next;                       /* get next mbuf, if any */
     }
 
     /* Pad if necessary */
@@ -722,12 +722,12 @@ void au1x00_emac_sendpacket (struct ifnet *ifp, struct mbuf *m)
     /* send it off */
     sc->tx_dma[sc->tx_head].stat = 0;
     sc->tx_dma[sc->tx_head].len = pkt_offset;
-    sc->tx_dma[sc->tx_head].addr = ((txbuf & ~0xe0000000) | 
+    sc->tx_dma[sc->tx_head].addr = ((txbuf & ~0xe0000000) |
                                     AU1X00_MAC_DMA_TXADDR_EN);
     au_sync();
 
 
-    /* 
+    /*
      *Without this delay, some outgoing packets never
      * make it out the device. Nothing in the documentation
      * explains this.
@@ -747,7 +747,7 @@ void au1x00_emac_sendpacket (struct ifnet *ifp, struct mbuf *m)
 } /* au1x00_emac_sendpacket () */
 
 
-        
+
 /* Show interface statistics */
 void au1x00_emac_stats (au1x00_emac_softc_t *sc)
 {
@@ -769,7 +769,7 @@ void au1x00_emac_stats (au1x00_emac_softc_t *sc)
     printf("RX runt:%-8lu", sc->rx_runt);
     printf("       RX watchdog:%-8lu", sc->rx_watchdog);
     printf("   RX dropped:%-8lu\n", sc->rx_dropped);
-    
+
     printf("TX Packets:%-8lu", sc->tx_pkts);
     printf("    TX Deferred:%-8lu", sc->tx_deferred);
     printf("   TX Underrun:%-8lu\n", sc->tx_underrun);
@@ -784,38 +784,38 @@ au1x00_emac_ioctl (struct ifnet *ifp, int command, caddr_t data)
 {
     au1x00_emac_softc_t *sc = ifp->if_softc;
     int error = 0;
-    
+
     switch (command) {
     case SIOCGIFADDR:
     case SIOCSIFADDR:
         ether_ioctl (ifp, command, data);
         break;
-        
+
     case SIOCSIFFLAGS:
         switch (ifp->if_flags & (IFF_UP | IFF_RUNNING))
         {
         case IFF_RUNNING:
             au1x00_emac_stop (sc);
             break;
-            
+
         case IFF_UP:
             au1x00_emac_init (sc);
             break;
-            
+
         case IFF_UP | IFF_RUNNING:
             au1x00_emac_stop (sc);
             au1x00_emac_init (sc);
             break;
-            
+
         default:
             break;
         } /* switch (if_flags) */
         break;
-        
+
     case SIO_RTEMS_SHOW_STATS:
         au1x00_emac_stats (sc);
         break;
-        
+
         /*
          * FIXME: All sorts of multicast commands need to be added here!
          */
@@ -841,7 +841,7 @@ rtems_isr au1x00_emac_isr (rtems_vector_number v)
     sc->interrupts++;
 
     /*
-     * Since there's no easy way to find out the source of the 
+     * Since there's no easy way to find out the source of the
      * interrupt, we have to look at the tx and rx dma buffers
      */
     /* receive interrupt */
@@ -850,7 +850,7 @@ rtems_isr au1x00_emac_isr (rtems_vector_number v)
         sc->rx_interrupts++;
         sc->rx_dma[sc->rx_tail].addr &= ~AU1X00_MAC_DMA_RXADDR_DN;
         au_sync();
-        
+
         sc->rx_tail++;
         if (sc->rx_tail >= NUM_RX_DMA_BUFS) {
             sc->rx_tail = 0;
@@ -865,7 +865,7 @@ rtems_isr au1x00_emac_isr (rtems_vector_number v)
         uint32_t status;
         tx_flag = 1;
         sc->tx_interrupts++;
-        
+
         status = sc->tx_dma[sc->tx_tail].stat;
         if (status & AU1X00_MAC_DMA_TXSTAT_DF) {
             sc->tx_deferred++;
@@ -876,7 +876,7 @@ rtems_isr au1x00_emac_isr (rtems_vector_number v)
         if (status & AU1X00_MAC_DMA_TXSTAT_FA) {
             sc->tx_aborted++;
         }
-        
+
         sc->tx_dma[sc->tx_tail].addr = 0;
         au_sync();
 
diff --git a/c/src/lib/libbsp/mips/csb350/start/start.S b/c/src/lib/libbsp/mips/csb350/start/start.S
index 45ec44d180..8c29999dce 100644
--- a/c/src/lib/libbsp/mips/csb350/start/start.S
+++ b/c/src/lib/libbsp/mips/csb350/start/start.S
@@ -3,7 +3,7 @@
  *
  *  Copyright (c) 2005 by Cogent Computer Systems
  *  Written by Jay Monkman <jtm@lopingdog.com>
- *	
+ *
  *  The license and distribution terms for this file may be
  *  found in found in the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
@@ -29,7 +29,7 @@
 _start:
 	.set	noreorder
 
-	/* Get the address of start into $5 in a position independent 
+	/* Get the address of start into $5 in a position independent
 	 * fashion. This lets us know whether we have been relocated or not.
 	 */
 	$LF1 = . + 8
@@ -47,7 +47,7 @@ _branch:
 	li	v0, SR_PE|SR_FR|SR_KX|SR_SX|SR_UX
 	mtc0	v0, C0_SR
 2:
-/* Fix high bits, if any, of the PC so that exception handling 
+/* Fix high bits, if any, of the PC so that exception handling
    doesn't get confused.  */
 	la v0, 3f
 	jr	v0
@@ -75,7 +75,7 @@ zerobss:
 	   case main wants to write them back to the stack.  The caller is
 	   supposed to allocate stack space for parameters in registers in
 	   the old MIPS ABIs.  We must do this even though we aren't passing
-	   arguments, because main might be declared to have them. 
+	   arguments, because main might be declared to have them.
 
 	   Some ports need a larger alignment for the stack, so we subtract
 	   32, which satisifes the stack for the arguments and keeps the
@@ -98,7 +98,7 @@ init:
 					/* destructors */
 	move	a0,v0			/* pass through the exit code */
 	.end	init
-	
+
 /*
  * _sys_exit -- Exit from the application. Normally we cause a user trap
  *          to return to the ROM monitor for another run. NOTE: This is
@@ -121,5 +121,5 @@ _sys_exit:
 	b	7b			/* but loop back just in-case */
 	nop
 	.end _sys_exit
-        
+
 /* EOF crt0.S */
diff --git a/c/src/lib/libbsp/mips/csb350/startup/bspreset.c b/c/src/lib/libbsp/mips/csb350/startup/bspreset.c
index 4bfdbddae3..e17b1f41a8 100644
--- a/c/src/lib/libbsp/mips/csb350/startup/bspreset.c
+++ b/c/src/lib/libbsp/mips/csb350/startup/bspreset.c
@@ -14,7 +14,7 @@
 void bsp_reset(void)
 {
   void (*reset_func)(void);
-  
+
   reset_func = (void *)0xbfc00000;
 
   mips_set_sr( 0x00200000 ); /* all interrupts off, boot exception vectors */
diff --git a/c/src/lib/libbsp/mips/csb350/startup/bspstart.c b/c/src/lib/libbsp/mips/csb350/startup/bspstart.c
index 6b9ea1e00a..afa50171c3 100644
--- a/c/src/lib/libbsp/mips/csb350/startup/bspstart.c
+++ b/c/src/lib/libbsp/mips/csb350/startup/bspstart.c
@@ -30,7 +30,7 @@ au1x00_uart_t *uart3 = (au1x00_uart_t *)AU1X00_UART3_ADDR;
  */
 void bsp_start( void )
 {
-  unsigned int compare = 0; 
+  unsigned int compare = 0;
 
   mips_set_sr( 0x7f00 );  /* all interrupts unmasked but globally off */
                           /* depend on the IRC to take care of things */
diff --git a/c/src/lib/libbsp/mips/csb350/timer/timer.c b/c/src/lib/libbsp/mips/csb350/timer/timer.c
index 68cc2acd1a..acbca37414 100644
--- a/c/src/lib/libbsp/mips/csb350/timer/timer.c
+++ b/c/src/lib/libbsp/mips/csb350/timer/timer.c
@@ -1,10 +1,10 @@
-/* 
+/*
  *  This file implements a benchmark timer using the count/compare
  *  CP0 registers.
  *
  *  Copyright (c) 2005 by Cogent Computer Systems
  *  Written by Jay Monkman <jtm@lopingdog.com>
- *	
+ *
  *  The license and distribution terms for this file may be
  *  found in found in the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
diff --git a/c/src/lib/libbsp/mips/hurricane/clock/ckinit.c b/c/src/lib/libbsp/mips/hurricane/clock/ckinit.c
index 1841bd8d85..b9c37d1116 100644
--- a/c/src/lib/libbsp/mips/hurricane/clock/ckinit.c
+++ b/c/src/lib/libbsp/mips/hurricane/clock/ckinit.c
@@ -90,7 +90,7 @@ uint32_t Clock_isrs;              /* ISRs until next tick */
 /*
  * These are set by clock driver during its init
  */
- 
+
 rtems_device_major_number rtems_clock_major = ~0;
 rtems_device_minor_number rtems_clock_minor;
 
@@ -163,24 +163,24 @@ void Install_clock(
   /*
   *  Hardware specific initialize goes here
   */
-  
+
   /* Set up USC heartbeat timer to generate interrupts */
   disable_hbi();      /* Disable heartbeat interrupt in USC */
-  
+
               /* Install interrupt handler */
   Old_ticker = (rtems_isr_entry) set_vector( USC_isr, CLOCK_VECTOR, 1 );
-  
+
   init_hbt();        /* Initialize heartbeat timer */
-  
+
   reset_wdt();      /* Reset watchdog timer */
-  
+
   enable_wdi();      /* Enable watchdog interrupt in USC */
-  
+
   enable_hbi();      /* Enable heartbeat interrupt in USC */
-  
+
               /* Enable USC interrupt in MIPS processor */
   mips_enable_in_interrupt_mask(CLOCK_VECTOR_MASK);
-  
+
   /*
   *  Schedule the clock cleanup routine to execute if the application exits.
   */
@@ -211,14 +211,14 @@ rtems_device_driver Clock_initialize(
 )
 {
   Install_clock( Clock_isr );
- 
+
   /*
    * make major/minor avail to others such as shared memory driver
    */
- 
+
   rtems_clock_major = major;
   rtems_clock_minor = minor;
- 
+
   return RTEMS_SUCCESSFUL;
 }
 
diff --git a/c/src/lib/libbsp/mips/hurricane/clock/clock.S b/c/src/lib/libbsp/mips/hurricane/clock/clock.S
index 112ea937a5..d94bd1b300 100644
--- a/c/src/lib/libbsp/mips/hurricane/clock/clock.S
+++ b/c/src/lib/libbsp/mips/hurricane/clock/clock.S
@@ -1,4 +1,4 @@
-/*  clock.s 
+/*  clock.s
  *
  *  This file contains the assembly code for the Hurricane BSP clock driver.
  *
diff --git a/c/src/lib/libbsp/mips/hurricane/console/console.c b/c/src/lib/libbsp/mips/hurricane/console/console.c
index 06f93a86df..f850cc12d9 100644
--- a/c/src/lib/libbsp/mips/hurricane/console/console.c
+++ b/c/src/lib/libbsp/mips/hurricane/console/console.c
@@ -54,16 +54,16 @@ rtems_device_driver console_initialize(
 )
 {
   rtems_status_code status;
- 
+
   status = rtems_io_register_name(
     "/dev/console",
     major,
     (rtems_device_minor_number) 0
   );
- 
+
   if (status != RTEMS_SUCCESSFUL)
     rtems_fatal_error_occurred(status);
- 
+
   return RTEMS_SUCCESSFUL;
 }
 
@@ -157,7 +157,7 @@ rtems_device_driver console_open(
 #endif
   return RTEMS_SUCCESSFUL;
 }
- 
+
 /*
  *  Close entry point
  */
@@ -189,7 +189,7 @@ rtems_device_driver console_read(
   char *buffer;
   int maximum;
   int count = 0;
- 
+
   rw_args = (rtems_libio_rw_args_t *) arg;
 
   buffer = rw_args->buffer;
@@ -208,7 +208,7 @@ rtems_device_driver console_read(
 }
 
 /*
- * write bytes to the serial port. Stdout and stderr are the same. 
+ * write bytes to the serial port. Stdout and stderr are the same.
  */
 
 rtems_device_driver console_write(
diff --git a/c/src/lib/libbsp/mips/hurricane/include/bsp.h b/c/src/lib/libbsp/mips/hurricane/include/bsp.h
index f8648cfcc6..3305668daa 100644
--- a/c/src/lib/libbsp/mips/hurricane/include/bsp.h
+++ b/c/src/lib/libbsp/mips/hurricane/include/bsp.h
@@ -35,7 +35,7 @@ extern uint32_t mips_get_timer( void );
  *  Simple spin delay in microsecond units for device drivers.
  *  This is very dependent on the clock speed of the target.
  *
- *  NOTE: This macro generates a warning like "integer constant out 
+ *  NOTE: This macro generates a warning like "integer constant out
  *        of range" which is safe to ignore.  In 64 bit mode, unsigned32
  *        types are actually 64 bits long so that comparisons between
  *        unsigned32 types and pointers are valid.  The warning is caused
diff --git a/c/src/lib/libbsp/mips/hurricane/start/start.S b/c/src/lib/libbsp/mips/hurricane/start/start.S
index e3bd7db3b5..f4d2a5b15a 100644
--- a/c/src/lib/libbsp/mips/hurricane/start/start.S
+++ b/c/src/lib/libbsp/mips/hurricane/start/start.S
@@ -19,7 +19,7 @@ two paragraphs in the transferred software.
 
 COPYRIGHT IDT CORPORATION 1996
 LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
-*/ 
+*/
 
 /*************************************************************************
 **
@@ -37,7 +37,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #include <rtems/asm.h>
 
 
-#if 0	
+#if 0
 	.extern _fdata,4		/* this is defined by the linker */
 	.extern _edata,4		/* this is defined by the linker */
 	.extern _idata,4		/* this is defined by the linker */
@@ -53,11 +53,11 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
   at least 16 megabytes of RAM */
 #define HARD_CODED_MEM_SIZE 0x1000000
 
-#define TMP_STKSIZE  1024 
+#define TMP_STKSIZE  1024
 
 /*
-** P_STACKSIZE is the size of the Prom Stack. 
-** the prom stack grows downward 
+** P_STACKSIZE is the size of the Prom Stack.
+** the prom stack grows downward
 */
 #define	P_STACKSIZE	0x2000   /* sets stack size to 8k */
 
@@ -72,7 +72,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 **		c) Clear all IntMask Enables
 **		d) Set kernel/disabled mode
 **	2)  Initialize Cause Register
-**		a)  clear software interrupt bits       
+**		a)  clear software interrupt bits
 **	3)  Determine FPU installed or not
 **		if not, clear CoProcessor 1 usable bit
 **	4)  Clear bss area
@@ -84,15 +84,15 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 **	9)  Flush Instruction and Data caches
 ** 	10)  If there is a Translation Lookaside Buffer, Clear the TLB
 ** 	11)  Execute initialization code if the IDT/c library is to be used
-** 
+**
 ** 	12)  Jump to user's "main()" (boot_card() for RTEMS)
 ** 	13)  Jump to promexit
 **
-**	IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally. 
+**	IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally.
 **	This is used to mark code specific to R3xxx or R4xxx processors.
-**	IDT/C 6.x defines __mips to be the ISA level for which we're 
-**	generating code. This is used to make sure the stack etc. is 
-**	double word aligned, when using -mips3 (default) or -mips2, 
+**	IDT/C 6.x defines __mips to be the ISA level for which we're
+**	generating code. This is used to make sure the stack etc. is
+**	double word aligned, when using -mips3 (default) or -mips2,
 **	when compiling with IDT/C6.x
 **
 ***************************************************************************/
@@ -110,7 +110,7 @@ FRAME(start,sp,0,ra)
 	nop
 	mtc0	zero,C0_CAUSE		/* clear software interrupts */
 	nop
-	
+
 	la	t0,0xBE200000		/* on Hurricane board, enable interrupt output signal from UART ch. B */
 	li	t1,0x8			/* UART INT B signal is left tri-state'd after reset, this results in processor interrupt signal being driven active low */
 	sw	t1,0x10(t0)
@@ -119,10 +119,10 @@ FRAME(start,sp,0,ra)
 	mtc0	v0,C0_CONFIG
 
 /*
-**	check to see if an fpu is really plugged in 
+**	check to see if an fpu is really plugged in
 */
 	li	t3,0xaaaa5555		/*  put a's and 5's in t3	*/
-	mtc1	t3,fp0			/* try to write them into fp0   */	
+	mtc1	t3,fp0			/* try to write them into fp0   */
 	mtc1	zero,fp1		/* try to write zero in fp	*/
 	mfc1	t0,fp0
 	mfc1	t1,fp1
@@ -140,7 +140,7 @@ FRAME(start,sp,0,ra)
 
 	mtc0	v0, C0_SR		/* reset status register */
 2:
-	la  	gp, _gp			
+	la  	gp, _gp
 
 #if 0
 					/* Initialize data sections from "rom" copy */
@@ -160,7 +160,7 @@ FRAME(start,sp,0,ra)
 	la	v1,end 			/* end of bss */
 4:	sw	zero,0(v0)
 	bltu	v0,v1,4b
-	add	v0,4 
+	add	v0,4
 
 
 /************************************************************************
@@ -173,7 +173,7 @@ FRAME(start,sp,0,ra)
 **
 *************************************************************************/
 	/* For MIPS 3, we need to be sure that the stack is aligned on a
-	 * double word boundary. 
+	 * double word boundary.
 	 */
 	andi	t0, v0, 0x7
 	beqz	t0, 11f   /* Last three bits Zero, already aligned */
@@ -185,11 +185,11 @@ FRAME(start,sp,0,ra)
 	add	v1, v0, TMP_STKSIZE 	/* end of bss + length of tmp stack */
 	sub	v1, v1, (4*4)		/* overhead */
 	move	sp, v1			/* set sp to top of stack */
-4:	sw	zero, 0(v0)  
+4:	sw	zero, 0(v0)
 	bltu	v0, v1, 4b		/* clear out temp stack */
-	add	v0, 4 
-	
-/* 	jal	init_exc_vecs */		/* install exception handlers */ 
+	add	v0, 4
+
+/* 	jal	init_exc_vecs */		/* install exception handlers */
 /*	nop */				/* MUST do before memory probes */
 
 					/* Force processor into uncached space during memory/cache probes */
@@ -216,7 +216,7 @@ FRAME(start,sp,0,ra)
 	move	v0, a0			/* mem_size */
 
 	/* For MIPS 3, we need to be sure that the stack (and hence v0
-	 * here) is aligned on a double word boundary. 
+	 * here) is aligned on a double word boundary.
 	 */
 	andi	t0, v0, 0x7
 	beqz	t0, 12f   /* Last three bits Zero, already aligned */
@@ -228,9 +228,9 @@ FRAME(start,sp,0,ra)
 
 /**************************************************************************
 **
-**  Permanent Stack - now know top of memory, put permanent stack there	
+**  Permanent Stack - now know top of memory, put permanent stack there
 **
-***************************************************************************/ 
+***************************************************************************/
 
 	la	t2, _fbss		/* cache mode as linked */
 	and	t2, 0xF0000000		/* isolate segment */
@@ -244,9 +244,9 @@ FRAME(start,sp,0,ra)
 	move	v1, v0
 	subu	v1, P_STACKSIZE 	/* clear requested stack size */
 
-7:	sw	zero, 0(v1)		/* clear P_STACKSIZE  stack */ 
+7:	sw	zero, 0(v1)		/* clear P_STACKSIZE  stack */
 	bltu	v1,v0,7b
-	add	v1, 4 
+	add	v1, 4
 	.set	reorder
 
 /* FIX THIS - This corrupts memory spaces */
@@ -258,7 +258,7 @@ FRAME(start,sp,0,ra)
 **
 **	If this chip supports a Translation Lookaside Buffer, clear it
 **
-***************************************************************************/ 
+***************************************************************************/
 
 	.set	noreorder
 	mfc0	t1,  C0_SR		/* look at Status Register */
@@ -279,7 +279,7 @@ FRAME(start,sp,0,ra)
 
 /************************************************************************
 **
-**  Initialization required if using IDT/c or libc.a, standard C Lib 
+**  Initialization required if using IDT/c or libc.a, standard C Lib
 **
 **  can SKIP if not necessary for application
 **
@@ -309,7 +309,7 @@ FRAME(start,sp,0,ra)
 1:
 	beq	zero,zero,1b
 	nop
-	
+
 ENDFRAME(start)
 
 /*
@@ -327,7 +327,7 @@ FRAME(_sys_exit,sp,0,ra)
 13:
 	b	13b				# but loop back just in-case
 	nop
-	
+
 ENDFRAME(_sys_exit)
 
 
diff --git a/c/src/lib/libbsp/mips/hurricane/startup/bspstart.c b/c/src/lib/libbsp/mips/hurricane/startup/bspstart.c
index 4f89abc503..100bcbb787 100644
--- a/c/src/lib/libbsp/mips/hurricane/startup/bspstart.c
+++ b/c/src/lib/libbsp/mips/hurricane/startup/bspstart.c
@@ -19,7 +19,7 @@
 #include <bsp.h>
 
 uint32_t bsp_clicks_per_microsecond;
- 
+
 /*
  *  bsp_start
  *
diff --git a/c/src/lib/libbsp/mips/hurricane/startup/exception.S b/c/src/lib/libbsp/mips/hurricane/startup/exception.S
index bb9e01d004..1dca7c5510 100644
--- a/c/src/lib/libbsp/mips/hurricane/startup/exception.S
+++ b/c/src/lib/libbsp/mips/hurricane/startup/exception.S
@@ -184,7 +184,7 @@ _chk_int:
         /* wastes a lot of stack space for context?? */
 	ADDIU    sp,sp,-EXCP_STACK_SIZE
 
-        STREG ra, R_RA*R_SZ(sp)  /* store ra on the stack */ 
+        STREG ra, R_RA*R_SZ(sp)  /* store ra on the stack */
         STREG v0, R_V0*R_SZ(sp)
         STREG v1, R_V1*R_SZ(sp)
         STREG a0, R_A0*R_SZ(sp)
@@ -201,13 +201,13 @@ _chk_int:
         STREG t7, R_T7*R_SZ(sp)
         mflo  t0
         STREG t8, R_T8*R_SZ(sp)
-        STREG t0, R_MDLO*R_SZ(sp) 
+        STREG t0, R_MDLO*R_SZ(sp)
         STREG t9, R_T9*R_SZ(sp)
         mfhi  t0
         STREG gp, R_GP*R_SZ(sp)
-        STREG t0, R_MDHI*R_SZ(sp) 
+        STREG t0, R_MDHI*R_SZ(sp)
         STREG fp, R_FP*R_SZ(sp)
-	
+
         .set noat
         STREG AT, R_AT*R_SZ(sp)
         .set at
@@ -277,7 +277,7 @@ _ISR_Handler_cleanup:
    *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
    *    restore stack
    *  #endif
-   *  
+   *
    *  if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing )
    *    goto the label "exit interrupt (simple case)"
    */
@@ -311,7 +311,7 @@ _ISR_Handler_cleanup:
 	/* save off our stack frame so the context switcher can get to it */
 	la	t0,__exceptionStackFrame
 	STREG	sp,(t0)
-					
+
         jal     _Thread_Dispatch
         NOP
 
@@ -321,7 +321,7 @@ _ISR_Handler_cleanup:
 	STREG	zero,(t0)
 	NOP
 
-/* 
+/*
 ** turn interrupts back off while we restore context so
 ** a badly timed interrupt won't accidentally mess things up
 */
@@ -335,7 +335,7 @@ _ISR_Handler_cleanup:
 	or	t0,t1
 #elif __mips == 1
 	/* ints off, current & prev kernel mode on (kernel mode enabled is bit clear..argh!) */
-	li	t1,SR_IEC | SR_KUP | SR_KUC	
+	li	t1,SR_IEC | SR_KUP | SR_KUC
 	not	t1
 	and	t0, t1
 #endif
@@ -347,14 +347,14 @@ _ISR_Handler_cleanup:
 	**
 	** make sure previous int enable is on  because we're returning from an interrupt
 	** which means interrupts have to be enabled
-	
+
 	li	t1,SR_IEP
 	or	t0,t1
 	*/
 #endif
         mtc0    t0, C0_SR
 	NOP
-	
+
   /*
    *  prepare to get out of interrupt
    *  return from interrupt  (maybe to _ISR_Dispatch)
@@ -370,7 +370,7 @@ _ISR_Handler_exit:
         LDREG t8, R_MDLO*R_SZ(sp)
         LDREG t0, R_T0*R_SZ(sp)
         mtlo  t8
-        LDREG t8, R_MDHI*R_SZ(sp)           
+        LDREG t8, R_MDHI*R_SZ(sp)
         LDREG t1, R_T1*R_SZ(sp)
         mthi  t8
         LDREG t2, R_T2*R_SZ(sp)
@@ -390,10 +390,10 @@ _ISR_Handler_exit:
         LDREG a3, R_A3*R_SZ(sp)
         LDREG v1, R_V1*R_SZ(sp)
         LDREG v0, R_V0*R_SZ(sp)
-	
+
         LDREG k1, R_EPC*R_SZ(sp)
 	mtc0  k1,C0_EPC
-	
+
 	.set noat
         LDREG     AT, R_AT*R_SZ(sp)
         .set at
@@ -407,14 +407,14 @@ _ISR_Handler_quick_exit:
 
 	/* Interrupts from USC320 are serviced here */
 	.global	USC_isr
-	.extern	Clock_isr	
+	.extern	Clock_isr
 USC_isr:
 	/* check if it's a USC320 heartbeat interrupt */
         la      k0,INT_STAT	/* read INT_STAT register */
         lw      k0,(k0)
         nop			/* reading from external device	*/
         sll     k0,(31-21)	/* test bit 21 (HBI) */
-        
+
         bgez	k0,USC_isr2	/* branch if not a heartbeat interrupt */
 	NOP
 
@@ -434,7 +434,7 @@ USC_isr1:
 	nop
 USC_isr2:
 	j	ra		/* no serviceable interrupt, return without doing anything */
-	nop		
+	nop
 
        .set    reorder
 
@@ -450,7 +450,7 @@ FRAME(_BRK_Handler,sp,0,ra)
 	and	k1,k1,k0
 	la	k0,INT_CFG3
 	sw	k1,(k0)
-	
+
 	la  k0,_brk_esr_link	/* Jump to next exception handler in PMON exception chain */
 	lw  k0,(k0)
 	lw  k0,4(k0)
@@ -478,7 +478,7 @@ FRAME(init_exc_vecs,sp,0,ra)
 	.set noreorder
 
 	.extern mon_onintr
-	
+
 /* Install interrupt handler in PMON exception handling chain */
 
 	addiu	sp,sp,-8
@@ -517,30 +517,30 @@ FRAME(init_hbt,sp,0,ra)
 	la	t0,SYSTEM	# Unlock USC registers
 	li	t1,0xA5
 	sb	t1,(t0)
-	
+
 	la	t0,WD_HBI	# Initialize heatbeat and watchdog timers
 
-				# (1 / 64 MHz) * 4000 * (63 + 1) = 4000.0 microseconds 
+				# (1 / 64 MHz) * 4000 * (63 + 1) = 4000.0 microseconds
 				# Watchdog period is heartbeat period times watchdog timer constant (bits 7 - 0)
 				# Watchdog period = 4000 * 5 = 20000 microseconds
 	li	t1,(WD_EN | HBI_4000_PS | 0x00003F00 | 0x5)
 
-				# (1 / 64 MHz) * 4000 * (15 + 1) = 1000.0 microseconds 
+				# (1 / 64 MHz) * 4000 * (15 + 1) = 1000.0 microseconds
 				# Watchdog period is heartbeat period times watchdog timer constant (bits 7 - 0)
 				# Watchdog period = 1000 * 20 = 20000 microseconds
 	li	t1,(WD_EN | HBI_4000_PS | 0x00000F00 | 0x14)
 
-				# (1 / 64 MHz) * 40000 * (15 + 1) = 10000.0 microseconds 
+				# (1 / 64 MHz) * 40000 * (15 + 1) = 10000.0 microseconds
 				# Watchdog period is heartbeat period times watchdog timer constant (bits 7 - 0)
 				# Watchdog period = 10000 * 20 = 200000 microseconds
 	li	t1,(WD_EN | HBI_4000_PS | 0x00009600 | 0x14)
 
 	sw	t1,(t0)
-	
+
 	la	t0,SYSTEM	# Lock USC registers
 	li	t1,0x60
 	sb	t1,(t0)
-	
+
 	.set reorder
 	j	ra
 	nop
@@ -555,9 +555,9 @@ FRAME(reset_wdt,sp,0,ra)
 	.set noreorder
 
 	la	t0,WD_HBI+2	# Load address watchdog timer reset byte
-	li	t1,WD_INIT	
+	li	t1,WD_INIT
 	sb	t1,(t0)
-	
+
 	.set reorder
 	j	ra
 	nop
@@ -575,7 +575,7 @@ FRAME(disable_wdt,sp,0,ra)
 	li	t2,~WD_EN
 	and	t1,t1,t2
 	sw	t1,(t0)
-	
+
 	.set reorder
 	j	ra
 	nop
@@ -588,13 +588,13 @@ ENDFRAME(disable_wdt)
 */
 FRAME(enable_hbi,sp,0,ra)
 	.set noreorder
-	
+
 	la	t0,INT_CFG3	# Enable heartbeat interrupt in USC320
 	lw	t1,(t0)
 	li	t2,(HBI_MASK | MODE_TOTEM_POLE)
 	or	t1,t1,t2
 	sw	t1,(t0)
-	
+
 	.set reorder
 	j	ra
 	nop
@@ -612,7 +612,7 @@ FRAME(disable_hbi,sp,0,ra)
 	li	t2,~HBI_MASK
 	and	t1,t1,t2
 	sw	t1,(t0)
-	
+
 	.set reorder
 	j	ra
 	nop
@@ -626,13 +626,13 @@ ENDFRAME(disable_hbi)
 */
 FRAME(enable_wdi,sp,0,ra)
 	.set noreorder
-	
+
 	la	t0,INT_CFG1	# Enable watchdog interrupt in USC320
 	lw	t1,(t0)
 	li	t2,(WDI_MASK | MODE_TOTEM_POLE)
 	or	t1,t1,t2
 	sw	t1,(t0)
-	
+
 	.set reorder
 	j	ra
 	nop
@@ -645,17 +645,17 @@ ENDFRAME(enable_wdi)
 */
 FRAME(disable_wdi,sp,0,ra)
 	.set noreorder
-	
+
 	la	t0,INT_CFG1	# Disable watchdog interrupt in USC320
 	lw	t1,(t0)
 	li	t2,~(WDI_MASK | MODE_TOTEM_POLE)
 	and	t1,t1,t2
 	sw	t1,(t0)
-	
+
 	la	t0,INT_STAT	# Clear watchdog interrupt status bit
 	li	t1,WDI_MASK
 	sw	t1,(t0)
-	
+
 	.set reorder
 	j	ra
 	nop
@@ -666,7 +666,7 @@ ENDFRAME(disable_wdi)
 	.data
 
 k1tmp:	.word	0	/* Temporary strage for K1 during interrupt service */
-	
+
 /*************************************************************
 *
 * Exception handler links, used in PMON exception handler chains
@@ -676,7 +676,7 @@ k1tmp:	.word	0	/* Temporary strage for K1 during interrupt service */
 _int_esr_link:
 	.word	0
 	.word	hurricane_ISR_Handler
-	
+
 	/* Break exception service routine link */
 	.global	_brk_esr_link
 _brk_esr_link:
@@ -684,5 +684,5 @@ _brk_esr_link:
 	.word	_BRK_Handler
 
 
-	
+
 
diff --git a/c/src/lib/libbsp/mips/hurricane/startup/idttlb.S b/c/src/lib/libbsp/mips/hurricane/startup/idttlb.S
index 15293fa02a..af32824bd7 100644
--- a/c/src/lib/libbsp/mips/hurricane/startup/idttlb.S
+++ b/c/src/lib/libbsp/mips/hurricane/startup/idttlb.S
@@ -182,7 +182,7 @@ ENDFRAME(ret_tlbhi)
 FRAME(ret_tlbpid,sp,0,ra)
 #if __mips == 1
 	.set	noreorder
-	mfc0	v0,C0_TLBHI		# fetch tlb high 
+	mfc0	v0,C0_TLBHI		# fetch tlb high
 	nop
 	and	v0,TLBHI_PIDMASK	# isolate and position
 	srl	v0,TLBHI_PIDSHIFT
@@ -215,8 +215,8 @@ FRAME(tlbprobe,sp,0,ra)
 	mfc0	t0,C0_SR		/* fetch status reg */
 	and	a0,TLBHI_VPNMASK	/* isolate just the vpn */
 	and	t0,~SR_PE		/* don't inadvertantly clear pe */
-	mtc0	zero,C0_SR 
-	mfc0	t1,C0_TLBHI	
+	mtc0	zero,C0_SR
+	mfc0	t1,C0_TLBHI
 	sll	a1,TLBHI_PIDSHIFT	/* possition the pid */
 	and	a1,TLBHI_PIDMASK
 	or	a0,a1			/* build entry hi value */
@@ -267,7 +267,7 @@ ENDFRAME(tlbprobe)
 FRAME(resettlb,sp,0,ra)
 #if __mips == 1
 	.set	noreorder
-	mfc0	t0,C0_TLBHI		# fetch the current hi 
+	mfc0	t0,C0_TLBHI		# fetch the current hi
 	mfc0	v0,C0_SR		# fetch the status reg.
 	li	t2,K0BASE&TLBHI_VPNMASK
 	and	v0,~SR_PE		# dont inadvertantly clear PE
@@ -325,13 +325,13 @@ FRAME(map_tlb,sp,0,ra)
 
 	mtc0	zero,C0_SR
 	mtc0	a1,C0_TLBHI		# set the hi entry
-	mtc0	a2,C0_TLBLO		# set the lo entry 
+	mtc0	a2,C0_TLBLO		# set the lo entry
 	mtc0	a0,C0_INX		# load the index
 	nop
 	tlbwi				# put the hi/lo in tlb entry indexed
 	nop
-	mtc0	a3,C0_TLBHI		# put back the tlb hi reg 
-	mtc0	v0,C0_SR		# restore the status register 
+	mtc0	a3,C0_TLBHI		# put back the tlb hi reg
+	mtc0	v0,C0_SR		# restore the status register
 	j	ra
 	nop
 	.set	reorder
@@ -353,7 +353,7 @@ FRAME(map_tlb4000,sp,0,ra)
 	mfc0	t1,C0_TLBHI		# save current TLBPID
 	mfc0	v0,C0_SR		# save SR and disable interrupts
 	mtc0	zero,C0_SR
-	mtc0	t2,C0_PAGEMASK		# set 
+	mtc0	t2,C0_PAGEMASK		# set
 	mtc0	a1,C0_TLBHI		# set VPN and TLBPID
 	mtc0	a2,C0_TLBLO0		# set PPN and access bits
 	mtc0	a3,C0_TLBLO1		# set PPN and access bits
diff --git a/c/src/lib/libbsp/mips/rbtx4925/console/console-io.c b/c/src/lib/libbsp/mips/rbtx4925/console/console-io.c
index 8a22a1ba1e..99a4bb4218 100644
--- a/c/src/lib/libbsp/mips/rbtx4925/console/console-io.c
+++ b/c/src/lib/libbsp/mips/rbtx4925/console/console-io.c
@@ -71,7 +71,7 @@ rtems_device_driver console_initialize(
     major,
     (rtems_device_minor_number) 0
   );
- 
+
   if (status != RTEMS_SUCCESSFUL)
     rtems_fatal_error_occurred(status);
 
@@ -168,7 +168,7 @@ rtems_device_driver console_open(
 #endif
   return RTEMS_SUCCESSFUL;
 }
- 
+
 /*
  *  Close entry point
  */
@@ -200,7 +200,7 @@ rtems_device_driver console_read(
   char *buffer;
   int maximum;
   int count = 0;
- 
+
   rw_args = (rtems_libio_rw_args_t *) arg;
 
   buffer = rw_args->buffer;
@@ -219,7 +219,7 @@ rtems_device_driver console_read(
 }
 
 /*
- * write bytes to the serial port. Stdout and stderr are the same. 
+ * write bytes to the serial port. Stdout and stderr are the same.
  */
 
 rtems_device_driver console_write(
diff --git a/c/src/lib/libbsp/mips/rbtx4925/start/start.S b/c/src/lib/libbsp/mips/rbtx4925/start/start.S
index 7127e6924b..9240fb610e 100644
--- a/c/src/lib/libbsp/mips/rbtx4925/start/start.S
+++ b/c/src/lib/libbsp/mips/rbtx4925/start/start.S
@@ -21,7 +21,7 @@ COPYRIGHT IDT CORPORATION 1996
 LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 
   $Id$
-*/ 
+*/
 
 /*************************************************************************
 **
@@ -38,10 +38,10 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #warning Call to boot_card has changed and needs checking.
 #warning The call is "void boot_card(const char* cmdline);"
 #warning Please check and remove these warnings.
-	
-	.extern	mon_flush_cache		
 
-#if 0	
+	.extern	mon_flush_cache
+
+#if 0
 	.extern _fdata,4		/* this is defined by the linker */
 	.extern _edata,4		/* this is defined by the linker */
 	.extern _idata,4		/* this is defined by the linker */
@@ -59,8 +59,8 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define TMP_STKSIZE  1024
 
 /*
-** P_STACKSIZE is the size of the Prom Stack. 
-** the prom stack grows downward 
+** P_STACKSIZE is the size of the Prom Stack.
+** the prom stack grows downward
 */
 #define	P_STACKSIZE	0x2000   /* sets stack size to 8k */
 
@@ -76,7 +76,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 **		c) Clear all IntMask Enables
 **		d) Set kernel/disabled mode
 **	2)  Initialize Cause Register
-**		a)  clear software interrupt bits       
+**		a)  clear software interrupt bits
 **	3)  Determine FPU installed or not
 **		if not, clear CoProcessor 1 usable bit
 **	4)  Initialize data areas. Clear bss area.
@@ -88,15 +88,15 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 **	9)  Flush Instruction and Data caches
 ** 	10)  If there is a Translation Lookaside Buffer, Clear the TLB
 ** 	11)  Execute initialization code if the IDT/c library is to be used
-** 
+**
 ** 	12)  Jump to user's "main()"
 ** 	13)  Jump to promexit
 **
-**	IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally. 
+**	IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally.
 **	This is used to mark code specific to R3xxx or R4xxx processors.
-**	IDT/C 6.x defines __mips to be the ISA level for which we're 
-**	generating code. This is used to make sure the stack etc. is 
-**	double word aligned, when using -mips3 (default) or -mips2, 
+**	IDT/C 6.x defines __mips to be the ISA level for which we're
+**	generating code. This is used to make sure the stack etc. is
+**	double word aligned, when using -mips3 (default) or -mips2,
 **	when compiling with IDT/C6.x
 **
 ***************************************************************************/
@@ -119,10 +119,10 @@ FRAME(start,sp,0,ra)
 	mtc0	v0,C0_CONFIG
 
 /*
-**	check to see if a fpu is really plugged in 
+**	check to see if a fpu is really plugged in
 */
 	li	t3,0xaaaa5555		/*  put a's and 5's in t3	*/
-	mtc1	t3,fp0			/* try to write them into fp0   */	
+	mtc1	t3,fp0			/* try to write them into fp0   */
 	mtc1	zero,fp1		/* try to write zero in fp	*/
 	mfc1	t0,fp0
 	mfc1	t1,fp1
@@ -140,7 +140,7 @@ FRAME(start,sp,0,ra)
 
 	mtc0	v0, C0_SR		/* reset status register */
 2:
-	la  	gp, _gp			/* Initialize gp register (pointer to "small" data)*/			
+	la  	gp, _gp			/* Initialize gp register (pointer to "small" data)*/
 
 #if 0
 					/* Initialize data sections from "rom" copy */
@@ -160,7 +160,7 @@ FRAME(start,sp,0,ra)
 	la	v1,end 			/* end of bss */
 4:	sw	zero,0(v0)
 	bltu	v0,v1,4b
-	add	v0,4 
+	add	v0,4
 
 
 /************************************************************************
@@ -173,7 +173,7 @@ FRAME(start,sp,0,ra)
 **
 *************************************************************************/
 	/* For MIPS 3, we need to be sure that the stack is aligned on a
-	 * double word boundary. 
+	 * double word boundary.
 	 */
 	andi	t0, v0, 0x7
 	beqz	t0, 11f   /* Last three bits Zero, already aligned */
@@ -185,16 +185,16 @@ FRAME(start,sp,0,ra)
 	add	v1, v0, TMP_STKSIZE 	/* end of bss + length of tmp stack */
 	sub	v1, v1, (4*4)		/* overhead */
 	move	sp, v1			/* set sp to top of stack */
-4:	sw	zero, 0(v0)  
+4:	sw	zero, 0(v0)
 	bltu	v0, v1, 4b		/* clear out temp stack */
-	add	v0, 4 
-	
-/* 	jal	init_exc_vecs */		/* install exception handlers */ 
+	add	v0, 4
+
+/* 	jal	init_exc_vecs */		/* install exception handlers */
 /*	nop */				/* MUST do before memory probes */
 
 					/* Force processor into uncached space during memory/cache probes */
 	la	v0, 5f
-	li	v1, K1BASE		
+	li	v1, K1BASE
 	or	v0, v1
 	j	v0
 	nop
@@ -216,7 +216,7 @@ FRAME(start,sp,0,ra)
 	move	v0, a0			/* mem_size */
 
 	/* For MIPS 3, we need to be sure that the stack (and hence v0
-	 * here) is aligned on a double word boundary. 
+	 * here) is aligned on a double word boundary.
 	 */
 	andi	t0, v0, 0x7
 	beqz	t0, 12f   /* Last three bits Zero, already aligned */
@@ -228,9 +228,9 @@ FRAME(start,sp,0,ra)
 
 /**************************************************************************
 **
-**  Permanent Stack - now know top of memory, put permanent stack there	
+**  Permanent Stack - now know top of memory, put permanent stack there
 **
-***************************************************************************/ 
+***************************************************************************/
 
 	la	t2, _fbss		/* cache mode as linked */
 	and	t2, 0xF0000000		/* isolate segment */
@@ -244,9 +244,9 @@ FRAME(start,sp,0,ra)
 	move	v1, v0
 	subu	v1, P_STACKSIZE 	/* clear requested stack size */
 
-7:	sw	zero, 0(v1)		/* clear P_STACKSIZE  stack */ 
+7:	sw	zero, 0(v1)		/* clear P_STACKSIZE  stack */
 	bltu	v1,v0,7b
-	add	v1, 4 
+	add	v1, 4
 
 
 /* Invalidate data cache*/
@@ -286,12 +286,12 @@ FRAME(start,sp,0,ra)
 2:	mtc0	t2, C0_CONFIG		/* set C0_Config */
 	nop
 
-/* Lock first 4k of PMON into instruction cache. This includes interrupt service code which 
+/* Lock first 4k of PMON into instruction cache. This includes interrupt service code which
  we don't want to run out of slow flash device. */
 
 	la	t0,0x9fc00000
 	li	t1, 0x1000
-	
+
 	move	t3, t0
 	addu	t1, t0, t1
 1:	bge	t0, t1, 2f
@@ -314,7 +314,7 @@ FRAME(start,sp,0,ra)
 
 /*
 ** Clear Translation Lookaside Buffer (TLB)
-*/ 
+*/
 	jal	init_tlb		/* clear the tlb */
 
 /*
@@ -331,7 +331,7 @@ FRAME(start,sp,0,ra)
 1:
 	beq	zero,zero,1b
 	nop
-	
+
 ENDFRAME(start)
 
 /*
@@ -349,7 +349,7 @@ FRAME(_sys_exit,sp,0,ra)
 13:
 	b	13b				# but loop back just in-case
 	nop
-	
+
 ENDFRAME(_sys_exit)
 
 
diff --git a/c/src/lib/libbsp/mips/rbtx4925/startup/bspstart.c b/c/src/lib/libbsp/mips/rbtx4925/startup/bspstart.c
index 1cd943bd00..4577fd97e2 100644
--- a/c/src/lib/libbsp/mips/rbtx4925/startup/bspstart.c
+++ b/c/src/lib/libbsp/mips/rbtx4925/startup/bspstart.c
@@ -16,7 +16,7 @@
 
 #include <bsp.h>
 #include <libcpu/isr_entries.h>
- 
+
 /*
  *  bsp_start
  *
diff --git a/c/src/lib/libbsp/mips/rbtx4925/startup/exception.S b/c/src/lib/libbsp/mips/rbtx4925/startup/exception.S
index 7efe6c5583..d4904e6439 100644
--- a/c/src/lib/libbsp/mips/rbtx4925/startup/exception.S
+++ b/c/src/lib/libbsp/mips/rbtx4925/startup/exception.S
@@ -137,7 +137,7 @@ void _ISR_Handler()
 FRAME(rbtx4925_ISR_Handler,sp,0,ra)
 	.set noreorder
 
-#if 0	
+#if 0
 /* Activate TX4925 PIO19 signal for diagnostics */
 	lui	k0,0xff1f
 	ori	k0,k0,0xf500
@@ -148,7 +148,7 @@ FRAME(rbtx4925_ISR_Handler,sp,0,ra)
 	ori	k0,k0,0xf500
 	sw	k1,(k0)
 #endif
-	
+
 	mfc0 k0,C0_CAUSE	/* Determine if an interrupt generated this exception */
 	nop
 	and k1,k0,CAUSE_EXCMASK
@@ -190,7 +190,7 @@ _chk_int:
         /* wastes a lot of stack space for context?? */
 	ADDIU    sp,sp,-EXCP_STACK_SIZE
 
-        STREG ra, R_RA*R_SZ(sp)  /* store ra on the stack */ 
+        STREG ra, R_RA*R_SZ(sp)  /* store ra on the stack */
         STREG v0, R_V0*R_SZ(sp)
         STREG v1, R_V1*R_SZ(sp)
         STREG a0, R_A0*R_SZ(sp)
@@ -207,13 +207,13 @@ _chk_int:
         STREG t7, R_T7*R_SZ(sp)
         mflo  t0
         STREG t8, R_T8*R_SZ(sp)
-        STREG t0, R_MDLO*R_SZ(sp) 
+        STREG t0, R_MDLO*R_SZ(sp)
         STREG t9, R_T9*R_SZ(sp)
         mfhi  t0
         STREG gp, R_GP*R_SZ(sp)
-        STREG t0, R_MDHI*R_SZ(sp) 
+        STREG t0, R_MDHI*R_SZ(sp)
         STREG fp, R_FP*R_SZ(sp)
-	
+
         .set noat
         STREG AT, R_AT*R_SZ(sp)
         .set at
@@ -287,7 +287,7 @@ _chk_int:
 	mtc0 t1,C0_SR
 	nop
 #endif
-	
+
 _ISR_Handler_cleanup:
 
   /*
@@ -317,7 +317,7 @@ _ISR_Handler_cleanup:
    *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
    *    restore stack
    *  #endif
-   *  
+   *
    *  if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing )
    *    goto the label "exit interrupt (simple case)"
    */
@@ -351,7 +351,7 @@ _ISR_Handler_cleanup:
 	/* save off our stack frame so the context switcher can get to it */
 	la	t0,__exceptionStackFrame
 	STREG	sp,(t0)
-					
+
         jal     _Thread_Dispatch
         NOP
 
@@ -361,7 +361,7 @@ _ISR_Handler_cleanup:
 	STREG	zero,(t0)
 	NOP
 
-/* 
+/*
 ** turn interrupts back off while we restore context so
 ** a badly timed interrupt won't accidentally mess things up
 */
@@ -375,7 +375,7 @@ _ISR_Handler_cleanup:
 
         mtc0    t0, C0_SR
 	NOP
-	
+
   /*
    *  prepare to get out of interrupt
    *  return from interrupt  (maybe to _ISR_Dispatch)
@@ -391,7 +391,7 @@ _ISR_Handler_exit:
         LDREG t8, R_MDLO*R_SZ(sp)
         LDREG t0, R_T0*R_SZ(sp)
         mtlo  t8
-        LDREG t8, R_MDHI*R_SZ(sp)           
+        LDREG t8, R_MDHI*R_SZ(sp)
         LDREG t1, R_T1*R_SZ(sp)
         mthi  t8
         LDREG t2, R_T2*R_SZ(sp)
@@ -411,10 +411,10 @@ _ISR_Handler_exit:
         LDREG a3, R_A3*R_SZ(sp)
         LDREG v1, R_V1*R_SZ(sp)
         LDREG v0, R_V0*R_SZ(sp)
-	
+
         LDREG k1, R_EPC*R_SZ(sp)
 	mtc0  k1,C0_EPC
-	
+
 	.set noat
         LDREG     AT, R_AT*R_SZ(sp)
         .set at
@@ -428,7 +428,7 @@ _ISR_Handler_quick_exit:
 
 #if 0
 	.global	int7_isr
-	.extern	Interrupt_7_isr	
+	.extern	Interrupt_7_isr
 int7_isr:
 	/* Verify interrupt is from Timer */
         la      k0,IRCS		/* read Interrupt Current Status register */
@@ -464,7 +464,7 @@ FRAME(_BRK_Handler,sp,0,ra)
 	la	k0,INT_CFG3
 	sw	k1,(k0)
 #endif
-	
+
 	la  k0,_brk_esr_link	/* Jump to next exception handler in PMON exception chain */
 	lw  k0,(k0)
 	lw  k0,4(k0)
@@ -492,7 +492,7 @@ FRAME(init_exc_vecs,sp,0,ra)
 	.set noreorder
 
 	.extern mon_onintr
-	
+
 /* Install interrupt handler in PMON exception handling chain */
 
 	addiu	sp,sp,-8
@@ -522,7 +522,7 @@ ENDFRAME(init_exc_vecs)
 */
 FRAME(enable_int7,sp,0,ra)
 	.set noreorder
-	
+
 	la	t0,IRDM1	# Set interrupt controller detection mode (bits 2-3 = 0 for int 7 active low)
 	li	t1,0x0
 	sw	t1,(t0)
@@ -530,7 +530,7 @@ FRAME(enable_int7,sp,0,ra)
 	la	t0,IRLVL4	# Set interrupt controller level (bit 8-10 = 2 for int 7 at level 2)
 	li	t1,0x200
 	sw	t1,(t0)
-	
+
 	la	t0,IRMSK	# Set interrupt controller mask
 	li	t1,0x0
 	sw	t1,(t0)
@@ -566,7 +566,7 @@ ENDFRAME(disable_int7)
 *  tx4925exception:
 *       Diagnostic code that can be hooked to PMON interrupt handler.
 *       Generates pulse on PIO22 pin.
-*	Called from _exception code in PMON (see mips.s of PMON). 
+*	Called from _exception code in PMON (see mips.s of PMON).
 *	Return address is located in k1.
 */
 FRAME(tx4925exception,sp,0,ra)
@@ -609,7 +609,7 @@ ENDFRAME(tx4925exception)
 	.data
 
 k1tmp:	.word	0	/* Temporary strage for K1 during interrupt service */
-	
+
 /*************************************************************
 *
 * Exception handler links, used in PMON exception handler chains
@@ -619,7 +619,7 @@ k1tmp:	.word	0	/* Temporary strage for K1 during interrupt service */
 _int_esr_link:
 	.word	0
 	.word	rbtx4925_ISR_Handler
-	
+
 	/* Break exception service routine link */
 	.global	_brk_esr_link
 _brk_esr_link:
@@ -627,5 +627,5 @@ _brk_esr_link:
 	.word	_BRK_Handler
 
 
-	
+
 
diff --git a/c/src/lib/libbsp/mips/rbtx4925/startup/idttlb.S b/c/src/lib/libbsp/mips/rbtx4925/startup/idttlb.S
index ed8517363c..d8800ae7ee 100644
--- a/c/src/lib/libbsp/mips/rbtx4925/startup/idttlb.S
+++ b/c/src/lib/libbsp/mips/rbtx4925/startup/idttlb.S
@@ -186,7 +186,7 @@ ENDFRAME(ret_tlbhi)
 FRAME(ret_tlbpid,sp,0,ra)
 #if __mips == 1
 	.set	noreorder
-	mfc0	v0,C0_TLBHI		# fetch tlb high 
+	mfc0	v0,C0_TLBHI		# fetch tlb high
 	nop
 	and	v0,TLBHI_PIDMASK	# isolate and position
 	srl	v0,TLBHI_PIDSHIFT
@@ -219,8 +219,8 @@ FRAME(tlbprobe,sp,0,ra)
 	mfc0	t0,C0_SR		/* fetch status reg */
 	and	a0,TLBHI_VPNMASK	/* isolate just the vpn */
 	and	t0,~SR_PE		/* don't inadvertantly clear pe */
-	mtc0	zero,C0_SR 
-	mfc0	t1,C0_TLBHI	
+	mtc0	zero,C0_SR
+	mfc0	t1,C0_TLBHI
 	sll	a1,TLBHI_PIDSHIFT	/* possition the pid */
 	and	a1,TLBHI_PIDMASK
 	or	a0,a1			/* build entry hi value */
@@ -271,7 +271,7 @@ ENDFRAME(tlbprobe)
 FRAME(resettlb,sp,0,ra)
 #if __mips == 1
 	.set	noreorder
-	mfc0	t0,C0_TLBHI		# fetch the current hi 
+	mfc0	t0,C0_TLBHI		# fetch the current hi
 	mfc0	v0,C0_SR		# fetch the status reg.
 	li	t2,K0BASE&TLBHI_VPNMASK
 	and	v0,~SR_PE		# dont inadvertantly clear PE
@@ -329,13 +329,13 @@ FRAME(map_tlb,sp,0,ra)
 
 	mtc0	zero,C0_SR
 	mtc0	a1,C0_TLBHI		# set the hi entry
-	mtc0	a2,C0_TLBLO		# set the lo entry 
+	mtc0	a2,C0_TLBLO		# set the lo entry
 	mtc0	a0,C0_INX		# load the index
 	nop
 	tlbwi				# put the hi/lo in tlb entry indexed
 	nop
-	mtc0	a3,C0_TLBHI		# put back the tlb hi reg 
-	mtc0	v0,C0_SR		# restore the status register 
+	mtc0	a3,C0_TLBHI		# put back the tlb hi reg
+	mtc0	v0,C0_SR		# restore the status register
 	j	ra
 	nop
 	.set	reorder
@@ -357,7 +357,7 @@ FRAME(map_tlb4000,sp,0,ra)
 	mfc0	t1,C0_TLBHI		# save current TLBPID
 	mfc0	v0,C0_SR		# save SR and disable interrupts
 	mtc0	zero,C0_SR
-	mtc0	t2,C0_PAGEMASK		# set 
+	mtc0	t2,C0_PAGEMASK		# set
 	mtc0	a1,C0_TLBHI		# set VPN and TLBPID
 	mtc0	a2,C0_TLBLO0		# set PPN and access bits
 	mtc0	a3,C0_TLBLO1		# set PPN and access bits
diff --git a/c/src/lib/libbsp/mips/rbtx4938/clock/yamon_api.h b/c/src/lib/libbsp/mips/rbtx4938/clock/yamon_api.h
index 70853f5d52..3a4a6b7698 100644
--- a/c/src/lib/libbsp/mips/rbtx4938/clock/yamon_api.h
+++ b/c/src/lib/libbsp/mips/rbtx4938/clock/yamon_api.h
@@ -8,7 +8,7 @@
  * ######################################################################
  *
  * mips_start_of_legal_notice
- * 
+ *
  * Copyright (c) 2003 MIPS Technologies, Inc. All rights reserved.
  *
  *
@@ -52,9 +52,9 @@
  * and conditions covering this code from MIPS Technologies or an authorized
  * third party.
  *
- * 
+ *
  * mips_end_of_legal_notice
- * 
+ *
  *
  ************************************************************************/
 
@@ -170,7 +170,7 @@ typedef void *t_yamon_ref;
  *  Parameters :
  *  ------------
  *
- *  'rc' (OUT) : Return code 
+ *  'rc' (OUT) : Return code
  *
  *  Return values :
  *  ---------------
@@ -178,7 +178,7 @@ typedef void *t_yamon_ref;
  *  None (never returns)
  *
  ************************************************************************/
-typedef void 
+typedef void
 (*t_yamon_exit)(
     t_yamon_uint32 rc );	/* Return code				*/
 
@@ -207,7 +207,7 @@ typedef void
  *  None
  *
  ************************************************************************/
-typedef void 
+typedef void
 (*t_yamon_print)(
     t_yamon_uint32 port, /* Output port (not used, always tty0)		*/
     const char           *s ); /* String to output				*/
@@ -238,7 +238,7 @@ typedef void
  *  None
  *
  ************************************************************************/
-typedef void 
+typedef void
 (*t_yamon_print_count)(
     t_yamon_uint32 port,	/* Output port (not used, always tty0	*/
     char	   *s,		/* String to output			*/
@@ -357,33 +357,33 @@ typedef void
  *
  *  Registers an exception handler, also known as an "Exception Service
  *  Routine" (ESR) for the specified exception.
- *  
+ *
  *  Two special exception IDs are defined :
  *      YAMON_DEFAULT_HANDLER used for a default ESR.
  *      YAMON_DEFAULT_EJTAG_ESR used for EJTAG exceptions.
- *	
+ *
  *  The default ESR is called if no other ESR is registered
  *  for an exception. If no default ESR is registered, a static
  *  (i.e. not registered) "super default" function is invoked.
  *  This function prints out the registers and halts.
  *
- *  Deregistration of an ESR may be be done by calling this function 
+ *  Deregistration of an ESR may be be done by calling this function
  *  with 'esr' set to NULL.
  *  An ESR can also be deregistered using the 'yamon_deregister_esr'
  *  function.
  *
- *  An ESR may be registered even if a previously registered 
+ *  An ESR may be registered even if a previously registered
  *  ESR has not been deregistered. In this case the previously
  *  registered ESR is lost.
  *
- *  The ESR will get called with registers in the state they were 
- *  when the exception occurred. This includes all CP0 registers and 
+ *  The ESR will get called with registers in the state they were
+ *  when the exception occurred. This includes all CP0 registers and
  *  CPU registers $0..$31, except for k0,k1 ($26,$27).
  *
  *  In case an ESR does not want to handle the exception, it may
  *  call the return function passed in the 'retfunc' parameter.
  *
- *  Case 1 : 'retfunc' called by ESR registered for the 
+ *  Case 1 : 'retfunc' called by ESR registered for the
  *           INTERRUPT exception.
  *
  *  We assume an application has registered this ESR and wants
@@ -396,7 +396,7 @@ typedef void
  *
  *  Case 3 : 'retfunc' is called by the ESR registered as default ESR.
  *
- *  The exception will be handled as though no ESR is registered 
+ *  The exception will be handled as though no ESR is registered
  *  (i.e. the "super default" function is called).
  *
  *  Parameters :
@@ -436,7 +436,7 @@ typedef t_yamon_int32
  *  -------------
  *
  *  Deregisters ESR..
- *  
+ *
  *  Parameters :
  *  ------------
  *
@@ -464,7 +464,7 @@ typedef t_yamon_int32
  *  Description :
  *  -------------
  *
- *  Registers an Interrupt Service Routine (ISR) for the specified 
+ *  Registers an Interrupt Service Routine (ISR) for the specified
  *  CPU interrupt.
  *  The highest service priority is attached to HW-INT5, which is
  *  connected to the CPU-built-in CP0-timer. SW_INT0 gets the lowest
@@ -474,15 +474,15 @@ typedef t_yamon_int32
  *
  *  A special ID is defined :
  *      YAMON_DEFAULT_HANDLER used for a default ISR.
- *	
+ *
  *  The default ISR is called if no other ISR is registered
  *  for a CPU interrupt.
  *
  *  Deregistration of the default ISR may be done by calling
  *  this function with 'isr' set to NULL.
- *  Also, a new default ISR may be registered even if a 
+ *  Also, a new default ISR may be registered even if a
  *  previously registered ISR has not been deregistered.
- *  ISRs for specific CPU interrupts must be deregistered using 
+ *  ISRs for specific CPU interrupts must be deregistered using
  *  'yamon_deregister_cpu_isr'.
  *
  *  Parameters :
@@ -521,7 +521,7 @@ typedef t_yamon_int32
  *  -------------
  *
  *  Deregisters ISR for CPU interrupt.
- *  
+ *
  *  Parameters :
  *  ------------
  *
@@ -549,20 +549,20 @@ typedef t_yamon_int32
  *  Description :
  *  -------------
  *
- *  Registers an Interrupt Service Routine (ISR) for the specified 
- *  source in the interrupt controller. 
+ *  Registers an Interrupt Service Routine (ISR) for the specified
+ *  source in the interrupt controller.
  *
  *  A special ID is defined :
  *      YAMON_DEFAULT_HANDLER used for a default ISR.
- *	
+ *
  *  The default ISR is called if no other ISR is registered
  *  for an interrupt.
  *
  *  Deregistration of the default ISR may be done by calling
  *  this function with 'isr' set to NULL.
- *  Also, a new default ISR may be registered even if a 
+ *  Also, a new default ISR may be registered even if a
  *  previously registered ISR has not been deregistered.
- *  ISRs for specific interrupts must be deregistered using 
+ *  ISRs for specific interrupts must be deregistered using
  *  'yamon_deregister_ic_isr'.
  *
  *  Parameters :
@@ -601,7 +601,7 @@ typedef t_yamon_int32
  *  -------------
  *
  *  Deregisters ISR for source in interrupt controller.
- *  
+ *
  *  Parameters :
  *  ------------
  *
diff --git a/c/src/lib/libbsp/mips/rbtx4938/console/console-io.c b/c/src/lib/libbsp/mips/rbtx4938/console/console-io.c
index 73d81c921d..f74c6b22e9 100644
--- a/c/src/lib/libbsp/mips/rbtx4938/console/console-io.c
+++ b/c/src/lib/libbsp/mips/rbtx4938/console/console-io.c
@@ -73,7 +73,7 @@ rtems_device_driver console_initialize(
     major,
     (rtems_device_minor_number) 0
   );
- 
+
   if (status != RTEMS_SUCCESSFUL)
     rtems_fatal_error_occurred(status);
 
@@ -174,7 +174,7 @@ rtems_device_driver console_open(
 #endif
   return RTEMS_SUCCESSFUL;
 }
- 
+
 /*
  *  Close entry point
  */
@@ -206,7 +206,7 @@ rtems_device_driver console_read(
   char *buffer;
   int maximum;
   int count = 0;
- 
+
   rw_args = (rtems_libio_rw_args_t *) arg;
 
   buffer = rw_args->buffer;
@@ -225,7 +225,7 @@ rtems_device_driver console_read(
 }
 
 /*
- * write bytes to the serial port. Stdout and stderr are the same. 
+ * write bytes to the serial port. Stdout and stderr are the same.
  */
 
 rtems_device_driver console_write(
diff --git a/c/src/lib/libbsp/mips/rbtx4938/console/yamon_api.h b/c/src/lib/libbsp/mips/rbtx4938/console/yamon_api.h
index 70853f5d52..3a4a6b7698 100644
--- a/c/src/lib/libbsp/mips/rbtx4938/console/yamon_api.h
+++ b/c/src/lib/libbsp/mips/rbtx4938/console/yamon_api.h
@@ -8,7 +8,7 @@
  * ######################################################################
  *
  * mips_start_of_legal_notice
- * 
+ *
  * Copyright (c) 2003 MIPS Technologies, Inc. All rights reserved.
  *
  *
@@ -52,9 +52,9 @@
  * and conditions covering this code from MIPS Technologies or an authorized
  * third party.
  *
- * 
+ *
  * mips_end_of_legal_notice
- * 
+ *
  *
  ************************************************************************/
 
@@ -170,7 +170,7 @@ typedef void *t_yamon_ref;
  *  Parameters :
  *  ------------
  *
- *  'rc' (OUT) : Return code 
+ *  'rc' (OUT) : Return code
  *
  *  Return values :
  *  ---------------
@@ -178,7 +178,7 @@ typedef void *t_yamon_ref;
  *  None (never returns)
  *
  ************************************************************************/
-typedef void 
+typedef void
 (*t_yamon_exit)(
     t_yamon_uint32 rc );	/* Return code				*/
 
@@ -207,7 +207,7 @@ typedef void
  *  None
  *
  ************************************************************************/
-typedef void 
+typedef void
 (*t_yamon_print)(
     t_yamon_uint32 port, /* Output port (not used, always tty0)		*/
     const char           *s ); /* String to output				*/
@@ -238,7 +238,7 @@ typedef void
  *  None
  *
  ************************************************************************/
-typedef void 
+typedef void
 (*t_yamon_print_count)(
     t_yamon_uint32 port,	/* Output port (not used, always tty0	*/
     char	   *s,		/* String to output			*/
@@ -357,33 +357,33 @@ typedef void
  *
  *  Registers an exception handler, also known as an "Exception Service
  *  Routine" (ESR) for the specified exception.
- *  
+ *
  *  Two special exception IDs are defined :
  *      YAMON_DEFAULT_HANDLER used for a default ESR.
  *      YAMON_DEFAULT_EJTAG_ESR used for EJTAG exceptions.
- *	
+ *
  *  The default ESR is called if no other ESR is registered
  *  for an exception. If no default ESR is registered, a static
  *  (i.e. not registered) "super default" function is invoked.
  *  This function prints out the registers and halts.
  *
- *  Deregistration of an ESR may be be done by calling this function 
+ *  Deregistration of an ESR may be be done by calling this function
  *  with 'esr' set to NULL.
  *  An ESR can also be deregistered using the 'yamon_deregister_esr'
  *  function.
  *
- *  An ESR may be registered even if a previously registered 
+ *  An ESR may be registered even if a previously registered
  *  ESR has not been deregistered. In this case the previously
  *  registered ESR is lost.
  *
- *  The ESR will get called with registers in the state they were 
- *  when the exception occurred. This includes all CP0 registers and 
+ *  The ESR will get called with registers in the state they were
+ *  when the exception occurred. This includes all CP0 registers and
  *  CPU registers $0..$31, except for k0,k1 ($26,$27).
  *
  *  In case an ESR does not want to handle the exception, it may
  *  call the return function passed in the 'retfunc' parameter.
  *
- *  Case 1 : 'retfunc' called by ESR registered for the 
+ *  Case 1 : 'retfunc' called by ESR registered for the
  *           INTERRUPT exception.
  *
  *  We assume an application has registered this ESR and wants
@@ -396,7 +396,7 @@ typedef void
  *
  *  Case 3 : 'retfunc' is called by the ESR registered as default ESR.
  *
- *  The exception will be handled as though no ESR is registered 
+ *  The exception will be handled as though no ESR is registered
  *  (i.e. the "super default" function is called).
  *
  *  Parameters :
@@ -436,7 +436,7 @@ typedef t_yamon_int32
  *  -------------
  *
  *  Deregisters ESR..
- *  
+ *
  *  Parameters :
  *  ------------
  *
@@ -464,7 +464,7 @@ typedef t_yamon_int32
  *  Description :
  *  -------------
  *
- *  Registers an Interrupt Service Routine (ISR) for the specified 
+ *  Registers an Interrupt Service Routine (ISR) for the specified
  *  CPU interrupt.
  *  The highest service priority is attached to HW-INT5, which is
  *  connected to the CPU-built-in CP0-timer. SW_INT0 gets the lowest
@@ -474,15 +474,15 @@ typedef t_yamon_int32
  *
  *  A special ID is defined :
  *      YAMON_DEFAULT_HANDLER used for a default ISR.
- *	
+ *
  *  The default ISR is called if no other ISR is registered
  *  for a CPU interrupt.
  *
  *  Deregistration of the default ISR may be done by calling
  *  this function with 'isr' set to NULL.
- *  Also, a new default ISR may be registered even if a 
+ *  Also, a new default ISR may be registered even if a
  *  previously registered ISR has not been deregistered.
- *  ISRs for specific CPU interrupts must be deregistered using 
+ *  ISRs for specific CPU interrupts must be deregistered using
  *  'yamon_deregister_cpu_isr'.
  *
  *  Parameters :
@@ -521,7 +521,7 @@ typedef t_yamon_int32
  *  -------------
  *
  *  Deregisters ISR for CPU interrupt.
- *  
+ *
  *  Parameters :
  *  ------------
  *
@@ -549,20 +549,20 @@ typedef t_yamon_int32
  *  Description :
  *  -------------
  *
- *  Registers an Interrupt Service Routine (ISR) for the specified 
- *  source in the interrupt controller. 
+ *  Registers an Interrupt Service Routine (ISR) for the specified
+ *  source in the interrupt controller.
  *
  *  A special ID is defined :
  *      YAMON_DEFAULT_HANDLER used for a default ISR.
- *	
+ *
  *  The default ISR is called if no other ISR is registered
  *  for an interrupt.
  *
  *  Deregistration of the default ISR may be done by calling
  *  this function with 'isr' set to NULL.
- *  Also, a new default ISR may be registered even if a 
+ *  Also, a new default ISR may be registered even if a
  *  previously registered ISR has not been deregistered.
- *  ISRs for specific interrupts must be deregistered using 
+ *  ISRs for specific interrupts must be deregistered using
  *  'yamon_deregister_ic_isr'.
  *
  *  Parameters :
@@ -601,7 +601,7 @@ typedef t_yamon_int32
  *  -------------
  *
  *  Deregisters ISR for source in interrupt controller.
- *  
+ *
  *  Parameters :
  *  ------------
  *
diff --git a/c/src/lib/libbsp/mips/rbtx4938/start/start.S b/c/src/lib/libbsp/mips/rbtx4938/start/start.S
index c0f5ec55e9..735fd923ab 100644
--- a/c/src/lib/libbsp/mips/rbtx4938/start/start.S
+++ b/c/src/lib/libbsp/mips/rbtx4938/start/start.S
@@ -21,7 +21,7 @@ COPYRIGHT IDT CORPORATION 1996
 LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 
   $Id$
-*/ 
+*/
 
 /*************************************************************************
 **
@@ -42,9 +42,9 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 /* The following include file was deprecated */
 /* #include <idtmon.h>	*/
 
-	.extern	mon_flush_cache		
+	.extern	mon_flush_cache
 
-#if 0	
+#if 0
 	.extern _fdata,4		/* this is defined by the linker */
 	.extern _edata,4		/* this is defined by the linker */
 	.extern _idata,4		/* this is defined by the linker */
@@ -59,11 +59,11 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define HARD_CODED_MEM_SIZE	0x1000000	/* RBTX4938 has 16 megabytes of RAM */
 #define PMON_VECTOR 0xbfc00500
 
-#define TMP_STKSIZE  1024 
+#define TMP_STKSIZE  1024
 
 /*
-** P_STACKSIZE is the size of the Prom Stack. 
-** the prom stack grows downward 
+** P_STACKSIZE is the size of the Prom Stack.
+** the prom stack grows downward
 */
 #define	P_STACKSIZE	0x2000   /* sets stack size to 8k */
 
@@ -78,7 +78,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 **		c) Clear all IntMask Enables
 **		d) Set kernel/disabled mode
 **	2)  Initialize Cause Register
-**		a)  clear software interrupt bits       
+**		a)  clear software interrupt bits
 **	3)  Determine FPU installed or not
 **		if not, clear CoProcessor 1 usable bit
 **	4)  Initialize data areas. Clear bss area.
@@ -90,15 +90,15 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 **	9)  Flush Instruction and Data caches
 ** 	10)  If there is a Translation Lookaside Buffer, Clear the TLB
 ** 	11)  Execute initialization code if the IDT/c library is to be used
-** 
+**
 ** 	12)  Jump to user's "main()"
 ** 	13)  Jump to promexit
 **
-**	IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally. 
+**	IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally.
 **	This is used to mark code specific to R3xxx or R4xxx processors.
-**	IDT/C 6.x defines __mips to be the ISA level for which we're 
-**	generating code. This is used to make sure the stack etc. is 
-**	double word aligned, when using -mips3 (default) or -mips2, 
+**	IDT/C 6.x defines __mips to be the ISA level for which we're
+**	generating code. This is used to make sure the stack etc. is
+**	double word aligned, when using -mips3 (default) or -mips2,
 **	when compiling with IDT/C6.x
 **
 ***************************************************************************/
@@ -121,10 +121,10 @@ FRAME(start,sp,0,ra)
 	mtc0	v0,C0_CONFIG
 
 /*
-**	check to see if a fpu is really plugged in 
+**	check to see if a fpu is really plugged in
 */
 	li	t3,0xaaaa5555		/*  put a's and 5's in t3	*/
-	mtc1	t3,fp0			/* try to write them into fp0   */	
+	mtc1	t3,fp0			/* try to write them into fp0   */
 	mtc1	zero,fp1		/* try to write zero in fp	*/
 	mfc1	t0,fp0
 	mfc1	t1,fp1
@@ -142,7 +142,7 @@ FRAME(start,sp,0,ra)
 
 	mtc0	v0, C0_SR		/* reset status register */
 2:
-	la  	gp, _gp			/* Initialize gp register (pointer to "small" data)*/			
+	la  	gp, _gp			/* Initialize gp register (pointer to "small" data)*/
 
 #if 0
 					/* Initialize data sections from "rom" copy */
@@ -162,7 +162,7 @@ FRAME(start,sp,0,ra)
 	la	v1,end 			/* end of bss */
 4:	sw	zero,0(v0)
 	bltu	v0,v1,4b
-	add	v0,4 
+	add	v0,4
 
 
 /************************************************************************
@@ -175,7 +175,7 @@ FRAME(start,sp,0,ra)
 **
 *************************************************************************/
 	/* For MIPS 3, we need to be sure that the stack is aligned on a
-	 * double word boundary. 
+	 * double word boundary.
 	 */
 	andi	t0, v0, 0x7
 	beqz	t0, 11f   /* Last three bits Zero, already aligned */
@@ -187,16 +187,16 @@ FRAME(start,sp,0,ra)
 	add	v1, v0, TMP_STKSIZE 	/* end of bss + length of tmp stack */
 	sub	v1, v1, (4*4)		/* overhead */
 	move	sp, v1			/* set sp to top of stack */
-4:	sw	zero, 0(v0)  
+4:	sw	zero, 0(v0)
 	bltu	v0, v1, 4b		/* clear out temp stack */
-	add	v0, 4 
-	
-/* 	jal	init_exc_vecs */		/* install exception handlers */ 
+	add	v0, 4
+
+/* 	jal	init_exc_vecs */		/* install exception handlers */
 /*	nop */				/* MUST do before memory probes */
 
 					/* Force processor into uncached space during memory/cache probes */
 	la	v0, 5f
-	li	v1, K1BASE		
+	li	v1, K1BASE
 	or	v0, v1
 	j	v0
 	nop
@@ -218,7 +218,7 @@ FRAME(start,sp,0,ra)
 	move	v0, a0			/* mem_size */
 
 	/* For MIPS 3, we need to be sure that the stack (and hence v0
-	 * here) is aligned on a double word boundary. 
+	 * here) is aligned on a double word boundary.
 	 */
 	andi	t0, v0, 0x7
 	beqz	t0, 12f   /* Last three bits Zero, already aligned */
@@ -230,9 +230,9 @@ FRAME(start,sp,0,ra)
 
 /**************************************************************************
 **
-**  Permanent Stack - now know top of memory, put permanent stack there	
+**  Permanent Stack - now know top of memory, put permanent stack there
 **
-***************************************************************************/ 
+***************************************************************************/
 
 	la	t2, _fbss		/* cache mode as linked */
 	and	t2, 0xF0000000		/* isolate segment */
@@ -246,9 +246,9 @@ FRAME(start,sp,0,ra)
 	move	v1, v0
 	subu	v1, P_STACKSIZE 	/* clear requested stack size */
 
-7:	sw	zero, 0(v1)		/* clear P_STACKSIZE  stack */ 
+7:	sw	zero, 0(v1)		/* clear P_STACKSIZE  stack */
 	bltu	v1,v0,7b
-	add	v1, 4 
+	add	v1, 4
 
 
 /* Invalidate data cache*/
@@ -288,12 +288,12 @@ FRAME(start,sp,0,ra)
 2:	mtc0	t2, C0_CONFIG		/* set C0_Config */
 	nop
 
-/* Lock first 4k of PMON into instruction cache. This includes interrupt service code which 
+/* Lock first 4k of PMON into instruction cache. This includes interrupt service code which
  we don't want to run out of slow flash device. */
 
 	la	t0,0x9fc00000
 	li	t1, 0x1000
-	
+
 	move	t3, t0
 	addu	t1, t0, t1
 1:	bge	t0, t1, 2f
@@ -316,7 +316,7 @@ FRAME(start,sp,0,ra)
 
 /*
 ** Clear Translation Lookaside Buffer (TLB)
-*/ 
+*/
 	jal	init_tlb		/* clear the tlb */
 
 /*
@@ -333,7 +333,7 @@ FRAME(start,sp,0,ra)
 1:
 	beq	zero,zero,1b
 	nop
-	
+
 ENDFRAME(start)
 
 /*
@@ -351,7 +351,7 @@ FRAME(_sys_exit,sp,0,ra)
 13:
 	b	13b				# but loop back just in-case
 	nop
-	
+
 ENDFRAME(_sys_exit)
 
 
diff --git a/c/src/lib/libbsp/mips/rbtx4938/startup/exception.S b/c/src/lib/libbsp/mips/rbtx4938/startup/exception.S
index 89b1061668..d5c58fccb9 100644
--- a/c/src/lib/libbsp/mips/rbtx4938/startup/exception.S
+++ b/c/src/lib/libbsp/mips/rbtx4938/startup/exception.S
@@ -137,7 +137,7 @@ void _ISR_Handler()
 FRAME(rbtx4938_ISR_Handler,sp,0,ra)
 	.set noreorder
 
-#if 0	
+#if 0
 /* Activate TX4938 PIO19 signal for diagnostics */
 	lui	k0,0xff1f
 	ori	k0,k0,0xf500
@@ -148,7 +148,7 @@ FRAME(rbtx4938_ISR_Handler,sp,0,ra)
 	ori	k0,k0,0xf500
 	sw	k1,(k0)
 #endif
-	
+
 	mfc0 k0,C0_CAUSE	/* Determine if an interrupt generated this exception */
 	nop
 	and k1,k0,CAUSE_EXCMASK
@@ -190,7 +190,7 @@ _chk_int:
         /* wastes a lot of stack space for context?? */
 	ADDIU    sp,sp,-EXCP_STACK_SIZE
 
-        STREG ra, R_RA*R_SZ(sp)  /* store ra on the stack */ 
+        STREG ra, R_RA*R_SZ(sp)  /* store ra on the stack */
         STREG v0, R_V0*R_SZ(sp)
         STREG v1, R_V1*R_SZ(sp)
         STREG a0, R_A0*R_SZ(sp)
@@ -207,13 +207,13 @@ _chk_int:
         STREG t7, R_T7*R_SZ(sp)
         mflo  t0
         STREG t8, R_T8*R_SZ(sp)
-        STREG t0, R_MDLO*R_SZ(sp) 
+        STREG t0, R_MDLO*R_SZ(sp)
         STREG t9, R_T9*R_SZ(sp)
         mfhi  t0
         STREG gp, R_GP*R_SZ(sp)
-        STREG t0, R_MDHI*R_SZ(sp) 
+        STREG t0, R_MDHI*R_SZ(sp)
         STREG fp, R_FP*R_SZ(sp)
-	
+
         .set noat
         STREG AT, R_AT*R_SZ(sp)
         .set at
@@ -287,7 +287,7 @@ _chk_int:
 	mtc0 t1,C0_SR
 	nop
 #endif
-	
+
 _ISR_Handler_cleanup:
 
   /*
@@ -317,7 +317,7 @@ _ISR_Handler_cleanup:
    *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
    *    restore stack
    *  #endif
-   *  
+   *
    *  if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing )
    *    goto the label "exit interrupt (simple case)"
    */
@@ -351,7 +351,7 @@ _ISR_Handler_cleanup:
 	/* save off our stack frame so the context switcher can get to it */
 	la	t0,__exceptionStackFrame
 	STREG	sp,(t0)
-					
+
         jal     _Thread_Dispatch
         NOP
 
@@ -361,7 +361,7 @@ _ISR_Handler_cleanup:
 	STREG	zero,(t0)
 	NOP
 
-/* 
+/*
 ** turn interrupts back off while we restore context so
 ** a badly timed interrupt won't accidentally mess things up
 */
@@ -375,7 +375,7 @@ _ISR_Handler_cleanup:
 
         mtc0    t0, C0_SR
 	NOP
-	
+
   /*
    *  prepare to get out of interrupt
    *  return from interrupt  (maybe to _ISR_Dispatch)
@@ -391,7 +391,7 @@ _ISR_Handler_exit:
         LDREG t8, R_MDLO*R_SZ(sp)
         LDREG t0, R_T0*R_SZ(sp)
         mtlo  t8
-        LDREG t8, R_MDHI*R_SZ(sp)           
+        LDREG t8, R_MDHI*R_SZ(sp)
         LDREG t1, R_T1*R_SZ(sp)
         mthi  t8
         LDREG t2, R_T2*R_SZ(sp)
@@ -411,10 +411,10 @@ _ISR_Handler_exit:
         LDREG a3, R_A3*R_SZ(sp)
         LDREG v1, R_V1*R_SZ(sp)
         LDREG v0, R_V0*R_SZ(sp)
-	
+
         LDREG k1, R_EPC*R_SZ(sp)
 	mtc0  k1,C0_EPC
-	
+
 	.set noat
         LDREG     AT, R_AT*R_SZ(sp)
         .set at
@@ -428,7 +428,7 @@ _ISR_Handler_quick_exit:
 
 #if 0
 	.global	int7_isr
-	.extern	Interrupt_7_isr	
+	.extern	Interrupt_7_isr
 int7_isr:
 	/* Verify interrupt is from Timer */
         la      k0,IRCS		/* read Interrupt Current Status register */
@@ -464,7 +464,7 @@ FRAME(_BRK_Handler,sp,0,ra)
 	la	k0,INT_CFG3
 	sw	k1,(k0)
 #endif
-	
+
 	la  k0,_brk_esr_link	/* Jump to next exception handler in PMON exception chain */
 	lw  k0,(k0)
 	lw  k0,4(k0)
@@ -492,7 +492,7 @@ FRAME(init_exc_vecs,sp,0,ra)
 	.set noreorder
 
 	.extern mon_onintr
-	
+
 /* Install interrupt handler in PMON exception handling chain */
 
 	addiu	sp,sp,-8
@@ -522,7 +522,7 @@ ENDFRAME(init_exc_vecs)
 */
 FRAME(enable_int7,sp,0,ra)
 	.set noreorder
-	
+
 	la	t0,IRDM1	# Set interrupt controller detection mode (bits 2-3 = 0 for int 7 active low)
 	li	t1,0x0
 	sw	t1,(t0)
@@ -530,7 +530,7 @@ FRAME(enable_int7,sp,0,ra)
 	la	t0,IRLVL4	# Set interrupt controller level (bit 8-10 = 2 for int 7 at level 2)
 	li	t1,0x200
 	sw	t1,(t0)
-	
+
 	la	t0,IRMSK	# Set interrupt controller mask
 	li	t1,0x0
 	sw	t1,(t0)
@@ -566,7 +566,7 @@ ENDFRAME(disable_int7)
 *  tx4938exception:
 *       Diagnostic code that can be hooked to PMON interrupt handler.
 *       Generates pulse on PIO22 pin.
-*	Called from _exception code in PMON (see mips.s of PMON). 
+*	Called from _exception code in PMON (see mips.s of PMON).
 *	Return address is located in k1.
 */
 FRAME(tx4938exception,sp,0,ra)
@@ -609,7 +609,7 @@ ENDFRAME(tx4938exception)
 	.data
 
 k1tmp:	.word	0	/* Temporary strage for K1 during interrupt service */
-	
+
 /*************************************************************
 *
 * Exception handler links, used in PMON exception handler chains
@@ -619,7 +619,7 @@ k1tmp:	.word	0	/* Temporary strage for K1 during interrupt service */
 _int_esr_link:
 	.word	0
 	.word	rbtx4938_ISR_Handler
-	
+
 	/* Break exception service routine link */
 	.global	_brk_esr_link
 _brk_esr_link:
@@ -627,5 +627,5 @@ _brk_esr_link:
 	.word	_BRK_Handler
 
 
-	
+
 
diff --git a/c/src/lib/libbsp/mips/rbtx4938/startup/idttlb.S b/c/src/lib/libbsp/mips/rbtx4938/startup/idttlb.S
index ed8517363c..d8800ae7ee 100644
--- a/c/src/lib/libbsp/mips/rbtx4938/startup/idttlb.S
+++ b/c/src/lib/libbsp/mips/rbtx4938/startup/idttlb.S
@@ -186,7 +186,7 @@ ENDFRAME(ret_tlbhi)
 FRAME(ret_tlbpid,sp,0,ra)
 #if __mips == 1
 	.set	noreorder
-	mfc0	v0,C0_TLBHI		# fetch tlb high 
+	mfc0	v0,C0_TLBHI		# fetch tlb high
 	nop
 	and	v0,TLBHI_PIDMASK	# isolate and position
 	srl	v0,TLBHI_PIDSHIFT
@@ -219,8 +219,8 @@ FRAME(tlbprobe,sp,0,ra)
 	mfc0	t0,C0_SR		/* fetch status reg */
 	and	a0,TLBHI_VPNMASK	/* isolate just the vpn */
 	and	t0,~SR_PE		/* don't inadvertantly clear pe */
-	mtc0	zero,C0_SR 
-	mfc0	t1,C0_TLBHI	
+	mtc0	zero,C0_SR
+	mfc0	t1,C0_TLBHI
 	sll	a1,TLBHI_PIDSHIFT	/* possition the pid */
 	and	a1,TLBHI_PIDMASK
 	or	a0,a1			/* build entry hi value */
@@ -271,7 +271,7 @@ ENDFRAME(tlbprobe)
 FRAME(resettlb,sp,0,ra)
 #if __mips == 1
 	.set	noreorder
-	mfc0	t0,C0_TLBHI		# fetch the current hi 
+	mfc0	t0,C0_TLBHI		# fetch the current hi
 	mfc0	v0,C0_SR		# fetch the status reg.
 	li	t2,K0BASE&TLBHI_VPNMASK
 	and	v0,~SR_PE		# dont inadvertantly clear PE
@@ -329,13 +329,13 @@ FRAME(map_tlb,sp,0,ra)
 
 	mtc0	zero,C0_SR
 	mtc0	a1,C0_TLBHI		# set the hi entry
-	mtc0	a2,C0_TLBLO		# set the lo entry 
+	mtc0	a2,C0_TLBLO		# set the lo entry
 	mtc0	a0,C0_INX		# load the index
 	nop
 	tlbwi				# put the hi/lo in tlb entry indexed
 	nop
-	mtc0	a3,C0_TLBHI		# put back the tlb hi reg 
-	mtc0	v0,C0_SR		# restore the status register 
+	mtc0	a3,C0_TLBHI		# put back the tlb hi reg
+	mtc0	v0,C0_SR		# restore the status register
 	j	ra
 	nop
 	.set	reorder
@@ -357,7 +357,7 @@ FRAME(map_tlb4000,sp,0,ra)
 	mfc0	t1,C0_TLBHI		# save current TLBPID
 	mfc0	v0,C0_SR		# save SR and disable interrupts
 	mtc0	zero,C0_SR
-	mtc0	t2,C0_PAGEMASK		# set 
+	mtc0	t2,C0_PAGEMASK		# set
 	mtc0	a1,C0_TLBHI		# set VPN and TLBPID
 	mtc0	a2,C0_TLBLO0		# set PPN and access bits
 	mtc0	a3,C0_TLBLO1		# set PPN and access bits
diff --git a/c/src/lib/libbsp/mips/shared/gdbstub/mips-stub.c b/c/src/lib/libbsp/mips/shared/gdbstub/mips-stub.c
index 9b16f94db8..f88ab9b6e1 100644
--- a/c/src/lib/libbsp/mips/shared/gdbstub/mips-stub.c
+++ b/c/src/lib/libbsp/mips/shared/gdbstub/mips-stub.c
@@ -118,7 +118,7 @@
 *       As an example, "0* " means the same thing as "0000".
 *
 *******************************************************************************/
-
+
 
 #include <string.h>
 #include <signal.h>
@@ -255,7 +255,7 @@ static struct z0break z0break_arr[BREAKNUM];
 static struct z0break *z0break_avail = NULL;
 static struct z0break *z0break_list  = NULL;
 
-
+
 /*
  * Convert an int to hex.
  */
@@ -334,7 +334,7 @@ mem2hex (void *_addr, int length, char *buf)
   return (buf);
 }
 
-
+
 /*
  * Convert a hex character to an int.
  */
@@ -531,7 +531,7 @@ bin2mem (
   return mem;
 }
 
-
+
 /*
  * Scan the input stream for a sequence for the form $<data>#<checksum>.
  */
@@ -649,7 +649,7 @@ putpacket (char *buffer)
   while  (getAck () != '+');
 }
 
-
+
 /*
  * Saved instruction data for single step support
  */
@@ -808,7 +808,7 @@ doSStep (void)
    return;
 }
 
-
+
 /*
  * Translate the R4600 exception code into a Unix-compatible signal.
  */
@@ -917,7 +917,7 @@ void gdb_stub_report_exception_info(
    *optr++ = '\0';
 }
 
-
+
 
 /*
  * Scratch frame used to retrieve contexts for different threads, so as
author	Ralf Corsepius <ralf.corsepius@rtems.org>	2009-11-29 15:27:07 +0000
committer	Ralf Corsepius <ralf.corsepius@rtems.org>	2009-11-29 15:27:07 +0000
commit	efdfd48add0e7f5549ce99a3cabf6aed9f170230 (patch)
tree	396c3c8ae3a969c7fe1b1d3f334e4b2bc442ff37 /c/src/lib/libbsp/mips
parent	Whitespace removal. (diff)
download	rtems-efdfd48add0e7f5549ce99a3cabf6aed9f170230.tar.bz2