diff options
| author | Chris Johns <chrisj@rtems.org> | 2006-09-11 11:52:08 +0000 |
|---|---|---|
| committer | Chris Johns <chrisj@rtems.org> | 2006-09-11 11:52:08 +0000 |
| commit | 8f1e494813360f49be23eb717ce9229198d2e21a (patch) | |
| tree | 83fd09e78c0d2a7eeaf766bbf9e2767ce8dcfab3 /c/src/lib/libbsp/mips | |
| parent | 2006-09-08 Kate Feng <feng1@bnl.gov> (diff) | |
| download | rtems-8f1e494813360f49be23eb717ce9229198d2e21a.tar.bz2 | |
Remove extra CRLF.
Diffstat (limited to 'c/src/lib/libbsp/mips')
| -rw-r--r-- | c/src/lib/libbsp/mips/hurricane/include/usc.h | 64 |
1 files changed, 32 insertions, 32 deletions
diff --git a/c/src/lib/libbsp/mips/hurricane/include/usc.h b/c/src/lib/libbsp/mips/hurricane/include/usc.h index 4cbbdfd4d9..167eff0949 100644 --- a/c/src/lib/libbsp/mips/hurricane/include/usc.h +++ b/c/src/lib/libbsp/mips/hurricane/include/usc.h @@ -1,32 +1,32 @@ -/* USC constants */
-
-#ifndef _USC_H__
-#define _USC_H__
-
-
-#define USC_REG_BASE (0x1D000000 | 0xA0000000)
-
-/* Internal register addresses */
-#define SYSTEM (USC_REG_BASE + 0x73)
-
-#define INT_CFG0 (USC_REG_BASE + 0xE0)
-#define INT_CFG1 (USC_REG_BASE + 0xE4)
-#define INT_CFG2 (USC_REG_BASE + 0xE8)
-#define INT_STAT (USC_REG_BASE + 0xEC)
-
-#define WD_HBI (USC_REG_BASE + 0xF4)
-
-#define INT_CFG3 (USC_REG_BASE + 0x158)
-
-/* INT_CFGx register masks */
-#define HBI_MASK 0x00200000 /* Heartbeat timer interrupt mask */
-#define WDI_MASK 0x00400000 /* Watchdog timer interrupt mask */
-#define MODE_TOTEM_POLE 0x20000000 /* Totem Pole Output Mode */
-
-/* WD_HBI register bits */
-#define WD_EN 0x00800000 /* Watchdog enable */
-#define HBI_4000_PS 0x00200000 /* Heartbeat timer prescaler = 4000 */
-#define WD_INIT 0x10 /* Watchdog reset pattern (written to byte 2 in WD_HBI register) */
-
-
-#endif /* _USC_H__ */
+/* USC constants */ + +#ifndef _USC_H__ +#define _USC_H__ + + +#define USC_REG_BASE (0x1D000000 | 0xA0000000) + +/* Internal register addresses */ +#define SYSTEM (USC_REG_BASE + 0x73) + +#define INT_CFG0 (USC_REG_BASE + 0xE0) +#define INT_CFG1 (USC_REG_BASE + 0xE4) +#define INT_CFG2 (USC_REG_BASE + 0xE8) +#define INT_STAT (USC_REG_BASE + 0xEC) + +#define WD_HBI (USC_REG_BASE + 0xF4) + +#define INT_CFG3 (USC_REG_BASE + 0x158) + +/* INT_CFGx register masks */ +#define HBI_MASK 0x00200000 /* Heartbeat timer interrupt mask */ +#define WDI_MASK 0x00400000 /* Watchdog timer interrupt mask */ +#define MODE_TOTEM_POLE 0x20000000 /* Totem Pole Output Mode */ + +/* WD_HBI register bits */ +#define WD_EN 0x00800000 /* Watchdog enable */ +#define HBI_4000_PS 0x00200000 /* Heartbeat timer prescaler = 4000 */ +#define WD_INIT 0x10 /* Watchdog reset pattern (written to byte 2 in WD_HBI register) */ + + +#endif /* _USC_H__ */ |