Eliminate unsigned{8|16|32}.

5 files changed, 34 insertions, 34 deletions

diff --git a/c/src/lib/libbsp/mips/csb350/clock/clockdrv.c b/c/src/lib/libbsp/mips/csb350/clock/clockdrv.c
index dc24a76945..e83228c3f4 100644
--- a/c/src/lib/libbsp/mips/csb350/clock/clockdrv.c
+++ b/c/src/lib/libbsp/mips/csb350/clock/clockdrv.c
@@ -18,8 +18,8 @@
 #include <libcpu/au1x00.h>
 #include <rtems/bspIo.h>
 
-unsigned32 tick_interval;
-unsigned32 last_match;
+uint32_t tick_interval;
+uint32_t last_match;
 
 #define CLOCK_VECTOR AU1X00_IRQ_TOY_MATCH2
 
@@ -45,7 +45,7 @@ unsigned32 last_match;
 
 void au1x00_clock_init(void)
 {
-    unsigned32 wakemask;
+    uint32_t wakemask;
     /* Clear the trim register */ 
     AU1X00_SYS_TOYTRIM(AU1X00_SYS_ADDR) = 0; 
     
diff --git a/c/src/lib/libbsp/mips/csb350/include/bsp.h b/c/src/lib/libbsp/mips/csb350/include/bsp.h
index 0118d3aec8..bd7d4b5c5c 100644
--- a/c/src/lib/libbsp/mips/csb350/include/bsp.h
+++ b/c/src/lib/libbsp/mips/csb350/include/bsp.h
@@ -42,8 +42,8 @@ extern "C" {
 /*
  *  Define the interrupt mechanism for Time Test 27
  */
-int assert_sw_irw(unsigned32 irqnum);
-int negate_sw_irw(unsigned32 irqnum);
+int assert_sw_irw(uint32_t irqnum);
+int negate_sw_irw(uint32_t irqnum);
 
 #define MUST_WAIT_FOR_INTERRUPT 0
 
diff --git a/c/src/lib/libbsp/mips/csb350/network/network.c b/c/src/lib/libbsp/mips/csb350/network/network.c
index c3bd64331e..2d59d3a140 100644
--- a/c/src/lib/libbsp/mips/csb350/network/network.c
+++ b/c/src/lib/libbsp/mips/csb350/network/network.c
@@ -94,10 +94,10 @@ typedef struct
     /*
      * register addresses
      */
-    unsigned32                      ctrl_regs;
-    unsigned32                     *en_reg;
-    unsigned32                      int_mask;
-    unsigned32                      int_ctrlr;
+    uint32_t                      ctrl_regs;
+    uint32_t                     *en_reg;
+    uint32_t                      int_mask;
+    uint32_t                      int_ctrlr;
 
     /*
      * device
@@ -147,11 +147,11 @@ void au1x00_emac_rx_daemon (void *arg);
 void au1x00_emac_sendpacket (struct ifnet *ifp, struct mbuf *m);
 void au1x00_emac_stats (au1x00_emac_softc_t *sc);
 static int au1x00_emac_ioctl (struct ifnet *ifp, int command, caddr_t data);
-static void mii_write(au1x00_emac_softc_t *sc, unsigned8 reg, unsigned16 val);
-static void mii_read(au1x00_emac_softc_t *sc, unsigned8 reg, unsigned16 *val);
+static void mii_write(au1x00_emac_softc_t *sc, uint8_t reg, uint16_t val);
+static void mii_read(au1x00_emac_softc_t *sc, uint8_t reg, uint16_t *val);
 static void mii_init(au1x00_emac_softc_t *sc);
 
-static void mii_write(au1x00_emac_softc_t *sc, unsigned8 reg, unsigned16 val)
+static void mii_write(au1x00_emac_softc_t *sc, uint8_t reg, uint16_t val)
 {
     /* wait for the interface to get unbusy */
     while (AU1X00_MAC_MIICTRL(sc->ctrl_regs) & AU1X00_MAC_MIICTRL_MB) {
@@ -170,7 +170,7 @@ static void mii_write(au1x00_emac_softc_t *sc, unsigned8 reg, unsigned16 val)
     }
 }
 
-static void mii_read(au1x00_emac_softc_t *sc, unsigned8 reg, unsigned16 *val)
+static void mii_read(au1x00_emac_softc_t *sc, uint8_t reg, uint16_t *val)
 {
     /* wait for the interface to get unbusy */
     while (AU1X00_MAC_MIICTRL(sc->ctrl_regs) & AU1X00_MAC_MIICTRL_MB) {
@@ -190,7 +190,7 @@ static void mii_read(au1x00_emac_softc_t *sc, unsigned8 reg, unsigned16 *val)
 
 static void mii_init(au1x00_emac_softc_t *sc)
 {
-    unsigned16 data;
+    uint16_t data;
 
     mii_write(sc, 0, 0x8000);     /* reset */
     do {
@@ -458,11 +458,11 @@ void  au1x00_emac_init_hw(au1x00_emac_softc_t *sc)
          * The receive buffer must be aligned with a cache line
          * boundary. 
          */
-        if (mtod(m, unsigned32) & 0x1f) {
-	  unsigned32 *p = mtod(m, unsigned32 *);
-          *p = (mtod(m, unsigned32) + 0x1f) & 0x1f;
+        if (mtod(m, uint32_t) & 0x1f) {
+	  uint32_t *p = mtod(m, uint32_t *);
+          *p = (mtod(m, uint32_t) + 0x1f) & 0x1f;
         }
-        sc->rx_dma[i].addr = (mtod(m, unsigned32) & ~0xe0000000);
+        sc->rx_dma[i].addr = (mtod(m, uint32_t) & ~0xe0000000);
         sc->rx_mbuf[i] = m;
     }
 
@@ -521,7 +521,7 @@ void au1x00_emac_tx_daemon (void *arg)
     struct ifnet *ifp = &sc->arpcom.ac_if;
     struct mbuf *m;
     rtems_event_set events;
-    unsigned32 ic_base;     /* interrupt controller */
+    uint32_t ic_base;     /* interrupt controller */
 
     ic_base = AU1X00_IC0_ADDR;
 
@@ -566,7 +566,7 @@ void au1x00_emac_rx_daemon (void *arg)
     struct mbuf *m;
     struct ether_header *eh;
     rtems_event_set events;
-    unsigned32 status;
+    uint32_t status;
 
     while (1) {
         rtems_bsdnet_event_receive(
@@ -655,8 +655,8 @@ void au1x00_emac_rx_daemon (void *arg)
                  * boundary. 
                  */
 		{
-                  unsigned32 *p = mtod(m, unsigned32 *);
-                  *p = (mtod(m, unsigned32) + 0x1f) & ~0x1f;
+                  uint32_t *p = mtod(m, uint32_t *);
+                  *p = (mtod(m, uint32_t) + 0x1f) & ~0x1f;
 		}
             
             } else {
@@ -667,7 +667,7 @@ void au1x00_emac_rx_daemon (void *arg)
             }
             
             /* set up the receive dma to use the mbuf's cluster */
-            sc->rx_dma[sc->rx_head].addr = (mtod(m, unsigned32) & ~0xe0000000);
+            sc->rx_dma[sc->rx_head].addr = (mtod(m, uint32_t) & ~0xe0000000);
             au_sync();
             sc->rx_mbuf[sc->rx_head] = m;
 
@@ -690,7 +690,7 @@ void au1x00_emac_sendpacket (struct ifnet *ifp, struct mbuf *m)
     struct mbuf *l = NULL;
     unsigned int pkt_offset = 0;
     au1x00_emac_softc_t *sc = (au1x00_emac_softc_t *)ifp->if_softc;
-    unsigned32 txbuf;
+    uint32_t txbuf;
 
     /* Wait for EMAC Transmit Queue to become available. */
     while((sc->tx_dma[sc->tx_head].addr & (AU1X00_MAC_DMA_TXADDR_EN ||
@@ -701,7 +701,7 @@ void au1x00_emac_sendpacket (struct ifnet *ifp, struct mbuf *m)
     /* copy the mbuf chain into the transmit buffer */
     l = m;
 
-    txbuf = (unsigned32)sc->tx_buf[sc->tx_head];
+    txbuf = (uint32_t)sc->tx_buf[sc->tx_head];
     while (l != NULL)
     {
         
@@ -862,7 +862,7 @@ rtems_isr au1x00_emac_isr (rtems_vector_number v)
 
     /* transmit interrupt */
     while (sc->tx_dma[sc->tx_tail].addr & AU1X00_MAC_DMA_TXADDR_DN) {
-        unsigned32 status;
+        uint32_t status;
         tx_flag = 1;
         sc->tx_interrupts++;
         
diff --git a/c/src/lib/libbsp/mips/csb350/startup/bspstart.c b/c/src/lib/libbsp/mips/csb350/startup/bspstart.c
index d17cf943b0..e34baea5dc 100644
--- a/c/src/lib/libbsp/mips/csb350/startup/bspstart.c
+++ b/c/src/lib/libbsp/mips/csb350/startup/bspstart.c
@@ -49,7 +49,7 @@ au1x00_uart_t *uart3 = (au1x00_uart_t *)AU1X00_UART3_ADDR;
  */
  
 void bsp_postdriver_hook(void);
-void bsp_libc_init( void *, unsigned32, int );
+void bsp_libc_init( void *, uint32_t, int );
 
 /*
  *  Function:   bsp_pretasking_hook
@@ -67,8 +67,8 @@ void bsp_libc_init( void *, unsigned32, int );
  
 void bsp_pretasking_hook(void)
 {
-    unsigned32 heap_start;
-    unsigned32 heap_size;
+    uint32_t heap_start;
+    uint32_t heap_size;
 
     /* 
      * Set up the heap. 
@@ -104,10 +104,10 @@ void bsp_start( void )
   /* Place RTEMS workspace at beginning of free memory. */
   BSP_Configuration.work_space_start = (void *)&_bss_free_start;
   
-  free_mem_start = ((unsigned32)&_bss_free_start + 
+  free_mem_start = ((uint32_t)&_bss_free_start + 
                     BSP_Configuration.work_space_size);
   
-  free_mem_end = ((unsigned32)&_sdram_base + (unsigned32)&_sdram_size);
+  free_mem_end = ((uint32_t)&_sdram_base + (uint32_t)&_sdram_size);
   
   mips_set_sr( 0x7f00 );  /* all interrupts unmasked but globally off */
                           /* depend on the IRC to take care of things */
diff --git a/c/src/lib/libbsp/mips/csb350/timer/timer.c b/c/src/lib/libbsp/mips/csb350/timer/timer.c
index 7dd684db1a..d322711dd0 100644
--- a/c/src/lib/libbsp/mips/csb350/timer/timer.c
+++ b/c/src/lib/libbsp/mips/csb350/timer/timer.c
@@ -17,7 +17,7 @@
 #include <bsp.h>
 
 rtems_boolean Timer_driver_Find_average_overhead;
-unsigned32 tstart;
+uint32_t tstart;
 
 void Timer_initialize()
 {
@@ -32,8 +32,8 @@ void Timer_initialize()
 
 int Read_timer()
 {
-  unsigned32  total;
-  unsigned32  cnt;
+  uint32_t  total;
+  uint32_t  cnt;
 
   asm volatile ("mfc0 %0, $9\n" : "=r" (cnt));