2000-11-25 Joel Sherrill <joel@OARcorp.com>

	* The JMR BSP is for a Toshiba TX39 evaluation board but
	can also be used with the mips simulator in gdb.
	* .cvsignore, ChangeLog, Makefile.am, README, bsp_specs,
	configure.in, clock/.cvsignore, clock/Makefile.am,
	clock/clockdrv.c, console/.cvsignore, console/Makefile.am,
	console/console-io.c, include/.cvsignore,
	include/Makefile.am, include/bsp.h, start/.cvsignore,
	start/Makefile.am, start/regs.S, start/start.S,
	startup/.cvsignore, startup/Makefile.am, startup/bspstart.c,
	startup/linkcmds, wrapup/.cvsignore, wrapup/Makefile.am: New files.

4 files changed, 404 insertions, 0 deletions

diff --git a/c/src/lib/libbsp/mips/jmr3904/start/.cvsignore b/c/src/lib/libbsp/mips/jmr3904/start/.cvsignore
new file mode 100644
index 0000000000..282522db03
--- /dev/null
+++ b/c/src/lib/libbsp/mips/jmr3904/start/.cvsignore
@@ -0,0 +1,2 @@
+Makefile
+Makefile.in
diff --git a/c/src/lib/libbsp/mips/jmr3904/start/Makefile.am b/c/src/lib/libbsp/mips/jmr3904/start/Makefile.am
new file mode 100644
index 0000000000..86053b9e99
--- /dev/null
+++ b/c/src/lib/libbsp/mips/jmr3904/start/Makefile.am
@@ -0,0 +1,33 @@
+##
+## $Id$
+##
+
+AUTOMAKE_OPTIONS = foreign 1.4
+
+PGM = $(ARCH)/start.o
+
+S_FILES = start.S
+S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o)
+
+OBJS = $(S_O_FILES)
+
+include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
+include $(top_srcdir)/../../../../../../automake/compile.am
+include $(top_srcdir)/../../../../../../automake/lib.am
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+$(PROJECT_RELEASE)/lib/start$(LIB_VARIANT).o: $(PGM)
+	$(INSTALL_DATA) $< $@
+
+TMPINSTALL_FILES += $(PROJECT_RELEASE)/lib/start$(LIB_VARIANT).o
+
+all-local: $(ARCH) $(OBJS) $(PGM) $(TMPINSTALL_FILES)
+
+.PRECIOUS: $(PGM)
+
+EXTRA_DIST = start.S
+
+include $(top_srcdir)/../../../../../../automake/local.am
diff --git a/c/src/lib/libbsp/mips/jmr3904/start/regs.S b/c/src/lib/libbsp/mips/jmr3904/start/regs.S
new file mode 100644
index 0000000000..c673e5e1c9
--- /dev/null
+++ b/c/src/lib/libbsp/mips/jmr3904/start/regs.S
@@ -0,0 +1,138 @@
+/*
+ * regs.S -- standard MIPS register names from
+ * newlib-1.8.2/libgloss/mips and adapted.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/* Standard MIPS register names: */
+#define zero	$0
+#define z0	$0
+#define v0	$2
+#define v1	$3
+#define a0	$4
+#define a1	$5
+#define a2	$6
+#define a3	$7
+#define t0	$8
+#define t1	$9
+#define t2	$10
+#define t3	$11
+#define t4	$12
+#define t5	$13
+#define t6	$14
+#define t7	$15
+#define s0	$16
+#define s1	$17
+#define s2	$18
+#define s3	$19
+#define s4	$20
+#define s5	$21
+#define s6	$22
+#define s7	$23
+#define t8	$24
+#define t9	$25
+#define k0	$26	/* kernel private register 0 */
+#define k1	$27	/* kernel private register 1 */
+#define gp	$28	/* global data pointer */
+#define sp 	$29	/* stack-pointer */
+#define fp	$30	/* frame-pointer */
+#define ra	$31	/* return address */
+#define pc	$pc	/* pc, used on mips16 */
+
+#define fp0	$f0
+#define fp1	$f1
+
+/* Useful memory constants: */
+#define K0BASE		0x80000000
+#ifndef __mips64
+#define K1BASE		0xA0000000
+#else
+#define K1BASE		0xFFFFFFFFA0000000LL
+#endif
+
+#define PHYS_TO_K1(a)   ((unsigned)(a) | K1BASE)
+
+/* Standard Co-Processor 0 register numbers:
+#define C0_COUNT	$9		/* Count Register */
+#define C0_SR		$12		/* Status Register */
+#define C0_CAUSE	$13		/* last exception description */
+#define C0_EPC		$14		/* Exception error address */
+#define C0_CONFIG	$16		/* CPU configuration */
+
+/* Standard Status Register bitmasks: */
+#define SR_CU1		0x20000000	/* Mark CP1 as usable */
+#define SR_FR		0x04000000	/* Enable MIPS III FP registers */
+#define SR_BEV		0x00400000	/* Controls location of exception vectors */
+#define SR_PE		0x00100000	/* Mark soft reset (clear parity error) */
+
+#define SR_KX		0x00000080	/* Kernel extended addressing enabled */
+#define SR_SX		0x00000040	/* Supervisor extended addressing enabled */
+#define SR_UX		0x00000020	/* User extended addressing enabled */
+
+/* Standard (R4000) cache operations. Taken from "MIPS R4000
+   Microprocessor User's Manual" 2nd edition: */
+
+#define CACHE_I		(0)	/* primary instruction */
+#define CACHE_D		(1)	/* primary data */
+#define CACHE_SI	(2)	/* secondary instruction */
+#define CACHE_SD	(3)	/* secondary data (or combined instruction/data) */
+
+#define INDEX_INVALIDATE		(0)	/* also encodes WRITEBACK if CACHE_D or CACHE_SD */
+#define INDEX_LOAD_TAG			(1)
+#define INDEX_STORE_TAG			(2)
+#define CREATE_DIRTY_EXCLUSIVE		(3)	/* CACHE_D and CACHE_SD only */
+#define HIT_INVALIDATE			(4)
+#define CACHE_FILL			(5)	/* CACHE_I only */
+#define HIT_WRITEBACK_INVALIDATE	(5)	/* CACHE_D and CACHE_SD only */
+#define HIT_WRITEBACK			(6)	/* CACHE_I, CACHE_D and CACHE_SD only */
+#define HIT_SET_VIRTUAL			(7)	/* CACHE_SI and CACHE_SD only */
+
+#define BUILD_CACHE_OP(o,c)		(((o) << 2) | (c))
+
+/* Individual cache operations: */
+#define INDEX_INVALIDATE_I		BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I)
+#define INDEX_WRITEBACK_INVALIDATE_D	BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D)
+#define INDEX_INVALIDATE_SI             BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI)
+#define INDEX_WRITEBACK_INVALIDATE_SD	BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD)
+
+#define INDEX_LOAD_TAG_I		BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I)
+#define INDEX_LOAD_TAG_D                BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D)
+#define INDEX_LOAD_TAG_SI               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI)
+#define INDEX_LOAD_TAG_SD               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD)
+
+#define INDEX_STORE_TAG_I              	BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I)
+#define INDEX_STORE_TAG_D               BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D)
+#define INDEX_STORE_TAG_SI              BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI)
+#define INDEX_STORE_TAG_SD              BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD)
+
+#define CREATE_DIRTY_EXCLUSIVE_D        BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D)
+#define CREATE_DIRTY_EXCLUSIVE_SD       BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD)
+
+#define HIT_INVALIDATE_I                BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I)
+#define HIT_INVALIDATE_D                BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D)
+#define HIT_INVALIDATE_SI               BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI)
+#define HIT_INVALIDATE_SD               BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD)
+
+#define CACHE_FILL_I                    BUILD_CACHE_OP(CACHE_FILL,CACHE_I)
+#define HIT_WRITEBACK_INVALIDATE_D      BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D)
+#define HIT_WRITEBACK_INVALIDATE_SD     BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD)
+
+#define HIT_WRITEBACK_I                 BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I)
+#define HIT_WRITEBACK_D                 BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D)
+#define HIT_WRITEBACK_SD                BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD)
+
+#define HIT_SET_VIRTUAL_SI		BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI)
+#define HIT_SET_VIRTUAL_SD              BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD)
+
+/*> EOF regs.S <*/
diff --git a/c/src/lib/libbsp/mips/jmr3904/start/start.S b/c/src/lib/libbsp/mips/jmr3904/start/start.S
new file mode 100644
index 0000000000..befe8b8b7a
--- /dev/null
+++ b/c/src/lib/libbsp/mips/jmr3904/start/start.S
@@ -0,0 +1,231 @@
+/*
+ * start.S -- startup file for JMR3904 BSP based upon crt0.S from
+ * newlib-1.8.2/libgloss/mips and adapted for RTEMS.
+ *
+ * crt0.S -- startup file for MIPS.
+ *
+ * Copyright (c) 1995, 1996, 1997 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+#ifdef __mips16
+/* This file contains 32 bit assembly code.  */
+	.set nomips16
+#endif
+
+#include "regs.S"
+
+/*
+ * Set up some room for a stack. We just grab a chunk of memory.
+ */
+#define STACK_SIZE  0x4000
+#define GLOBAL_SIZE 0x2000
+
+#define STARTUP_STACK_SIZE	0x0100
+
+/* This is for referencing addresses that are not in the .sdata or
+   .sbss section under embedded-pic, or before we've set up gp.  */
+#ifdef __mips_embedded_pic
+# ifdef __mips64
+#  define LA(t,x) la t,x-PICBASE ; daddu t,s0,t
+# else
+#  define LA(t,x) la t,x-PICBASE ; addu t,s0,t
+# endif
+#else /* __mips_embedded_pic */ 
+# define LA(t,x) la t,x
+#endif /* __mips_embedded_pic */ 
+
+	.comm	__memsize, 12
+	.comm	__lstack, STARTUP_STACK_SIZE
+	.comm   __stackbase,4
+
+	.text
+	.align	2
+
+/* Without the following nop, GDB thinks _start is a data variable.
+ * This is probably a bug in GDB in handling a symbol that is at the
+ * start of the .text section.
+ */
+	nop
+
+	.globl	_start
+	.ent	_start
+_start:
+	.set	noreorder
+#ifdef __mips_embedded_pic
+	PICBASE = .+8
+        bal	PICBASE
+	nop
+	move	s0,$31
+#endif
+
+	li	v0, SR_CU1|SR_PE|SR_FR|SR_KX|SR_SX|SR_UX
+	mtc0	v0, C0_SR
+	mtc0	zero, C0_CAUSE
+
+/* Check for FPU presence */
+#ifndef __mips_soft_float
+/* This doesn't work if there is no FPU.  We get illegal instruction
+   exceptions.  */
+	li	t2,0xAAAA5555
+	mtc1	t2,fp0		/* write to FPR 0 */
+	mtc1	zero,fp1	/* write to FPR 1 */
+	mfc1	t0,fp0
+	mfc1	t1,fp1
+	nop
+	bne	t0,t2,1f	/* check for match */
+	nop
+	bne	t1,zero,1f	/* double check */
+	nop
+#ifndef __mips64  /* Clear the FR bit */
+	li	v0, SR_CU1|SR_PE|SR_KX|SR_SX|SR_UX
+	mtc0	v0, C0_SR
+#endif
+	j	2f
+	nop
+#endif
+1:
+	li	v0, SR_PE|SR_FR|SR_KX|SR_SX|SR_UX
+	mtc0	v0, C0_SR
+2:
+/* Fix high bits, if any, of the PC so that exception handling 
+   doesn't get confused.  */
+	LA (v0, 3f)
+	jr	v0
+	nop
+3:
+	LA (gp, _gp)				# set the global data pointer
+	.end _start
+
+/*
+ * zero out the bss section.
+ */
+	.globl	__memsize
+	.globl	get_mem_info .text
+	.globl	__stack
+	.globl	__global
+	.globl	zerobss
+	.ent	zerobss
+zerobss:
+	LA (v0, _fbss)
+	LA (v1, _end)
+3:
+	sw	zero,0(v0)
+	bltu	v0,v1,3b
+	addiu	v0,v0,4				# executed in delay slot
+
+	la	t0, __lstack			# make a small stack so we
+	addiu	sp, t0, STARTUP_STACK_SIZE	# can run some C code
+	la	a0, __memsize			# get the usable memory size
+	jal	get_mem_info
+	nop
+
+	/* setup the stack pointer */
+	LA (t0, __stack)			# is __stack set ?
+	bne	t0,zero,4f
+	nop
+
+	/* NOTE: a0[0] contains the amount of memory available, and
+	         not the last memory address. */
+	lw	t0,0(a0)			# last address of memory available
+	la	t1,K0BASE			# cached kernel memory
+	addu	t0,t0,t1			# get the end of memory address
+	/* We must subtract 24 bytes for the 3 8 byte arguments to main, in
+	   case main wants to write them back to the stack.  The caller is
+	   supposed to allocate stack space for parameters in registers in
+	   the old MIPS ABIs.  We must do this even though we aren't passing
+	   arguments, because main might be declared to have them. 
+
+	   Some ports need a larger alignment for the stack, so we subtract
+	   32, which satisifes the stack for the arguments and keeps the
+	   stack pointer better aligned.  */
+	subu	t0,t0,32			# and generate a starting stack-pointer
+4:
+	move	sp,t0				# set stack pointer
+	sw	sp,__stackbase			# keep this for future ref
+	.end	zerobss
+
+/*
+ * initialize target specific stuff. Only execute these
+ * functions it they exist.
+ */
+#if 0
+	.globl	hardware_init_hook .text
+	.globl	software_init_hook .text
+	.globl	__do_global_dtors .text
+	.globl	atexit .text
+#endif
+	.globl	exit .text
+	.globl	init
+	.ent	init
+init:
+#if 0
+	LA (t9, hardware_init_hook)		# init the hardware if needed
+	beq	t9,zero,6f
+	nop
+	jal	t9
+	nop
+6:
+	LA (t9, software_init_hook)		# init the hardware if needed
+	beq	t9,zero,7f
+	nop
+	jal	t9
+	nop
+7:
+	LA (a0, __do_global_dtors)
+	jal	atexit
+	nop
+#endif
+
+#ifdef GCRT0
+	.globl	_ftext
+	.globl	_extext
+	LA (a0, _ftext)
+	LA (a1, _etext)
+	jal	monstartup
+	nop
+#endif
+
+	move	a0,zero				# set argc to 0
+	jal	boot_card			# call the program start function
+	nop
+
+	# fall through to the "exit" routine
+	jal	exit				# call libc exit to run the G++
+						# destructors
+	move	a0,v0				# pass through the exit code
+	.end	init
+	
+/*
+ * _exit -- Exit from the application. Normally we cause a user trap
+ *          to return to the ROM monitor for another run. NOTE: This is
+ *	    the only other routine we provide in the crt0.o object, since
+ *          it may be tied to the "_start" routine. It also allows
+ *          executables that contain a complete world to be linked with
+ *          just the crt0.o object.
+ */
+	.globl	_sys_exit
+	.ent _sys_exit
+_sys_exit:
+7:
+#ifdef GCRT0
+	jal	_mcleanup
+	nop
+#endif
+	# break instruction can cope with 0xfffff, but GAS limits the range:
+	break	1023
+	nop
+	b	7b				# but loop back just in-case
+	nop
+	.end _exit
+
+/* EOF crt0.S */