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authorJoel Sherrill <joel.sherrill@OARcorp.com>2000-08-04 22:29:51 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2000-08-04 22:29:51 +0000
commit964717bb56d8580795b956bf280a11c20a0b76fc (patch)
tree6271481ab737832e40f6a684ac4664358b588396 /c/src/lib/libbsp/m68k
parent5b8d82a2a77c569be929cb49ef30c3250df5bd7b (diff)
downloadrtems-964717bb56d8580795b956bf280a11c20a0b76fc.tar.bz2
Now compiles after breaking things with mvme16x_hw.h
Diffstat (limited to 'c/src/lib/libbsp/m68k')
-rw-r--r--c/src/lib/libbsp/m68k/mvme167/include/Makefile.am5
-rw-r--r--c/src/lib/libbsp/m68k/mvme167/include/bsp.h2
2 files changed, 6 insertions, 1 deletions
diff --git a/c/src/lib/libbsp/m68k/mvme167/include/Makefile.am b/c/src/lib/libbsp/m68k/mvme167/include/Makefile.am
index d7e3d0bdb1..5a9f1836af 100644
--- a/c/src/lib/libbsp/m68k/mvme167/include/Makefile.am
+++ b/c/src/lib/libbsp/m68k/mvme167/include/Makefile.am
@@ -16,6 +16,9 @@ $(PROJECT_INCLUDE)/bsp.h: bsp.h
$(PROJECT_INCLUDE)/coverhd.h: coverhd.h
$(INSTALL_DATA) $< $@
+$(PROJECT_INCLUDE)/fatal.h: fatal.h
+ $(INSTALL_DATA) $< $@
+
$(PROJECT_INCLUDE)/mvme16x_hw.h: $(srcdir)/../../mvme162/include/mvme16x_hw.h
$(INSTALL_DATA) $< $@
@@ -27,7 +30,7 @@ $(PROJECT_INCLUDE)/fatal.h: fatal.h
TMPINSTALL_FILES += $(PROJECT_INCLUDE) $(PROJECT_INCLUDE)/bsp.h \
$(PROJECT_INCLUDE)/coverhd.h $(PROJECT_INCLUDE)/mvme16x_hw.h \
- $(PROJECT_INCLUDE)/page_table.h $(PROJECT_INCLUDE)/tod.h
+ $(PROJECT_INCLUDE)/page_table.h $(PROJECT_INCLUDE)/fatal.h
all: $(TMPINSTALL_FILES)
diff --git a/c/src/lib/libbsp/m68k/mvme167/include/bsp.h b/c/src/lib/libbsp/m68k/mvme167/include/bsp.h
index 4ca30810ee..12af9fe2aa 100644
--- a/c/src/lib/libbsp/m68k/mvme167/include/bsp.h
+++ b/c/src/lib/libbsp/m68k/mvme167/include/bsp.h
@@ -48,6 +48,7 @@ extern "C" {
/* i82596 is in mvme16x_hw.h */
/* NVRAM is in mvme16x_hw.h */
+#if 0
/*
* Representation of the PCCchip2
*/
@@ -107,6 +108,7 @@ typedef volatile struct pccchip2_regs_ {
*/
#define pccchip2 ((pccchip2_regs * const) 0xFFF42000)
+#endif
/*
* The MVME167 is equiped with one or two MEMC040 memory controllers at
* 0xFFF43000 and 0xFFF43100. This port assumes that the controllers